of parts of caches

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CPC
G06F12/0895

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0895of parts of caches

Industries

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for performing caching in hashed storage
- Patent number 12,147,347
- Issue date Nov 19, 2024
- Samsung Electronics Co., Ltd.
- Chun-Chu Chen-Jhy Archie Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and method for cleaning valid bits in cache memo...
- Patent number 12,147,350
- Issue date Nov 19, 2024
- Nuvoton Technology Corporation
- Yung-Chi Lan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized scrubbing transactions
- Patent number 12,147,301
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible dictionary sharing for compressed caches
- Patent number 12,135,653
- Issue date Nov 5, 2024
- Advanced Micro Devices, Inc.
- Alexander D. Breslow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Saving track metadata format information for tracks demoted from ca...
- Patent number 12,135,655
- Issue date Nov 5, 2024
- International Business Machines Corporation
- Kyler A. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for sharing a cache line between non-contiguous m...
- Patent number 12,130,736
- Issue date Oct 29, 2024
- Next Silicon Ltd
- Dan Shechter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static power reduction in caches using deterministic naps
- Patent number 12,130,691
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to reduce bandwidth and latency overheads of p...
- Patent number 12,124,371
- Issue date Oct 22, 2024
- Intel Corporation
- Ruchira Sasanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physically-tagged data cache memory that uses translation context t...
- Patent number 12,118,076
- Issue date Oct 15, 2024
- Ventana Micro Systems Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for storing data and tags in different memory arrays
- Patent number 12,079,135
- Issue date Sep 3, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refreshing displays using on-die cache
- Patent number 12,073,806
- Issue date Aug 27, 2024
- Advanced Micro Devices, Inc.
- Ashish Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor micro-operations cache architecture for intermediate inst...
- Patent number 12,061,907
- Issue date Aug 13, 2024
- Nokia Solutions and Networks Oy
- Pranjal Kumar Dutta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag update bus for updated coherence state
- Patent number 12,056,051
- Issue date Aug 6, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for compute enabled cache
- Patent number 12,050,536
- Issue date Jul 30, 2024
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system and method to provide line level tagging of data at...
- Patent number 12,038,845
- Issue date Jul 16, 2024
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for storing cache location information for cache...
- Patent number 12,026,099
- Issue date Jul 2, 2024
- Advanced Micro Devices, Inc.
- Paul James Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling non-correctable errors
- Patent number 12,019,514
- Issue date Jun 25, 2024
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile architecture for graphics operations
- Patent number 12,013,808
- Issue date Jun 18, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,007,907
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE
- Publication number 20240354254
- Publication date Oct 24, 2024
- Lodestar Licensing Group LLC
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PROCESSING REQUEST FOR DATA STORED IN STACK AREA BY USING USE...
- Publication number 20240320159
- Publication date Sep 26, 2024
- Samsung Electronics Co., Ltd.
- Moongyung KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE CACHE STRUCTURE FOR CACHING COMPRESSED AND UNCOMPRESSED DATA
- Publication number 20240320155
- Publication date Sep 26, 2024
- Imagination Technologies Limited
- Ross Martin Torkington
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING NON-CORRECTABLE ERRORS
- Publication number 20240311235
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER, METHOD OF DRIVING MEMORY CONTROLLER, AND MEMORY...
- Publication number 20240264946
- Publication date Aug 8, 2024
- SK HYNIX INC.
- Eun Soo JANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGGING CACHE LINE LIFETIME HINTS WHEN RECORDING BIT-ACCURATE TRACE
- Publication number 20240264951
- Publication date Aug 8, 2024
- Microsoft Technology Licensing, LLC
- Jordi Mola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL PROCESSING HAZARD MITIGATION AVOIDANCE
- Publication number 20240264974
- Publication date Aug 8, 2024
- Ascenium, Inc.
- Peter Foley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY ASSOCIATIVE CACHE LOOKUP WITH MULTIPLE CHOICE HASHING
- Publication number 20240256439
- Publication date Aug 1, 2024
- VMware LLC
- Andreas Georg Nowatzyk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Cooperative Caching between File Systems an...
- Publication number 20240256458
- Publication date Aug 1, 2024
- Dell Products L.P.
- Vasudevan Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-MODE INDEXED CACHE IN A PROCESSOR
- Publication number 20240241832
- Publication date Jul 18, 2024
- Nokia Solutions and Networks Oy
- Pranjal Kumar Dutta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCALLY BIASED CACHE REPLACEMENT FOR CLUSTERED CACHE ARCHITECTURE
- Publication number 20240220420
- Publication date Jul 4, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Packet Cache System and Method
- Publication number 20240193093
- Publication date Jun 13, 2024
- Google LLC
- Jiazhen Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR SUPPORT FOR USING CACHE WAY-LOCKING TO SIMULTANEOUSLY REC...
- Publication number 20240193092
- Publication date Jun 13, 2024
- Microsoft Technology Licensing, LLC
- Jordi Mola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20240184739
- Publication date Jun 6, 2024
- Intel Corporation
- Joydeep RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM WITH CACHED MEMORY MODULE OPERATIONS
- Publication number 20240160587
- Publication date May 16, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODE
- Publication number 20240153548
- Publication date May 9, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE DATA STORAGE METHOD FOR DEEP LEARNING, COMPUTER DEVICE AND S...
- Publication number 20240126684
- Publication date Apr 18, 2024
- Shenzhen Corerain Technologies Co., Ltd.
- Kuen Hung Tsoi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRYPTOGRAPHIC SEPARATION OF MMIO ON DEVICE
- Publication number 20240126691
- Publication date Apr 18, 2024
- Intel Corporation
- Luis S. Kida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ALTERING TRACKING GRANULARITY IN A REGION-BASED CACHE D...
- Publication number 20240111683
- Publication date Apr 4, 2024
- ADVANCED MICRO DEVICES, INC.
- Amit Apte
- G06 - COMPUTING CALCULATING COUNTING

of parts of caches

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus for read-modify-write support in multi-banked...

System and method for performing caching in hashed storage

Integrated circuit and method for cleaning valid bits in cache memo...

Parallelized scrubbing transactions

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Atomic operations and histogram operations in a cache pipeline

Flexible dictionary sharing for compressed caches

Cache coherence shared state suppression

Saving track metadata format information for tracks demoted from ca...

System and method for sharing a cache line between non-contiguous m...

Static power reduction in caches using deterministic naps

Apparatus and method to reduce bandwidth and latency overheads of p...

Physically-tagged data cache memory that uses translation context t...

Methods and apparatus for eviction in dual datapath victim cache sy...

Multi-tile memory management

Compression techniques

Techniques for storing data and tags in different memory arrays

Graphics processor operation scheduling for deterministic latency

Refreshing displays using on-die cache

Methods and apparatus to facilitate read-modify-write support in a...

Cache structure and utilization

Processor micro-operations cache architecture for intermediate inst...

Tag update bus for updated coherence state

Apparatuses and methods for compute enabled cache

Device, system and method to provide line level tagging of data at...

System and method for storing cache location information for cache...

Handling non-correctable errors

Multi-tile architecture for graphics operations

Victim cache with write miss merging

Patents Applicationslast 30 patents

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

CACHE PROCESSING REQUEST FOR DATA STORED IN STACK AREA BY USING USE...

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

FLEXIBLE CACHE STRUCTURE FOR CACHING COMPRESSED AND UNCOMPRESSED DATA

HANDLING NON-CORRECTABLE ERRORS

VICTIM CACHE WITH WRITE MISS MERGING

MEMORY CONTROLLER, METHOD OF DRIVING MEMORY CONTROLLER, AND MEMORY...

LOGGING CACHE LINE LIFETIME HINTS WHEN RECORDING BIT-ACCURATE TRACE

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

PARALLEL PROCESSING HAZARD MITIGATION AVOIDANCE

FULLY ASSOCIATIVE CACHE LOOKUP WITH MULTIPLE CHOICE HASHING

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

Systems and Methods for Cooperative Caching between File Systems an...

MULTI-MODE INDEXED CACHE IN A PROCESSOR

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

LOCALLY BIASED CACHE REPLACEMENT FOR CLUSTERED CACHE ARCHITECTURE

Packet Cache System and Method

PROCESSOR SUPPORT FOR USING CACHE WAY-LOCKING TO SIMULTANEOUSLY REC...

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

DYNAMIC MEMORY RECONFIGURATION

MEMORY SYSTEM WITH CACHED MEMORY MODULE OPERATIONS

SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODE

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

SPARSE DATA STORAGE METHOD FOR DEEP LEARNING, COMPUTER DEVICE AND S...

CRYPTOGRAPHIC SEPARATION OF MMIO ON DEVICE

DYNAMICALLY ALTERING TRACKING GRANULARITY IN A REGION-BASED CACHE D...