Plutonium [Pu]

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CPC
H01L2924/01094

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Current Industry

H01L2924/01094Plutonium [Pu]

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Optoelectronic system
- Patent number 9,748,449
- Issue date Aug 29, 2017
- Epistar Corporation
- Min-Hsun Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device comprising a nanotube-based interface connection...
- Patent number 9,145,294
- Issue date Sep 29, 2015
- STMicroelectronics S.R.L.
- Davide Giuseppe Patti
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Nano memory, light, energy, antenna and strand-based systems and me...
- Patent number 9,117,550
- Issue date Aug 25, 2015
- Bao Q. Tran
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Chip on wafer bonder
- Patent number 9,093,447
- Issue date Jul 28, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Optoelectronic system
- Patent number 8,999,736
- Issue date Apr 7, 2015
- Epistar Corporation
- Min-Hsun Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked electronic device and method of making such an electronic d...
- Patent number 8,860,200
- Issue date Oct 14, 2014
- Commissariat a l'Energie Atomique et aux Energies Alternatives
- Jean Brun
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Post passivation structure for a semiconductor device and packaging...
- Patent number 8,558,383
- Issue date Oct 15, 2013
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip on wafer bonder
- Patent number 8,387,674
- Issue date Mar 5, 2013
- Taiwan Semiconductor Manufacturing Comany, Ltd.
- Chen-Hua Yu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit chip made secure against the action of electroma...
- Patent number 8,138,566
- Issue date Mar 20, 2012
- Gemalto SA
- Robert A. Leydier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device
- Patent number 8,116,100
- Issue date Feb 14, 2012
- Hitachi, Ltd.
- Makoto Saen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thinned image sensor with trench-insulated contact terminals
- Patent number 7,998,780
- Issue date Aug 16, 2011
- E2V Semiconductors
- Pierre Blanchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for magnetically assisted statistical assembly of...
- Patent number 7,956,382
- Issue date Jun 7, 2011
- Massachusetts Institute of Technology
- Clifton G. Fonstad, Jr.
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for mounting an electronic component on a preferably soft su...
- Patent number 7,948,764
- Issue date May 24, 2011
- Oberthur Technologies
- Guy Enouf
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Dice rearrangement package structure using layout process to form a...
- Patent number 7,927,922
- Issue date Apr 19, 2011
- Chipmos Technologies Inc
- Geng-Shin Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die rearrangement package structure using layout process to form a...
- Patent number 7,915,690
- Issue date Mar 29, 2011
- ChipMOS Technologies Inc.
- Geng-Shin Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip stacked structure and the forming method
- Patent number 7,888,172
- Issue date Feb 15, 2011
- ChipMOS Technologies Inc.
- Cheng-Tang Huang
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Chip package structure and the method thereof with adhering the chi...
- Patent number 7,888,783
- Issue date Feb 15, 2011
- ChipMOS Technologies Inc.
- Geng-Shin Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, system, program product for bonding two circuitry-including...
- Patent number 7,875,528
- Issue date Jan 25, 2011
- International Business Machines Corporation
- Douglas C. La Tulipe, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package structure and the method thereof with adhering the chi...
- Patent number 7,700,412
- Issue date Apr 20, 2010
- ChipMOS Technologies Inc.
- Geng-Shin Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano memory, light, energy, antenna and strand-based systems and me...
- Patent number 7,671,398
- Issue date Mar 2, 2010
- Bao Q. Tran
- G11 - INFORMATION STORAGE
Information Patent Grant
Die rearrangement package structure using layout process to form a...
- Patent number 7,662,667
- Issue date Feb 16, 2010
- ChipMOS Technologies Inc.
- Geng-Shin Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 7,626,275
- Issue date Dec 1, 2009
- Mitsubishi Electric Corporation
- Masayasu Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming filling paste structure of WL package
- Patent number 7,476,565
- Issue date Jan 13, 2009
- Advanced Chip Engineering Technology Inc.
- Wen-Kun Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and process for WL-CSP with metal cover
- Patent number 7,468,544
- Issue date Dec 23, 2008
- Advanced Chip Engineering Technology Inc.
- Wen-Kun Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post passivation structure for a semiconductor device and packaging...
- Patent number 7,468,545
- Issue date Dec 23, 2008
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaging structure with coplanar filling paste and dice and with p...
- Patent number 7,400,037
- Issue date Jul 15, 2008
- Advanced Chip Engineering Tachnology Inc.
- Wen-Kun Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
NANO IC packaging
- Patent number 7,375,417
- Issue date May 20, 2008
- Bao Tran
- G11 - INFORMATION STORAGE
Information Patent Grant
Wafer street buffer layer
- Patent number 7,342,296
- Issue date Mar 11, 2008
- Advanced Chip Engineering Technology Inc.
- Wen-Kun Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for field assisted statistical assembly of wafers
- Patent number 7,323,757
- Issue date Jan 29, 2008
- Massachusetts Institute of Technology
- Clifton G. Fonstad, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method of semiconductor device
- Patent number 7,253,040
- Issue date Aug 7, 2007
- Sharp Kabushiki Kaisha
- Takashi Itoga
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
OPTOELECTRONIC SYSTEM
- Publication number 20240421266
- Publication date Dec 19, 2024
- EPISTAR CORPORATION
- Min-Hsun HSIEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTOELECTRONIC SYSTEM
- Publication number 20170324009
- Publication date Nov 9, 2017
- EPISTAR CORPORATION
- Min-Hsun HSIEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ON WAFER BONDER
- Publication number 20130157412
- Publication date Jun 20, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS TO COOL SEMICONDUCTOR
- Publication number 20120299175
- Publication date Nov 29, 2012
- Bao Tran
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE COMPRISING A NANOTUBE-BASED INTERFACE CONNECTION...
- Publication number 20110316173
- Publication date Dec 29, 2011
- STMicroelectronics S.r.l.
- Davide Giuseppe PATTI
- F28 - HEAT EXCHANGE IN GENERAL
Information Patent Application
Dice Rearrangement Package Structure Using Layout Process to Form a...
- Publication number 20110163426
- Publication date Jul 7, 2011
- Geng-Shin SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND MAGNETIC TRANSFER STAMP FOR TRANSFERRING SEMICONDUCTOR D...
- Publication number 20110151588
- Publication date Jun 23, 2011
- COOLEDGE LIGHTING, INC.
- Ian Ashdown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED ELECTRONIC DEVICE AND METHOD OF MAKING SUCH AN ELECTRONIC D...
- Publication number 20110114377
- Publication date May 19, 2011
- Jean Brun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS
- Publication number 20110086468
- Publication date Apr 14, 2011
- Yacine Felk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOUNTED BOARD, MOUNTED BOARD SET, AND PANEL UNIT
- Publication number 20110019125
- Publication date Jan 27, 2011
- Hiroki Nakahama
- G02 - OPTICS
Information Patent Application
METHOD OF DIE REARRANGEMENT PACKAGE STRUCTURE HAVING PATTERNED UNDE...
- Publication number 20110003431
- Publication date Jan 6, 2011
- Cheng-Tang HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE
- Publication number 20100327457
- Publication date Dec 30, 2010
- LIQUID DESIGN SYSTEMS, INC.
- Yoshihiro Mabuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTOELECTRONIC SYSTEM
- Publication number 20100283062
- Publication date Nov 11, 2010
- Min-Hsun HSIEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE AND THE METHOD THEREOF WITH ADHERING THE CHI...
- Publication number 20100155916
- Publication date Jun 24, 2010
- Geng-Shin SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANO MEMORY, LIGHT, ENERGY, ANTENNA AND STRAND-BASED SYSTEMS AND ME...
- Publication number 20100155692
- Publication date Jun 24, 2010
- Bao Q. Tran
- G11 - INFORMATION STORAGE
Information Patent Application
DICING/DIE-BONDING TAPE AND METHOD FOR MANUFACTURING SEMICONDUCTOR...
- Publication number 20100099240
- Publication date Apr 22, 2010
- Kouji Watanabe
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Application
Die Rearrangement Package Structure Using Layout Process to Form a...
- Publication number 20100084759
- Publication date Apr 8, 2010
- Geng-Shin SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20100008058
- Publication date Jan 14, 2010
- Hitachi, Ltd.
- Makoto SAEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Die Rearrangement Package Structure and the Forming Method Thereof
- Publication number 20090309209
- Publication date Dec 17, 2009
- Yu-Ren CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE REARRANGEMENT PACKAGE STRUCTURE AND METHOD THEREOF
- Publication number 20090302465
- Publication date Dec 10, 2009
- Cheng-Tang HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip Stacked Structure and the Forming Method
- Publication number 20090302448
- Publication date Dec 10, 2009
- Cheng-Tang Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultrahigh-Purity Copper and Process for Producing the Same, and Bon...
- Publication number 20090272466
- Publication date Nov 5, 2009
- Nippon Mining & Metals Co., Ltd.
- Yuichiro Shindo
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
THINNED IMAGE SENSOR WITH TRENCH-INSULATED CONTACT TERMINALS
- Publication number 20090263931
- Publication date Oct 22, 2009
- E2V Semiconductors
- Pierre Blanchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip package structure and the method thereof
- Publication number 20090236703
- Publication date Sep 24, 2009
- Geng-Shin SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-chips package structure and the method thereof
- Publication number 20090230527
- Publication date Sep 17, 2009
- Geng-Shin SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for mounting an electronic component on a preferably soft su...
- Publication number 20090200064
- Publication date Aug 13, 2009
- OBERTHUR CARD SYSTEMS SA
- Guy Enouf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managed Memory Component
- Publication number 20090160042
- Publication date Jun 25, 2009
- Entorian Technologies, LP
- James Douglas Wehrly, JR.
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Die rearrangement package structure using layout process to form a...
- Publication number 20090160071
- Publication date Jun 25, 2009
- Geng-Shin SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dice Rearrangement Package Structure Using Layout Process to Form a...
- Publication number 20090160043
- Publication date Jun 25, 2009
- Geng-Shin SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ON WAFER BONDER
- Publication number 20090142903
- Publication date Jun 4, 2009
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS

Plutonium [Pu]

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Optoelectronic system

Electronic device comprising a nanotube-based interface connection...

Nano memory, light, energy, antenna and strand-based systems and me...

Chip on wafer bonder

Optoelectronic system

Stacked electronic device and method of making such an electronic d...

Post passivation structure for a semiconductor device and packaging...

Chip on wafer bonder

Integrated circuit chip made secure against the action of electroma...

Semiconductor device

Thinned image sensor with trench-insulated contact terminals

Method and system for magnetically assisted statistical assembly of...

Method for mounting an electronic component on a preferably soft su...

Dice rearrangement package structure using layout process to form a...

Die rearrangement package structure using layout process to form a...

Chip stacked structure and the forming method

Chip package structure and the method thereof with adhering the chi...

Method, system, program product for bonding two circuitry-including...

Chip package structure and the method thereof with adhering the chi...

Nano memory, light, energy, antenna and strand-based systems and me...

Die rearrangement package structure using layout process to form a...

Semiconductor device

Method for forming filling paste structure of WL package

Structure and process for WL-CSP with metal cover

Post passivation structure for a semiconductor device and packaging...

Packaging structure with coplanar filling paste and dice and with p...

NANO IC packaging

Wafer street buffer layer

System for field assisted statistical assembly of wafers

Fabrication method of semiconductor device

Patents Applicationslast 30 patents

OPTOELECTRONIC SYSTEM

OPTOELECTRONIC SYSTEM

CHIP ON WAFER BONDER

SYSTEMS AND METHODS TO COOL SEMICONDUCTOR

ELECTRONIC DEVICE COMPRISING A NANOTUBE-BASED INTERFACE CONNECTION...

Dice Rearrangement Package Structure Using Layout Process to Form a...

METHOD AND MAGNETIC TRANSFER STAMP FOR TRANSFERRING SEMICONDUCTOR D...

STACKED ELECTRONIC DEVICE AND METHOD OF MAKING SUCH AN ELECTRONIC D...

ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS

MOUNTED BOARD, MOUNTED BOARD SET, AND PANEL UNIT

METHOD OF DIE REARRANGEMENT PACKAGE STRUCTURE HAVING PATTERNED UNDE...

SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE

OPTOELECTRONIC SYSTEM

CHIP PACKAGE STRUCTURE AND THE METHOD THEREOF WITH ADHERING THE CHI...

NANO MEMORY, LIGHT, ENERGY, ANTENNA AND STRAND-BASED SYSTEMS AND ME...

DICING/DIE-BONDING TAPE AND METHOD FOR MANUFACTURING SEMICONDUCTOR...

Die Rearrangement Package Structure Using Layout Process to Form a...

SEMICONDUCTOR DEVICE

Die Rearrangement Package Structure and the Forming Method Thereof

DIE REARRANGEMENT PACKAGE STRUCTURE AND METHOD THEREOF

Chip Stacked Structure and the Forming Method

Ultrahigh-Purity Copper and Process for Producing the Same, and Bon...

THINNED IMAGE SENSOR WITH TRENCH-INSULATED CONTACT TERMINALS

Chip package structure and the method thereof

Multi-chips package structure and the method thereof

Method for mounting an electronic component on a preferably soft su...

Managed Memory Component

Die rearrangement package structure using layout process to form a...

Dice Rearrangement Package Structure Using Layout Process to Form a...

CHIP ON WAFER BONDER