Pre-forming the dual damascene structure in a resist layer

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H01L2221/1021

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00

Current Industry

H01L2221/1021Pre-forming the dual damascene structure in a resist layer

Industries

Patents Grantslast 30 patents

Information Patent Grant
Selective recessing to form a fully aligned via
- Patent number 11,837,501
- Issue date Dec 5, 2023
- TESSERA LLC
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming semiconductor structure
- Patent number 11,764,062
- Issue date Sep 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ping-Hao Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective recessing to form a fully aligned via
- Patent number 11,257,717
- Issue date Feb 22, 2022
- Tessera, Inc.
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming interconnect structures using via holes filled w...
- Patent number 11,024,533
- Issue date Jun 1, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hsi-Wen Tien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective recessing to form a fully aligned via
- Patent number 10,832,952
- Issue date Nov 10, 2020
- Tessera, Inc.
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective recessing to form a fully aligned via
- Patent number 10,636,706
- Issue date Apr 28, 2020
- Tessera, Inc.
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective recessing to form a fully aligned via
- Patent number 10,276,436
- Issue date Apr 30, 2019
- International Business Machines Corporation
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating dual damascene structure
- Patent number 9,748,139
- Issue date Aug 29, 2017
- United Microelectronics Corp.
- En-Chiuan Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of semiconductor integrated circuit fabrication
- Patent number 9,728,408
- Issue date Aug 8, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Ju Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and methods of manufacture thereof
- Patent number 9,484,257
- Issue date Nov 1, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsin-Chieh Yao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via patterning using multiple photo multiple etch
- Patent number 9,412,648
- Issue date Aug 9, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jung-Hau Shiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of multiple exposures with spin castable films
- Patent number 9,058,997
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Martin Burkhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to define multiple layer patterns using a single exposure
- Patent number 8,791,024
- Issue date Jul 29, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yen-Cheng Lu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dual damascene copper process using a selected mask
- Patent number 8,685,853
- Issue date Apr 1, 2014
- Semiconductor Manufacturing International (Shanghai) Corporation
- Fan Chung Tseng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for fabricating dual damascene profiles using sub pixel-voti...
- Patent number 8,652,763
- Issue date Feb 18, 2014
- The Board of Trustees of the University of Illinois
- Kanti Jain
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of fabricating dual damascene structures using a multilevel...
- Patent number 8,536,031
- Issue date Sep 17, 2013
- International Business Machines Corporation
- John C. Arnold
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Pattern formation method
- Patent number 8,506,830
- Issue date Aug 13, 2013
- Kabushiki Kaisha Toshiba
- Kenji Furusho
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Methods and apparatus for forming memory lines and vias in three di...
- Patent number 8,466,068
- Issue date Jun 18, 2013
- Sandisk 3D LLC
- Roy E. Scheuerlein
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of fabricating damascene structures
- Patent number 8,293,638
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Jeffrey P. Gambino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano imprint technique with increased flexibility with respect to a...
- Patent number 8,293,641
- Issue date Oct 23, 2012
- Advanced Micro Devices, Inc.
- Robert Seidel
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of fabricating damascene structures
- Patent number 8,119,522
- Issue date Feb 21, 2012
- International Business Machines Corporation
- Jeffrey P. Gambino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascence copper process using a selected mask
- Patent number 7,989,341
- Issue date Aug 2, 2011
- Semiconductor Manufacturing International (Shanghai) Corporation
- Fan Chung Tseng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Nano imprint technique with increased flexibility with respect to a...
- Patent number 7,928,004
- Issue date Apr 19, 2011
- Advanced Micro Devices, Inc.
- Robert Seidel
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
System and method for imprint lithography to facilitate dual damasc...
- Patent number 7,709,373
- Issue date May 4, 2010
- Advanced Micro Devices, Inc.
- Srikanteswara Dakshina-Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method
- Patent number 7,446,057
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Alexander Bietsch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for imprint lithography to facilitate dual damasc...
- Patent number 7,148,142
- Issue date Dec 12, 2006
- Advanced Micro Devices, Inc.
- Srikanteswara Dakshina-Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene process using a single photo mask
- Patent number 6,858,377
- Issue date Feb 22, 2005
- Nanya Technology Corporation
- Shih-Chi Shu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Damascene structure fabricated using a layer of silicon-based photo...
- Patent number 6,825,562
- Issue date Nov 30, 2004
- Applied Materials Inc.
- Mehul B. Naik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Partial via hard mask open on low-k dual damascene etch with dual h...
- Patent number 6,797,630
- Issue date Sep 28, 2004
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tsang-Jiuh Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dual damascene line structure
- Patent number 6,743,711
- Issue date Jun 1, 2004
- Hynix Semiconductor Inc.
- Kil Ho Kim
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
- Publication number 20240347383
- Publication date Oct 17, 2024
- Adeia Semiconductor Solutions LLC
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE
- Publication number 20230386900
- Publication date Nov 30, 2023
- NANYA TECHNOLOGY CORPORATION
- CHIH-HSUAN YEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
- Publication number 20220181205
- Publication date Jun 9, 2022
- Tessera, Inc.
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
- Publication number 20210082758
- Publication date Mar 18, 2021
- Tessera, Inc.
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING INTERCONNECT STRUCTURES USING VIA HOLES FILLED W...
- Publication number 20200365451
- Publication date Nov 19, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsi-Wen TIEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
- Publication number 20180315654
- Publication date Nov 1, 2018
- International Business Machines Corporation
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
- Publication number 20180315653
- Publication date Nov 1, 2018
- International Business Machines Corporation
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
- Publication number 20180040510
- Publication date Feb 8, 2018
- International Business Machines Corporation
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE
- Publication number 20170229345
- Publication date Aug 10, 2017
- UNITED MICROELECTRONICS CORP.
- En-Chiuan Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Devices and Methods of Manufacture Thereof
- Publication number 20160197012
- Publication date Jul 7, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsin-Chieh Yao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNING METHOD FOR FORMING STAIRCASE STRUCTURE AND METHOD FOR FA...
- Publication number 20140329379
- Publication date Nov 6, 2014
- Samsung Electronics Co., Ltd.
- Chul-Ho Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING DUAL DAMASCENE PROFILES USING SUB PIXEL-VOTI...
- Publication number 20140134404
- Publication date May 15, 2014
- THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
- Kanti JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL ME...
- Publication number 20130264675
- Publication date Oct 10, 2013
- Roy E. Scheuerlein
- B82 - NANO-TECHNOLOGY
Information Patent Application
DUAL DAMASCENE PROCESS AND APPARATUS
- Publication number 20130178068
- Publication date Jul 11, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Chai Der YEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating dual damascene structures using a multilevel...
- Publication number 20130026639
- Publication date Jan 31, 2013
- International Business Machines Corporation
- John C. Arnold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process of Multiple Exposures With Spin Castable Films
- Publication number 20120214311
- Publication date Aug 23, 2012
- International Business Machines Corporation
- Martin Burkhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING DAMASCENE STRUCTURES
- Publication number 20120115303
- Publication date May 10, 2012
- International Business Machines Corporation
- Jeffrey P. Gambino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual Damascene Copper Process Using a Selected Mask
- Publication number 20120108054
- Publication date May 3, 2012
- Semiconductor Manufacturing International (Shanghai) Corporation
- Fan Chung Tseng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
PATTERN FORMATION METHOD
- Publication number 20110290759
- Publication date Dec 1, 2011
- Kenji FURUSHO
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL...
- Publication number 20110204523
- Publication date Aug 25, 2011
- International Business Machines Corporation
- John C. Arnold
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO A...
- Publication number 20110117723
- Publication date May 19, 2011
- Advanced Micro Devices, Inc.
- Robert Seidel
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
THREE-STATE MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE U...
- Publication number 20100311241
- Publication date Dec 9, 2010
- Jae Hyun Kang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR TH...
- Publication number 20100301449
- Publication date Dec 2, 2010
- SanDisk 3D LLC
- Roy E. Scheuerlein
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DI...
- Publication number 20090166682
- Publication date Jul 2, 2009
- ROY E. SCHEUERLEIN
- B82 - NANO-TECHNOLOGY
Information Patent Application
Process of multiple exposures with spin castable film
- Publication number 20090104566
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Martin Burkhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING DUAL DAMASCENE PROFILES USING SUB PIXEL-VOTI...
- Publication number 20090023098
- Publication date Jan 22, 2009
- Kanti Jain
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Dual Damascene Copper Process Using a Selected Mask
- Publication number 20080020565
- Publication date Jan 24, 2008
- Semiconductor Manufacturing International (Shanghai) Corporation
- Fan Chung Tseng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO A...
- Publication number 20080003818
- Publication date Jan 3, 2008
- Robert Seidel
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Fabrication Method
- Publication number 20070275556
- Publication date Nov 29, 2007
- Alexander Bietsch
- B82 - NANO-TECHNOLOGY
Information Patent Application
Single mask process for variable thickness dual damascene structure...
- Publication number 20070212872
- Publication date Sep 13, 2007
- Timothy Harrison Daubenspeck
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Pre-forming the dual damascene structure in a resist layer

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Selective recessing to form a fully aligned via

Method of forming semiconductor structure

Selective recessing to form a fully aligned via

Methods of forming interconnect structures using via holes filled w...

Selective recessing to form a fully aligned via

Selective recessing to form a fully aligned via

Selective recessing to form a fully aligned via

Method of fabricating dual damascene structure

Method of semiconductor integrated circuit fabrication

Semiconductor devices and methods of manufacture thereof

Via patterning using multiple photo multiple etch

Process of multiple exposures with spin castable films

Method to define multiple layer patterns using a single exposure

Dual damascene copper process using a selected mask

Method for fabricating dual damascene profiles using sub pixel-voti...

Method of fabricating dual damascene structures using a multilevel...

Pattern formation method

Methods and apparatus for forming memory lines and vias in three di...

Method of fabricating damascene structures

Nano imprint technique with increased flexibility with respect to a...

Method of fabricating damascene structures

Dual damascence copper process using a selected mask

Nano imprint technique with increased flexibility with respect to a...

System and method for imprint lithography to facilitate dual damasc...

Fabrication method

System and method for imprint lithography to facilitate dual damasc...

Dual damascene process using a single photo mask

Damascene structure fabricated using a layer of silicon-based photo...

Partial via hard mask open on low-k dual damascene etch with dual h...

Method for forming dual damascene line structure

Patents Applicationslast 30 patents

SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE

SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA

SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA

METHODS OF FORMING INTERCONNECT STRUCTURES USING VIA HOLES FILLED W...

SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA

SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA

SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA

METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE

Semiconductor Devices and Methods of Manufacture Thereof

PATTERNING METHOD FOR FORMING STAIRCASE STRUCTURE AND METHOD FOR FA...

METHOD FOR FABRICATING DUAL DAMASCENE PROFILES USING SUB PIXEL-VOTI...

APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL ME...

DUAL DAMASCENE PROCESS AND APPARATUS

Method of fabricating dual damascene structures using a multilevel...

Process of Multiple Exposures With Spin Castable Films

METHOD OF FABRICATING DAMASCENE STRUCTURES

Dual Damascene Copper Process Using a Selected Mask

PATTERN FORMATION METHOD

METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL...

NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO A...

THREE-STATE MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE U...

METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR TH...

METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DI...

Process of multiple exposures with spin castable film

METHOD FOR FABRICATING DUAL DAMASCENE PROFILES USING SUB PIXEL-VOTI...

Dual Damascene Copper Process Using a Selected Mask

NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO A...

Fabrication Method

Single mask process for variable thickness dual damascene structure...