Pre-treatment of the connector or the bonding area

Industry

CPC
H01L2224/82009

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Parent Industries

HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/82009Pre-treatment of the connector or the bonding area

Industries

Patents Grantslast 30 patents

Information Patent Grant
Chip to chip interconnect in encapsulant of molded semiconductor pa...
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- Issue date Jan 31, 2023
- Infineon Technologies AG
- Khay Chwan Saw
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of mounting semiconductor chips, semiconductor device obtain...
- Patent number 9,795,033
- Issue date Oct 17, 2017
- Panasonic Corporation
- Shingo Yoshioka
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional structure for wiring formation
- Patent number 9,082,438
- Issue date Jul 14, 2015
- Panasonic Corporation
- Shingo Yoshioka
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional structure in which wiring is provided on its surface
- Patent number 9,070,393
- Issue date Jun 30, 2015
- Panasonic Corporation
- Shingo Yoshioka
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of mounting semiconductor chips, semiconductor device obtain...
- Patent number 8,901,728
- Issue date Dec 2, 2014
- Panasonic Corporation
- Shingo Yoshioka
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor die having fine pitch electrical interconnects
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- Issue date Sep 9, 2014
- Invensas Corporation
- Keith Lake Barrie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of mounting semiconductor chips, semiconductor device obtain...
- Patent number 8,759,148
- Issue date Jun 24, 2014
- Panasonic Corporation
- Shingo Yoshioka
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of mounting semiconductor chips, semiconductor device obtain...
- Patent number 8,482,137
- Issue date Jul 9, 2013
- Panasonic Corporation
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- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL STRUCTURE IN WHICH WIRING IS PROVIDED ON ITS SURFACE
- Publication number 20140183751
- Publication date Jul 3, 2014
- PANASONIC CORPORATION
- Shingo YOSHIOKA
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL STRUCTURE FOR WIRING FORMATION
- Publication number 20140182887
- Publication date Jul 3, 2014
- PANASONIC CORPORATION
- Shingo YOSHIOKA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...
- Publication number 20140097004
- Publication date Apr 10, 2014
- PANASONIC CORPORATION
- Shingo YOSHIOKA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...
- Publication number 20140090876
- Publication date Apr 3, 2014
- PANASONIC CORPORATION
- Shingo YOSHIOKA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...
- Publication number 20130200522
- Publication date Aug 8, 2013
- PANASONIC CORPORATION
- Shingo YOSHIOKA
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor die having fine pitch electrical interconnects
- Publication number 20120248607
- Publication date Oct 4, 2012
- Vertical Circuits, Inc.
- Keith Lake Barrie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...
- Publication number 20110281138
- Publication date Nov 17, 2011
- Panasonic Electric Works Co., Ltd.
- Shingo Yoshioka
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Pre-treatment of the connector or the bonding area

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Chip to chip interconnect in encapsulant of molded semiconductor pa...

Method of mounting semiconductor chips, semiconductor device obtain...

Three-dimensional structure for wiring formation

Three-dimensional structure in which wiring is provided on its surface

Method of mounting semiconductor chips, semiconductor device obtain...

Semiconductor die having fine pitch electrical interconnects

Method of mounting semiconductor chips, semiconductor device obtain...

Method of mounting semiconductor chips, semiconductor device obtain...

Patents Applicationslast 30 patents

THREE-DIMENSIONAL STRUCTURE IN WHICH WIRING IS PROVIDED ON ITS SURFACE

THREE-DIMENSIONAL STRUCTURE FOR WIRING FORMATION

METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...

METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...

METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...

Semiconductor die having fine pitch electrical interconnects

METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAIN...