Scan latches or cell details

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CPC
G01R31/318541

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318541Scan latches or cell details

Industries

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Patents Grantslast 30 patents

Information Patent Grant
TSV testing
- Patent number 12,163,998
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method which can reduce circuit area while performing te...
- Patent number 12,158,500
- Issue date Dec 3, 2024
- Realtek Semiconductor Corp.
- Yu-Cheng Lo
- G01 - MEASURING TESTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit including constant-0 flip flops reconfigured to...
- Patent number 12,130,330
- Issue date Oct 29, 2024
- QUALCOMM Incorporated
- Paul Policke
- G01 - MEASURING TESTING
Information Patent Grant
Multiplexer for SDFQ having differently-sized scan and data transis...
- Patent number 12,099,090
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip-flop circuitry
- Patent number 12,078,679
- Issue date Sep 3, 2024
- Samsung Electronics Co., Ltd.
- Byoung Gon Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan flip-flops with pre-setting combinational logic
- Patent number 12,066,489
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Grant
Flip-flops and scan chain circuits including the same
- Patent number 12,044,733
- Issue date Jul 23, 2024
- Samsung Electronics Co., Ltd.
- Byounggon Kang
- G01 - MEASURING TESTING
Information Patent Grant
Calibration data generation circuit and associated method
- Patent number 12,032,020
- Issue date Jul 9, 2024
- Realtek Semiconductor Corporation
- Chun-Yi Kuo
- G01 - MEASURING TESTING
Information Patent Grant
Flip-flop with delineated layout for reduced footprint
- Patent number 12,015,409
- Issue date Jun 18, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chi-Lin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuit and test method
- Patent number 11,988,711
- Issue date May 21, 2024
- Realtek Semiconductor Corporation
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Grant
Multi-bit flip-flop and integrated circuit including the same
- Patent number 11,988,712
- Issue date May 21, 2024
- Samsung Electronics Co., Ltd.
- Chunghee Kim
- G01 - MEASURING TESTING
Information Patent Grant
Process for scan chain in a memory
- Patent number 11,971,448
- Issue date Apr 30, 2024
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-bit flip-flop circuit with reduced area and reduced wire comp...
- Patent number 11,936,384
- Issue date Mar 19, 2024
- Samsung Electronics Co., Ltd.
- Wonhyun Choi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Secured scan access for a device including a scan chain
- Patent number 11,927,633
- Issue date Mar 12, 2024
- Texas Instruments Incorporated
- Mudasir Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit, test assembly and method for testing an integra...
- Patent number 11,874,325
- Issue date Jan 16, 2024
- Infineon Technologies AG
- Tobias Kilian
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing method and apparatus
- Patent number 11,835,573
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiplexer for SDFQ having differently-sized scan and data transis...
- Patent number 11,821,947
- Issue date Nov 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split-scan sense amplifier flip-flop
- Patent number 11,789,075
- Issue date Oct 17, 2023
- Advanced Micro Devices, Inc.
- Nur Mohammad Baksh
- G01 - MEASURING TESTING
Information Patent Grant
Scan test device and scan test method
- Patent number 11,789,073
- Issue date Oct 17, 2023
- Realtek Semiconductor Corporation
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Grant
Flip flop circuit
- Patent number 11,764,766
- Issue date Sep 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Chia Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 11,747,398
- Issue date Sep 5, 2023
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device and semiconductor device examination method
- Patent number 11,740,287
- Issue date Aug 29, 2023
- Kioxia Corporation
- Isao Ooigawa
- G01 - MEASURING TESTING
Information Patent Grant
Flip-flop circuitry
- Patent number 11,726,141
- Issue date Aug 15, 2023
- Samsung Electronics Co., Ltd.
- Byoung Gon Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-bit flip-flop with power saving feature
- Patent number 11,714,125
- Issue date Aug 1, 2023
- Mediatek Inc.
- Kin-Hooi Dia
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain for memory with reduced power consumption
- Patent number 11,693,056
- Issue date Jul 4, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- G01 - MEASURING TESTING
Information Patent Grant
Signal toggling detection and correction circuit
- Patent number 11,686,769
- Issue date Jun 27, 2023
- NXP B.V.
- Shikhar Makkar
- G01 - MEASURING TESTING
Information Patent Grant
Scalable scan architecture for multi-circuit block arrays
- Patent number 11,639,962
- Issue date May 2, 2023
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of updating firmware of chip stably and effectively, firmwar...
- Patent number 11,630,732
- Issue date Apr 18, 2023
- Fulian Precision Electronics (Tianjin) Co., LTD.
- Li-Yun Hao
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
- Publication number 20240418776
- Publication date Dec 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Ashraf MOHAMMED
- G01 - MEASURING TESTING
Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
D FLIP-FLOP HAVING MULTIPLEXER FUNCTION
- Publication number 20240388281
- Publication date Nov 21, 2024
- SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
- Zhijun FAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20240369629
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Flip-Flops With Pre-Setting Combinational Logic
- Publication number 20240361383
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Application
Configurable Storage Circuits And Methods
- Publication number 20240337692
- Publication date Oct 10, 2024
- Intel Corporation
- Rajiv Kumar
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT TESTING
- Publication number 20240319273
- Publication date Sep 26, 2024
- NORDIC SEMICONDUCTOR ASA
- Linda KRISTOFFERSEN
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...
- Publication number 20240295604
- Publication date Sep 5, 2024
- STMicroelectronics International N.V.
- Gianluca TORTORA
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN
- Publication number 20240241174
- Publication date Jul 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mudasir KAWOOSA
- G01 - MEASURING TESTING
Information Patent Application
Design For Test For Source Synchronous Interfaces
- Publication number 20240192271
- Publication date Jun 13, 2024
- NXP B.V.
- Akhil Garg
- G01 - MEASURING TESTING
Information Patent Application
META-STABILITY-FREE TWO-CLOCK-DOMAIN SYNCHRONOUS LATCH
- Publication number 20240146285
- Publication date May 2, 2024
- VIETTEL GROUP
- Thai Ha Le
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT HAVING TEST CIRCUITRY FOR MEMORY SUB-SYSTEMS
- Publication number 20240142520
- Publication date May 2, 2024
- NXP USA, Inc.
- Alexander Hoefler
- G01 - MEASURING TESTING
Information Patent Application
SCAN FLIP-FLOP, SCAN CHAIN CIRCUIT INCLUDING THE SAME, AND CONTROL...
- Publication number 20240142521
- Publication date May 2, 2024
- Research & Business Foundation Sungkyunkwan University
- Changyoun Im
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER FLIP-FLOP
- Publication number 20240128952
- Publication date Apr 18, 2024
- Samsung Electronics Co., Ltd.
- Byounggon Kang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN
- Publication number 20240103078
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mudasir KAWOOSA
- G01 - MEASURING TESTING
Information Patent Application
TSV TESTING
- Publication number 20240094280
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME
- Publication number 20240061039
- Publication date Feb 22, 2024
- Samsung Electronics Co., Ltd.
- Byounggon Kang
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20230408582
- Publication date Dec 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip Flop Circuit
- Publication number 20230387895
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Flip Flop Circuit
- Publication number 20230378941
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD
- Publication number 20230358806
- Publication date Nov 9, 2023
- STMicroelectronics S.r.l.
- Marco CASARSA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FLIP-FLOP CIRCUITRY
- Publication number 20230333162
- Publication date Oct 19, 2023
- Samsung Electronics Co., Ltd.
- Byoung Gon Kang
- G01 - MEASURING TESTING
Information Patent Application
Process for Scan Chain in a Memory
- Publication number 20230296672
- Publication date Sep 21, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TEST CIRCUIT AND TEST METHOD
- Publication number 20230288478
- Publication date Sep 14, 2023
- REALTEK SEMICONDUCTOR CORPORATION
- PO-LIN CHEN
- G01 - MEASURING TESTING
Information Patent Application
CALIBRATION DATA GENERATION CIRCUIT AND ASSOCIATED METHOD
- Publication number 20230236246
- Publication date Jul 27, 2023
- REALTEK SEMICONDUCTOR CORPORATION
- CHUN-YI KUO
- G01 - MEASURING TESTING
Information Patent Application
SIGNAL TOGGLING DETECTION AND CORRECTION CIRCUIT
- Publication number 20230213580
- Publication date Jul 6, 2023
- NXP B.V.
- Shikhar Makkar
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain for Memory with Reduced Power Consumption
- Publication number 20230194607
- Publication date Jun 22, 2023
- Ceremorphic, Inc.
- Shakti SINGH
- G01 - MEASURING TESTING
Information Patent Application
Data Gating Using Scan Enable Pin
- Publication number 20230194606
- Publication date Jun 22, 2023
- Apple Inc.
- FNU Rajeev Kumar
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD WHICH CAN REDUCE CIRCUIT AREA WHILE PERFORMING TE...
- Publication number 20230092349
- Publication date Mar 23, 2023
- Realtek Semiconductor Corp.
- Yu-Cheng Lo
- G01 - MEASURING TESTING

Scan latches or cell details

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

TSV testing

System and method which can reduce circuit area while performing te...

TVF transition coverage with self-test and production-test time red...

Integrated circuit including constant-0 flip flops reconfigured to...

Multiplexer for SDFQ having differently-sized scan and data transis...

Flip-flop circuitry

Scan flip-flops with pre-setting combinational logic

Flip-flops and scan chain circuits including the same

Calibration data generation circuit and associated method

Flip-flop with delineated layout for reduced footprint

Test circuit and test method

Multi-bit flip-flop and integrated circuit including the same

Process for scan chain in a memory

Single “A” latch with an array of “B” latches

Multi-bit flip-flop circuit with reduced area and reduced wire comp...

Secured scan access for a device including a scan chain

Integrated circuit, test assembly and method for testing an integra...

TSV testing method and apparatus

Multiplexer for SDFQ having differently-sized scan and data transis...

Split-scan sense amplifier flip-flop

Scan test device and scan test method

Flip flop circuit

Scan chain circuit and corresponding method

Semiconductor device and semiconductor device examination method

Flip-flop circuitry

Multi-bit flip-flop with power saving feature

Scan chain for memory with reduced power consumption

Signal toggling detection and correction circuit

Scalable scan architecture for multi-circuit block arrays

Method of updating firmware of chip stably and effectively, firmwar...

Patents Applicationslast 30 patents

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

D FLIP-FLOP HAVING MULTIPLEXER FUNCTION

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

Scan Flip-Flops With Pre-Setting Combinational Logic

Configurable Storage Circuits And Methods

CIRCUIT TESTING

INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN

Design For Test For Source Synchronous Interfaces

META-STABILITY-FREE TWO-CLOCK-DOMAIN SYNCHRONOUS LATCH

INTEGRATED CIRCUIT HAVING TEST CIRCUITRY FOR MEMORY SUB-SYSTEMS

SCAN FLIP-FLOP, SCAN CHAIN CIRCUIT INCLUDING THE SAME, AND CONTROL...

LOW POWER FLIP-FLOP

SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN

TSV TESTING

FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

Flip Flop Circuit

Flip Flop Circuit

SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD

FLIP-FLOP CIRCUITRY

Process for Scan Chain in a Memory

TEST CIRCUIT AND TEST METHOD

CALIBRATION DATA GENERATION CIRCUIT AND ASSOCIATED METHOD

SIGNAL TOGGLING DETECTION AND CORRECTION CIRCUIT

Scan Chain for Memory with Reduced Power Consumption

Data Gating Using Scan Enable Pin

SYSTEM AND METHOD WHICH CAN REDUCE CIRCUIT AREA WHILE PERFORMING TE...