Test of Modular systems

Industry

CPC
G01R31/318505

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318505Test of Modular systems

Industries

Patents Grantslast 30 patents

Information Patent Grant
Signal generator and a method for controlling the signal generator
- Patent number 11,762,016
- Issue date Sep 19, 2023
- Anritsu Corporation
- Jesse Paulo Valencia Macabasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TSV testing using test circuits and grounding means
- Patent number 11,644,503
- Issue date May 9, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing using test circuits and grounding means
- Patent number 11,467,210
- Issue date Oct 11, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with JTAG port, tap linking module, and off-chip...
- Patent number 11,150,297
- Issue date Oct 19, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for inter-die functional testing of an...
- Patent number 11,105,854
- Issue date Aug 31, 2021
- Intel Corporation
- Lakshminarayana Pappu
- G01 - MEASURING TESTING
Information Patent Grant
Integrated laser voltage probe pad for measuring DC or low frequenc...
- Patent number 11,079,432
- Issue date Aug 3, 2021
- NXP B.V.
- Pieter Gustaaf Nierop
- G01 - MEASURING TESTING
Information Patent Grant
TSVS, test circuits, scan cells, comparators, electrical source, an...
- Patent number 10,901,034
- Issue date Jan 26, 2021
- Texas Instruments Incorporated
- Lee D. Whetsei
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit on chip instrument controller
- Patent number 10,871,517
- Issue date Dec 22, 2020
- NXP B.V.
- Johannes Petrus Wilhelmus van Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible manufacturing flow enabled by adaptive binning system
- Patent number 10,761,137
- Issue date Sep 1, 2020
- Xilinx, Inc.
- Lee N. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with JTAG port, TAP linking module, and off chip...
- Patent number 10,690,720
- Issue date Jun 23, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC TSV scan cells with sensed and reference voltage inputs
- Patent number 10,605,866
- Issue date Mar 31, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device
- Patent number 10,445,206
- Issue date Oct 15, 2019
- Renesas Electronics Corporation
- Mitsuhiko Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient test architecture for multi-die chips
- Patent number 10,429,441
- Issue date Oct 1, 2019
- QUALCOMM Incorporated
- Tapan Jyoti Chakraborty
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device
- Patent number 10,396,802
- Issue date Aug 27, 2019
- Renesas Electronics Corporation
- Mitsuhiko Igarashi
- G01 - MEASURING TESTING
Information Patent Grant
Register array having groups of latches with single test latch test...
- Patent number 10,365,328
- Issue date Jul 30, 2019
- GLOBALFOUNDRIES Inc.
- Jian Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TSV first ends connected to test stimulus and response signals
- Patent number 10,267,856
- Issue date Apr 23, 2019
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Selectively uncoupling tap and coupling OCI responsive to link inst...
- Patent number 10,036,777
- Issue date Jul 31, 2018
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing TSV with current/voltage source, resistor, comparator, and...
- Patent number 9,880,222
- Issue date Jan 30, 2018
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit and method for controlling test circuit
- Patent number 9,835,685
- Issue date Dec 5, 2017
- Fujitsu Limited
- Gen Oshiyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-step interconnect testing of semiconductor dies
- Patent number 9,678,142
- Issue date Jun 13, 2017
- IMEC
- Julien Ryckaert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Off-chip tap interface control with instruction register, multiplex...
- Patent number 9,575,121
- Issue date Feb 21, 2017
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Monolithic integrated circuit die having modular die regions stitch...
- Patent number 9,547,034
- Issue date Jan 17, 2017
- Xilinx, Inc.
- Rafael C. Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit chip and multi-chip system including the same
- Patent number 9,490,032
- Issue date Nov 8, 2016
- SK Hynix Inc.
- Sang-Jin Byeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing of thru-silicon vias
- Patent number 9,435,846
- Issue date Sep 6, 2016
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING
Information Patent Grant
TSVs connected to ground and combined stimulus and testing leads
- Patent number 9,383,403
- Issue date Jul 5, 2016
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Linking circuitry for IC TAP, core TAP, off-chip TAP interface
- Patent number 9,188,639
- Issue date Nov 17, 2015
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device
- Patent number 9,157,959
- Issue date Oct 13, 2015
- Renesas Electronics Corporation
- Koichi Ishimi
- G01 - MEASURING TESTING
Information Patent Grant
Multi-chip package and interposer with signal line compression
- Patent number 9,153,508
- Issue date Oct 6, 2015
- Rambus Inc.
- Torsten Partsch
- G01 - MEASURING TESTING
Information Patent Grant
Probeless testing of pad buffers on wafer
- Patent number 9,021,322
- Issue date Apr 28, 2015
- Texas Instrument Incorporated
- Lee D. Whetsel
- G11 - INFORMATION STORAGE
Information Patent Grant
Accelerating scan test by re-using response data as stimulus data a...
- Patent number 9,015,544
- Issue date Apr 21, 2015
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Array of Through-Silicon Via Contact Points on a Semiconductor Die
- Publication number 20230273258
- Publication date Aug 31, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS
- Publication number 20220317182
- Publication date Oct 6, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SIGNAL GENERATOR AND A METHOD FOR CONTROLLING THE SIGNAL GENERATOR
- Publication number 20220236327
- Publication date Jul 28, 2022
- Anritsu Corporation
- Jesse Paulo Valencia MACABASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS
- Publication number 20210102996
- Publication date Apr 8, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFFCHIP...
- Publication number 20200278390
- Publication date Sep 3, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED LASER VOLTAGE PROBE PAD FOR MEASURING DC OR LOW FREQUENC...
- Publication number 20200264232
- Publication date Aug 20, 2020
- NPX B.V.
- Pieter Gustaaf Nierop
- G01 - MEASURING TESTING
Information Patent Application
TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS
- Publication number 20200191867
- Publication date Jun 18, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS
- Publication number 20190195945
- Publication date Jun 27, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TEST...
- Publication number 20190004114
- Publication date Jan 3, 2019
- GLOBALFOUNDRIES INC.
- JIAN SUN
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFFCHIP...
- Publication number 20180306859
- Publication date Oct 25, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS
- Publication number 20180106863
- Publication date Apr 19, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20180089052
- Publication date Mar 29, 2018
- RENESAS ELECTRONICS CORPORATION
- Mitsuhiko IGARASHI
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20160003910
- Publication date Jan 7, 2016
- RENESAS ELECTRONICS CORPORATION
- Koichi ISHIMI
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT CHIP AND MULTI-CHIP SYSTEM INCLUDING THE SAME
- Publication number 20140354311
- Publication date Dec 4, 2014
- SK HYNIX INC.
- Sang-Jin BYEON
- G01 - MEASURING TESTING
Information Patent Application
Testing of Thru-Silicon Vias
- Publication number 20140347089
- Publication date Nov 27, 2014
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING
Information Patent Application
TWO-STEP INTERCONNECT TESTING OF SEMICONDUCTOR DIES
- Publication number 20140300379
- Publication date Oct 9, 2014
- IMEC
- Julien RYCKAERT
- G01 - MEASURING TESTING
Information Patent Application
Multi-core processor having disabled cores
- Publication number 20140304449
- Publication date Oct 9, 2014
- PACT XPP TECHNOLOGIES AG
- Martin Vorbach
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP...
- Publication number 20140215283
- Publication date Jul 31, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
MULTI-CHIP PACKAGE AND INTERPOSER WITH SIGNAL LINE COMPRESSION
- Publication number 20140197409
- Publication date Jul 17, 2014
- RAMBUS INC.
- Torsten Partsch
- G01 - MEASURING TESTING
Information Patent Application
PROBELESS TESTING OF PAD BUFFERS ON WAFER
- Publication number 20140082445
- Publication date Mar 20, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA A...
- Publication number 20140082443
- Publication date Mar 20, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
CHIP APPLIED TO SERIAL TRANSMISSION SYSTEM AND ASSOCIATED FAIL SAFE...
- Publication number 20130346821
- Publication date Dec 26, 2013
- Silicon Touch Technology Inc.
- Chi-Yuan Chin
- G01 - MEASURING TESTING
Information Patent Application
PROBELESS TESTING OF PAD BUFFERS ON WAFER
- Publication number 20130254607
- Publication date Sep 26, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TSV Testing Using Test Circuits and Grounding Means
- Publication number 20130249590
- Publication date Sep 26, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP...
- Publication number 20130151916
- Publication date Jun 13, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20130103988
- Publication date Apr 25, 2013
- RENESAS ELECTRONICS CORPORATION
- Koichi ISHIMI
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR DIE TESTING ON WAFER
- Publication number 20130049804
- Publication date Feb 28, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
PROBELESS TESTING OF PAD BUFFERS ON WAFER
- Publication number 20120317451
- Publication date Dec 13, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP...
- Publication number 20120144254
- Publication date Jun 7, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROBELESS TESTING OF PAD BUFFERS ON WAFER
- Publication number 20120117434
- Publication date May 10, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Test of Modular systems

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Signal generator and a method for controlling the signal generator

TSV testing using test circuits and grounding means

TSV testing using test circuits and grounding means

Integrated circuit with JTAG port, tap linking module, and off-chip...

System, apparatus and method for inter-die functional testing of an...

Integrated laser voltage probe pad for measuring DC or low frequenc...

TSVS, test circuits, scan cells, comparators, electrical source, an...

Integrated circuit on chip instrument controller

Flexible manufacturing flow enabled by adaptive binning system

Integrated circuit with JTAG port, TAP linking module, and off chip...

IC TSV scan cells with sensed and reference voltage inputs

Semiconductor device

Efficient test architecture for multi-die chips

Semiconductor device

Register array having groups of latches with single test latch test...

TSV first ends connected to test stimulus and response signals

Selectively uncoupling tap and coupling OCI responsive to link inst...

Testing TSV with current/voltage source, resistor, comparator, and...

Test circuit and method for controlling test circuit

Two-step interconnect testing of semiconductor dies

Off-chip tap interface control with instruction register, multiplex...

Monolithic integrated circuit die having modular die regions stitch...

Integrated circuit chip and multi-chip system including the same

Testing of thru-silicon vias

TSVs connected to ground and combined stimulus and testing leads

Linking circuitry for IC TAP, core TAP, off-chip TAP interface

Semiconductor device

Multi-chip package and interposer with signal line compression

Probeless testing of pad buffers on wafer

Accelerating scan test by re-using response data as stimulus data a...

Patents Applicationslast 30 patents

Array of Through-Silicon Via Contact Points on a Semiconductor Die

TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS

SIGNAL GENERATOR AND A METHOD FOR CONTROLLING THE SIGNAL GENERATOR

TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS

INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFFCHIP...

INTEGRATED LASER VOLTAGE PROBE PAD FOR MEASURING DC OR LOW FREQUENC...

TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS

TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS

REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TEST...

INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFFCHIP...

TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

INTEGRATED CIRCUIT CHIP AND MULTI-CHIP SYSTEM INCLUDING THE SAME

Testing of Thru-Silicon Vias

TWO-STEP INTERCONNECT TESTING OF SEMICONDUCTOR DIES

Multi-core processor having disabled cores

INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP...

MULTI-CHIP PACKAGE AND INTERPOSER WITH SIGNAL LINE COMPRESSION

PROBELESS TESTING OF PAD BUFFERS ON WAFER

ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA A...

CHIP APPLIED TO SERIAL TRANSMISSION SYSTEM AND ASSOCIATED FAIL SAFE...

PROBELESS TESTING OF PAD BUFFERS ON WAFER

TSV Testing Using Test Circuits and Grounding Means

INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP...

SEMICONDUCTOR DEVICE

METHOD AND APPARATUS FOR DIE TESTING ON WAFER

PROBELESS TESTING OF PAD BUFFERS ON WAFER

INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP...

PROBELESS TESTING OF PAD BUFFERS ON WAFER