the second connecting process involving a build-up interconnect

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H01L2224/92164

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/92164the second connecting process involving a build-up interconnect

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Patents Grantslast 30 patents

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Chip package structure and manufacturing method thereof
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- Issue date Jun 14, 2022
- Unimicron Technology Corp.
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged electronic devices with top terminations
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- Issue date May 24, 2022
- NXP USA, INC.
- Fernando A. Santos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor devices, corresponding device...
- Patent number 11,133,242
- Issue date Sep 28, 2021
- STMicroelectronics S.r.l.
- Michele Derai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package for a mems sensor device and corresponding manu...
- Patent number 10,882,738
- Issue date Jan 5, 2021
- STMicroelectronics (Malta) Ltd.
- Conrad Cachia
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of manufacturing semiconductor devices, corresponding device...
- Patent number 10,818,578
- Issue date Oct 27, 2020
- STMicroelectronics S.r.l.
- Michele Derai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing packaged electronic devices with top termi...
- Patent number 10,375,833
- Issue date Aug 6, 2019
- NXP USA, INC.
- Lakshminarayan Viswanathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double-sided semiconductor package and dual-mold method of making same
- Patent number 10,115,672
- Issue date Oct 30, 2018
- STATS ChipPAC Pte. Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interposer frame electri...
- Patent number 9,966,335
- Issue date May 8, 2018
- STATS ChipPAC Pte. Ltd.
- NamJu Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double-sided semiconductor package and dual-mold method of making same
- Patent number 9,893,017
- Issue date Feb 13, 2018
- STATS ChipPAC Pte. Ltd.
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package and method for forming the same
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- Issue date Sep 12, 2017
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- Chien-Hung Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit substrate interconnect
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- Issue date Jan 3, 2017
- Texas Instruments Incorporated
- Yohei Koto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stack packages and methods of manufacturing the same
- Patent number 9,343,439
- Issue date May 17, 2016
- SK hynix Inc.
- Jin Ho Bae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stack packages and methods of manufacturing the same
- Patent number 9,196,607
- Issue date Nov 24, 2015
- SK Hynix Inc.
- Jin Ho Bae
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20210118839
- Publication date Apr 22, 2021
- Unimicron Technology Corp.
- Pu-Ju Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE...
- Publication number 20210013134
- Publication date Jan 14, 2021
- STMicroelectronics S.r.l.
- Michele DERAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double-Sided Semiconductor Package and Dual-Mold Method of Making Same
- Publication number 20180076142
- Publication date Mar 15, 2018
- STATS ChipPAC Pte Ltd.
- Il Kwon Shim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME
- Publication number 20140361441
- Publication date Dec 11, 2014
- SK HYNIX INC.
- Jin Ho BAE
- H01 - BASIC ELECTRIC ELEMENTS

the second connecting process involving a build-up interconnect

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Chip package structure and manufacturing method thereof

Packaged electronic devices with top terminations

Method of manufacturing semiconductor devices, corresponding device...

Wafer level package for a mems sensor device and corresponding manu...

Method of manufacturing semiconductor devices, corresponding device...

Methods of manufacturing packaged electronic devices with top termi...

Double-sided semiconductor package and dual-mold method of making same

Semiconductor device and method of forming interposer frame electri...

Double-sided semiconductor package and dual-mold method of making same

Chip package and method for forming the same

Circuit substrate interconnect

Stack packages and methods of manufacturing the same

Stack packages and methods of manufacturing the same

Patents Applicationslast 30 patents

CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE...

Double-Sided Semiconductor Package and Dual-Mold Method of Making Same

STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME