Timing aspects

Industry

CPC
G01R31/318594

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318594Timing aspects

Industries

Patents Grantslast 30 patents

Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Multi-modal memory apparatuses and systems
- Patent number 12,072,381
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Kenneth M. Curewitz
- G01 - MEASURING TESTING
Information Patent Grant
Integrated test circuit, test assembly and method for testing an in...
- Patent number 12,055,587
- Issue date Aug 6, 2024
- Infineon Technologies AG
- Tobias Kilian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stress-testing electrical components using telemetry modeling
- Patent number 12,038,479
- Issue date Jul 16, 2024
- Cisco Technology, Inc.
- James Edwin Turman
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,025,649
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit and test method
- Patent number 11,988,711
- Issue date May 21, 2024
- Realtek Semiconductor Corporation
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Grant
Server JTAG component adaptive interconnection system and method
- Patent number 11,953,550
- Issue date Apr 9, 2024
- INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD
- Yanpo Huang
- G01 - MEASURING TESTING
Information Patent Grant
Built in self test (BIST) for clock generation circuitry
- Patent number 11,821,946
- Issue date Nov 21, 2023
- NXP USA, INC.
- Jorge Arturo Corso Sarmiento
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test device and scan test method
- Patent number 11,789,073
- Issue date Oct 17, 2023
- Realtek Semiconductor Corporation
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Grant
Pseudo-random binary sequences (PRBS) generator for performing on-c...
- Patent number 11,774,496
- Issue date Oct 3, 2023
- INDIAN INSTITUTE OF TECHNOLOGY
- Mahendra Sakare
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for timing-annotated scan-chain testing using...
- Patent number 11,768,239
- Issue date Sep 26, 2023
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
3D TAP and scan port architectures
- Patent number 11,762,014
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 11,747,398
- Issue date Sep 5, 2023
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,726,135
- Issue date Aug 15, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Direct scan access JTAG
- Patent number 11,693,055
- Issue date Jul 4, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Performing testing utilizing staggered clocks
- Patent number 11,668,750
- Issue date Jun 6, 2023
- NVIDIA Corporation
- Sailendra Chadalavada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for selecting a clock
- Patent number 11,644,504
- Issue date May 9, 2023
- STMicroelectronics S.r.l.
- Mirko Dondini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for monitoring data and timing signals in integra...
- Patent number 11,635,465
- Issue date Apr 25, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Rohit Goel
- G01 - MEASURING TESTING
Information Patent Grant
Multi-capture at-speed scan test based on a slow clock signal
- Patent number 11,614,487
- Issue date Mar 28, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 11,549,983
- Issue date Jan 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Testing memory elements using an internal testing interface
- Patent number 11,500,017
- Issue date Nov 15, 2022
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip for AT-SPEED test of logic circuit and operating met...
- Patent number 11,442,107
- Issue date Sep 13, 2022
- Samsung Electronics Co., Ltd.
- Beom Seok Shin
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,391,769
- Issue date Jul 19, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method for synchronizing a checking apparatus, and a checking appar...
- Patent number 11,255,909
- Issue date Feb 22, 2022
- dspace digital signal processing and control engineering GmbH
- Matthias Klemm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct scan access JTAG
- Patent number 11,255,908
- Issue date Feb 22, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Processor to JTAG test data register interface
- Patent number 11,243,252
- Issue date Feb 8, 2022
- Cisco Technology, Inc.
- Venkatasubramanian Seetharaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 11,231,461
- Issue date Jan 25, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Enabling high at-speed test coverage of functional memory interface...
- Patent number 11,087,857
- Issue date Aug 10, 2021
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Design-for-test for asynchronous circuit elements
- Patent number 11,073,552
- Issue date Jul 27, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuan-Yen Huang
- G01 - MEASURING TESTING
Information Patent Grant
Combinatorial serial and parallel test access port selection in a J...
- Patent number 11,041,905
- Issue date Jun 22, 2021
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS
- Publication number 20240369632
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Kenneth M. Curewitz
- G01 - MEASURING TESTING
Information Patent Application
GLITCH FILTER
- Publication number 20240369630
- Publication date Nov 7, 2024
- NORDIC SEMICONDUCTOR ASA
- Christian HERGOT
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
- Publication number 20240339992
- Publication date Oct 10, 2024
- Samsung Electronics Co., Ltd.
- Mitesh GOYAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock Insertion Delay Systems and Methods
- Publication number 20240183902
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- G01 - MEASURING TESTING
Information Patent Application
MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS
- Publication number 20240125851
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Kenneth M. Curewitz
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
- Publication number 20240120016
- Publication date Apr 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
STRESS-TESTING ELECTRICAL COMPONENTS USING TELEMETRY MODELING
- Publication number 20240085477
- Publication date Mar 14, 2024
- Cisco Technology, Inc.
- James Edwin Turman
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20230366920
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BUILDING DATA PLATFORM WITH DIGITAL TWIN DIAGNOSTICS
- Publication number 20230359176
- Publication date Nov 9, 2023
- Johnson Controls Tyco IP Holdings LLP
- Rajiv Ramanasankaran
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD
- Publication number 20230358806
- Publication date Nov 9, 2023
- STMicroelectronics S.r.l.
- Marco CASARSA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT MARGIN MEASUREMENT FOR STRUCTURAL TESTING
- Publication number 20230258719
- Publication date Aug 17, 2023
- PROTEANTECS LTD.
- Evelyn LANDMAN
- G01 - MEASURING TESTING
Information Patent Application
SERVER JTAG COMPONENT ADAPTIVE INTERCONNECTION SYSTEM AND METHOD
- Publication number 20230184831
- Publication date Jun 15, 2023
- INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD
- Yanpo HUANG
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230160958
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20220341985
- Publication date Oct 27, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DEVICE AND METHOD FOR MONITORING DATA AND TIMING SIGNALS IN INTEGRA...
- Publication number 20220137133
- Publication date May 5, 2022
- STMicroelectronics International N.V.
- Rohit GOEL
- G01 - MEASURING TESTING
Information Patent Application
DIRECT SCAN ACCESS JTAG
- Publication number 20220137134
- Publication date May 5, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20220107362
- Publication date Apr 7, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
MULTI-CAPTURE AT-SPEED SCAN TEST BASED ON A SLOW CLOCK SIGNAL
- Publication number 20220018902
- Publication date Jan 20, 2022
- Siemens Industry Software Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
- Publication number 20210327525
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...
- Publication number 20210223315
- Publication date Jul 22, 2021
- Samsung Electronics Co., Ltd.
- Beom Seok SHIN
- G01 - MEASURING TESTING
Information Patent Application
DIE STACK TEST ARCHITECTURE AND METHOD
- Publication number 20210148963
- Publication date May 20, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20210088587
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SELECTING A CLOCK
- Publication number 20200278393
- Publication date Sep 3, 2020
- STMicroelectronics S.r.l
- Mirko Dondini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME INTERLEAVED SCAN SYSTEM
- Publication number 20200233031
- Publication date Jul 23, 2020
- QUALCOMM Incorporated
- Jais ABRAHAM
- G01 - MEASURING TESTING
Information Patent Application
DIE STACK TEST ARCHITECTURE AND METHOD
- Publication number 20200116779
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20200116787
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DESIGN METHOD FOR SCAN TEST CIRCUIT, DESIGN PROGRAM FOR SCAN TEST C...
- Publication number 20200096570
- Publication date Mar 26, 2020
- Kabushiki Kaisha Toshiba
- Chikako Tokunaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...
- Publication number 20200064405
- Publication date Feb 27, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING

Timing aspects

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

3D tap and scan port architectures

Multi-modal memory apparatuses and systems

Integrated test circuit, test assembly and method for testing an in...

Stress-testing electrical components using telemetry modeling

Integrated circuit die test architecture

Test circuit and test method

Server JTAG component adaptive interconnection system and method

Built in self test (BIST) for clock generation circuitry

Scan test device and scan test method

Pseudo-random binary sequences (PRBS) generator for performing on-c...

Method and apparatus for timing-annotated scan-chain testing using...

3D TAP and scan port architectures

Scan chain circuit and corresponding method

Integrated circuit die test architecture

Direct scan access JTAG

Performing testing utilizing staggered clocks

System and method for selecting a clock

Device and method for monitoring data and timing signals in integra...

Multi-capture at-speed scan test based on a slow clock signal

3D tap and scan port architectures

Testing memory elements using an internal testing interface

System-on-chip for AT-SPEED test of logic circuit and operating met...

Integrated circuit die test architecture

Method for synchronizing a checking apparatus, and a checking appar...

Direct scan access JTAG

Processor to JTAG test data register interface

3D tap and scan port architectures

Enabling high at-speed test coverage of functional memory interface...

Design-for-test for asynchronous circuit elements

Combinatorial serial and parallel test access port selection in a J...

Patents Applicationslast 30 patents

MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS

GLITCH FILTER

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY

Clock Insertion Delay Systems and Methods

MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS

AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES

STRESS-TESTING ELECTRICAL COMPONENTS USING TELEMETRY MODELING

3D TAP & SCAN PORT ARCHITECTURES

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

BUILDING DATA PLATFORM WITH DIGITAL TWIN DIAGNOSTICS

SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD

INTEGRATED CIRCUIT MARGIN MEASUREMENT FOR STRUCTURAL TESTING

SERVER JTAG COMPONENT ADAPTIVE INTERCONNECTION SYSTEM AND METHOD

3D TAP & SCAN PORT ARCHITECTURES

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

DEVICE AND METHOD FOR MONITORING DATA AND TIMING SIGNALS IN INTEGRA...

DIRECT SCAN ACCESS JTAG

3D TAP & SCAN PORT ARCHITECTURES

MULTI-CAPTURE AT-SPEED SCAN TEST BASED ON A SLOW CLOCK SIGNAL

AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES

SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING MET...

DIE STACK TEST ARCHITECTURE AND METHOD

3D TAP & SCAN PORT ARCHITECTURES

SYSTEM AND METHOD FOR SELECTING A CLOCK

TIME INTERLEAVED SCAN SYSTEM

DIE STACK TEST ARCHITECTURE AND METHOD

3D TAP & SCAN PORT ARCHITECTURES

DESIGN METHOD FOR SCAN TEST CIRCUIT, DESIGN PROGRAM FOR SCAN TEST C...

COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...