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G01R31/318538

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318538Topological or mechanical aspects

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Scan testable through silicon VIAs
- Patent number 12,154,835
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit including constant-0 flip flops reconfigured to...
- Patent number 12,130,330
- Issue date Oct 29, 2024
- QUALCOMM Incorporated
- Paul Policke
- G01 - MEASURING TESTING
Information Patent Grant
Scan correlation-aware scan cluster reordering method and apparatus...
- Patent number 12,000,891
- Issue date Jun 4, 2024
- UIF (University Industry Foundation), Yonsei University
- Sungho Kang
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,899,064
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor apparatus
- Patent number 11,683,883
- Issue date Jun 20, 2023
- Seiko Epson Corporation
- Yukio Okamura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing interposer method and apparatus
- Patent number 11,644,482
- Issue date May 9, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Grant
Scan apparatus capable of fault diagnosis and scan chain fault diag...
- Patent number 11,567,132
- Issue date Jan 31, 2023
- UIF (University Industry Foundation), Yonsei University
- Sungho Kang
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,549,984
- Issue date Jan 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Electronic circuit and corresponding method of testing electronic c...
- Patent number 11,486,928
- Issue date Nov 1, 2022
- STMicroelectronics S.r.l.
- Ignazio Pisello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling isolated development mode in utility end points
- Patent number 11,448,698
- Issue date Sep 20, 2022
- Landis+Gyr Innovations, Inc.
- Pushpesh Kumar Deshmukh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Diagnostic enhancement for multiple instances of identical structures
- Patent number 11,378,623
- Issue date Jul 5, 2022
- International Business Machines Corporation
- Steven Michael Douskey
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan testable through silicon VIAs
- Patent number 11,302,591
- Issue date Apr 12, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Safety mechanism for digital reset state
- Patent number 11,128,282
- Issue date Sep 21, 2021
- ALLEGRO MICROSYSTEMS, LLC
- Sergio Nicolás Deligiannis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Empirical LBIST latch switching and state probability determination
- Patent number 11,105,853
- Issue date Aug 31, 2021
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Grant
Combinatorial serial and parallel test access port selection in a J...
- Patent number 11,041,905
- Issue date Jun 22, 2021
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interposer, Test Access Port, First and Second Through Silicon Vias
- Patent number 10,928,419
- Issue date Feb 23, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- B44 - DECORATIVE ARTS
Information Patent Grant
Sequential test access port selection in a JTAG interface
- Patent number 10,890,619
- Issue date Jan 12, 2021
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Scan testable through silicon VIAs
- Patent number 10,796,974
- Issue date Oct 6, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Common test board, IP evaluation board, and semiconductor device te...
- Patent number 10,718,789
- Issue date Jul 21, 2020
- Kabushiki Kaisha Toshiba
- Masato Onda
- G01 - MEASURING TESTING
Information Patent Grant
TCKC/TMSC counter, gating circuitry for selection, deselection, tec...
- Patent number 10,649,029
- Issue date May 12, 2020
- Texas Instruments Incorporated
- Gary L. Swoboda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interposer with multiplexers, stimulus and control generators, and...
- Patent number 10,591,510
- Issue date Mar 17, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Grant
Series equivalent scans across multiple scan topologies
- Patent number RE47864
- Issue date Feb 18, 2020
- Texas Instruments Incorporated
- Gary L. Swoboda
Information Patent Grant
Three state buffer, another buffer coupled to ends of tsv
- Patent number 10,553,509
- Issue date Feb 4, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 10,539,617
- Issue date Jan 21, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Test application time reduction using capture-per-cycle test points
- Patent number 10,509,072
- Issue date Dec 17, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Method for identifying a fault at a device output and system therefor
- Patent number 10,436,839
- Issue date Oct 8, 2019
- NXP B.V.
- Robert Meyer
- G01 - MEASURING TESTING
Information Patent Grant
IC interposer with tap, multiplexers, stimulus generator and respon...
- Patent number 10,215,774
- Issue date Feb 26, 2019
- Texas Instruments Incorporated
- Lee D. Whetsel
- B44 - DECORATIVE ARTS
Information Patent Grant
Common test board, IP evaluation board, and semiconductor device te...
- Patent number 10,101,359
- Issue date Oct 16, 2018
- Kabushiki Kaisha Toshiba
- Masato Onda
- G01 - MEASURING TESTING
Information Patent Grant
Scan cell coupled to via ends, buffer coupled to via
- Patent number 10,068,816
- Issue date Sep 4, 2018
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TCK, TMS(C) clock, gating circuitry providing selection and deselec...
- Patent number 10,054,638
- Issue date Aug 21, 2018
- Texas Instruments Incorporated
- Gary L. Swoboda
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...
- Publication number 20250027993
- Publication date Jan 23, 2025
- QUALCOMM Incorporated
- Paul POLICKE
- G01 - MEASURING TESTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20240133951
- Publication date Apr 25, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
TESTING INTERPOSER METHOD AND APPARATUS
- Publication number 20230273238
- Publication date Aug 31, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
SCAN CORRELATION-AWARE SCAN CLUSTER REORDERING METHOD AND APPARATUS...
- Publication number 20230125568
- Publication date Apr 27, 2023
- UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
- Sung Ho KANG
- G01 - MEASURING TESTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20230113905
- Publication date Apr 13, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR DETECTING ACCESS TO A PRE-DEFINED AREA ON A PRINTED CIRC...
- Publication number 20220330422
- Publication date Oct 13, 2022
- THALES DIS CPL USA, Inc.
- Stephane LEMIRE
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ENABLING ISOLATED DEVELOPMENT MODE IN UTILITY END POINTS
- Publication number 20220317187
- Publication date Oct 6, 2022
- Landis+Gyr Innovations, Inc.
- Pushpesh Kumar Deshmukh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20220230928
- Publication date Jul 21, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIAGNOSTIC ENHANCEMENT FOR MULTIPLE INSTANCES OF IDENTICAL STRUCTURES
- Publication number 20220178996
- Publication date Jun 9, 2022
- International Business Machines Corporation
- Steven Michael DOUSKEY
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR APPARATUS
- Publication number 20210274641
- Publication date Sep 2, 2021
- SEIKO EPSON CORPORATION
- Yukio OKAMURA
- G01 - MEASURING TESTING
Information Patent Application
EMPIRICAL LBIST LATCH SWITCHING AND STATE PROBABILITY DETERMINATION
- Publication number 20210270898
- Publication date Sep 2, 2021
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Application
SAFETY MECHANISM FOR DIGITAL RESET STATE
- Publication number 20210239758
- Publication date Aug 5, 2021
- ALLEGRO MICROSYSTEMS, LLC
- Sergio Nicolás Deligiannis
- G01 - MEASURING TESTING
Information Patent Application
TESTING INTERPOSER METHOD AND APPARATUS
- Publication number 20210132111
- Publication date May 6, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- B44 - DECORATIVE ARTS
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20200411394
- Publication date Dec 31, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TESTING INTERPOSER METHOD AND APPARATUS
- Publication number 20200150149
- Publication date May 14, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- B44 - DECORATIVE ARTS
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20200124668
- Publication date Apr 23, 2020
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20200118897
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...
- Publication number 20200064405
- Publication date Feb 27, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING INTERPOSER METHOD AND APPARATUS
- Publication number 20190146004
- Publication date May 16, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON TEST BOARD, IP EVALUATION BOARD, AND SEMICONDUCTOR DEVICE TE...
- Publication number 20190004088
- Publication date Jan 3, 2019
- Kabushiki Kaisha Toshiba
- Masato Onda
- G01 - MEASURING TESTING
Information Patent Application
ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA
- Publication number 20180321310
- Publication date Nov 8, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Gary L. SWOBODA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20180308774
- Publication date Oct 25, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20180061723
- Publication date Mar 1, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS
- Publication number 20180003769
- Publication date Jan 4, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Gary L. SWOBODA
- G01 - MEASURING TESTING
Information Patent Application
PHYSICALLY AWARE SCAN DIAGNOSTIC LOGIC AND POWER SAVING CIRCUIT INS...
- Publication number 20170254851
- Publication date Sep 7, 2017
- International Business Machines Corporation
- WILLIAM V. HUOTT
- G01 - MEASURING TESTING
Information Patent Application
TESTING INTERPOSER METHOD AND APPARATUS
- Publication number 20170242069
- Publication date Aug 24, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20170103931
- Publication date Apr 13, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CH...
- Publication number 20160299191
- Publication date Oct 13, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Gary L. Swoboda
- G01 - MEASURING TESTING
Information Patent Application
BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CH...
- Publication number 20160003905
- Publication date Jan 7, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Gary L. Swoboda
- G01 - MEASURING TESTING
Information Patent Application
SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS
- Publication number 20140337678
- Publication date Nov 13, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Gary L. SWOBODA
- G01 - MEASURING TESTING

Topological or mechanical aspects

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Scan testable through silicon VIAs

Integrated circuit including constant-0 flip flops reconfigured to...

Scan correlation-aware scan cluster reordering method and apparatus...

Scan architecture for interconnect testing in 3D integrated circuits

Semiconductor apparatus

Testing interposer method and apparatus

Scan apparatus capable of fault diagnosis and scan chain fault diag...

Scan architecture for interconnect testing in 3D integrated circuits

Electronic circuit and corresponding method of testing electronic c...

Enabling isolated development mode in utility end points

Diagnostic enhancement for multiple instances of identical structures

Scan testable through silicon VIAs

Safety mechanism for digital reset state

Empirical LBIST latch switching and state probability determination

Combinatorial serial and parallel test access port selection in a J...

Interposer, Test Access Port, First and Second Through Silicon Vias

Sequential test access port selection in a JTAG interface

Scan testable through silicon VIAs

Common test board, IP evaluation board, and semiconductor device te...

TCKC/TMSC counter, gating circuitry for selection, deselection, tec...

Interposer with multiplexers, stimulus and control generators, and...

Series equivalent scans across multiple scan topologies

Three state buffer, another buffer coupled to ends of tsv

Scan architecture for interconnect testing in 3D integrated circuits

Test application time reduction using capture-per-cycle test points

Method for identifying a fault at a device output and system therefor

IC interposer with tap, multiplexers, stimulus generator and respon...

Common test board, IP evaluation board, and semiconductor device te...

Scan cell coupled to via ends, buffer coupled to via

TCK, TMS(C) clock, gating circuitry providing selection and deselec...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

TESTING INTERPOSER METHOD AND APPARATUS

SCAN CORRELATION-AWARE SCAN CLUSTER REORDERING METHOD AND APPARATUS...

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

SYSTEM FOR DETECTING ACCESS TO A PRE-DEFINED AREA ON A PRINTED CIRC...

ENABLING ISOLATED DEVELOPMENT MODE IN UTILITY END POINTS

SCAN TESTABLE THROUGH SILICON VIAs

DIAGNOSTIC ENHANCEMENT FOR MULTIPLE INSTANCES OF IDENTICAL STRUCTURES

SEMICONDUCTOR APPARATUS

EMPIRICAL LBIST LATCH SWITCHING AND STATE PROBABILITY DETERMINATION

SAFETY MECHANISM FOR DIGITAL RESET STATE

TESTING INTERPOSER METHOD AND APPARATUS

SCAN TESTABLE THROUGH SILICON VIAs

TESTING INTERPOSER METHOD AND APPARATUS

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

SCAN TESTABLE THROUGH SILICON VIAs

COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...

TESTING INTERPOSER METHOD AND APPARATUS

COMMON TEST BOARD, IP EVALUATION BOARD, AND SEMICONDUCTOR DEVICE TE...

ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA

SCAN TESTABLE THROUGH SILICON VIAs

SCAN TESTABLE THROUGH SILICON VIAs

SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS

PHYSICALLY AWARE SCAN DIAGNOSTIC LOGIC AND POWER SAVING CIRCUIT INS...

TESTING INTERPOSER METHOD AND APPARATUS

SCAN TESTABLE THROUGH SILICON VIAs

BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CH...

BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CH...

SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS