using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Industry

CPC
H03K19/1738

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Parent Industries

HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE H03K19/00Logic circuits

Current Industry

H03K19/1738using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Industries

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Patents Grantslast 30 patents

Information Patent Grant
On-chip memory block circuit
- Patent number 11,182,110
- Issue date Nov 23, 2021
- Xilinx, Inc.
- Ahmad R. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loop optimization for implementing circuit designs in hardware
- Patent number 10,331,836
- Issue date Jun 25, 2019
- Xilinx, Inc.
- Anup Hosangadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for variable latency redundancy
- Patent number 10,020,812
- Issue date Jul 10, 2018
- Intel Corporation
- Martin Langhammer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Combinatorial logic circuit
- Patent number 7,872,503
- Issue date Jan 18, 2011
- ST-Ericsson SA
- Mihai Adrian Tiberiu Sanduleanu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable logic cell made up of double-gate MOSFET transistors
- Patent number 7,859,308
- Issue date Dec 28, 2010
- Ecole Centrale de Lyon
- Ian D. O'Connor
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplexer circuit
- Patent number 7,816,972
- Issue date Oct 19, 2010
- Korea Advanced Institute of Science and Technology
- Kyoung Hoon Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic and differential CMOS logic with signal-independent power c...
- Patent number 7,692,449
- Issue date Apr 6, 2010
- The Regents of the University of California
- Ingrid M. Verbauwhede
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic and differential CMOS logic with signal-independent power c...
- Patent number 7,417,468
- Issue date Aug 26, 2008
- The Regents of the University of California
- Ingrid M. Verbauwhede
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low swing current mode logic family
- Patent number 7,362,140
- Issue date Apr 22, 2008
- Universite Catholique De Louvain
- Ilham Hassoune
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit arrangement and method for producing a dual-rail signal
- Patent number 7,323,910
- Issue date Jan 29, 2008
- Infineon Technologies AG
- Thomas Kunemund
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power management circuit
- Patent number 7,132,848
- Issue date Nov 7, 2006
- Taiwan Semiconductor Manufacturing Co, Ltd.
- Fang-Shi Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for a glitch-free differential current steering s...
- Patent number 7,071,858
- Issue date Jul 4, 2006
- Broadcom Corporation
- Hui Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital clock manager having cascade voltage switch logic clock paths
- Patent number 7,038,519
- Issue date May 2, 2006
- Xilinx, Inc.
- Raymond C. Pang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pipelined low-voltage current-mode logic with a switching stack hei...
- Patent number 6,903,579
- Issue date Jun 7, 2005
- International Business Machines Corporation
- Sergey V. Rylov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronous clocked full-rail differential logic with single-rail l...
- Patent number 6,876,230
- Issue date Apr 5, 2005
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for clock control of clocked half-rail differential logic wi...
- Patent number 6,859,072
- Issue date Feb 22, 2005
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Control of guard-flops
- Patent number 6,831,482
- Issue date Dec 14, 2004
- Azuro (UK) Limited
- Paul Alexander Cunningham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for clock control of half-rail differential logic
- Patent number 6,828,826
- Issue date Dec 7, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for clock control of clocked half-rail differential logic wi...
- Patent number 6,784,697
- Issue date Aug 31, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for clock control of clocked full-rail differential logic ci...
- Patent number 6,768,345
- Issue date Jul 27, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocked half-rail differential logic with sense amplifier and shut-off
- Patent number 6,768,343
- Issue date Jul 27, 2004
- Sun Microsystems
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocked half-rail differential logic with single-rail logic and sen...
- Patent number 6,768,344
- Issue date Jul 27, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocked full-rail differential logic with shut-off
- Patent number 6,765,415
- Issue date Jul 20, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocked full-rail differential logic with sense amplifier and singl...
- Patent number 6,750,679
- Issue date Jun 15, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocked half-rail differential logic with sense amplifier
- Patent number 6,744,283
- Issue date Jun 1, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for clock control of clocked half-rail differential logic wi...
- Patent number 6,741,101
- Issue date May 25, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for increasing the power efficiency and noise immunity of cl...
- Patent number 6,737,889
- Issue date May 18, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocked half-rail differential logic with single-rail logic
- Patent number 6,717,438
- Issue date Apr 6, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocked full-rail differential logic with sense amplifier and shut-off
- Patent number 6,703,867
- Issue date Mar 9, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Symmetrical CML logic gate system
- Patent number 6,680,625
- Issue date Jan 20, 2004
- Lattice Semiconductor Corp.
- Kochung Lee
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
RECONFIGURABLE LOGIC CELL MADE UP OF DOUBLE-GATE MOSFET TRANSISTORS
- Publication number 20100194430
- Publication date Aug 5, 2010
- Ecole Centrale de Lyon
- Ian D. O'Connor
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLEXER CIRCUIT
- Publication number 20090080465
- Publication date Mar 26, 2009
- Korea Advanced Institute of Science and Technology
- Kyoung Hoon YANG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC AND DIFFERENTIAL CMOS LOGIC WITH SIGNAL-INDEPENDENT POWER C...
- Publication number 20090039919
- Publication date Feb 12, 2009
- The Regents of the University of California
- Ingrid M. Verbauwhede
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combinatorial Logic Circuit
- Publication number 20070285119
- Publication date Dec 13, 2007
- Koninklijke Philips Electronics N.V.
- Mihai A., T. Sanduleanu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Swing Current Mode Logic Family
- Publication number 20070222475
- Publication date Sep 27, 2007
- Ilham Hassoune
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dynamic and differential cmos logic with signal-independent power c...
- Publication number 20070057698
- Publication date Mar 15, 2007
- Ingrid M. Verbauwhede
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR A GLITCH-FREE DIFFERENTIAL CURRENT STEERING S...
- Publication number 20060092062
- Publication date May 4, 2006
- BROADCOM CORPORATION
- Hui Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power management circuit
- Publication number 20060017469
- Publication date Jan 26, 2006
- Fang-Shi Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit arrangement and method for producing a dual-rail signal
- Publication number 20050063478
- Publication date Mar 24, 2005
- Infineon Technologies AG
- Thomas Kunemund
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Pipelined low-voltage current-mode logic with a switching stack hei...
- Publication number 20040263210
- Publication date Dec 30, 2004
- International Business Machines Corporation
- Sergey V. Rylov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Synchronous clocked full-rail differential logic with single-rail l...
- Publication number 20040263207
- Publication date Dec 30, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methos for clock control of clocked half-rail differential logic wi...
- Publication number 20040183569
- Publication date Sep 23, 2004
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for clock control of clocked half-rail differential logic wi...
- Publication number 20040070423
- Publication date Apr 15, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for clock control of clocked full-rail differential logic ci...
- Publication number 20040066214
- Publication date Apr 8, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clocked half-rail differential logic with single-rail logic and sen...
- Publication number 20040041589
- Publication date Mar 4, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCKED HALF-RAIL DIFFERENTIAL LOGIC WITH SINGLE-RAIL LOGIC
- Publication number 20040041588
- Publication date Mar 4, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCKED FULL-RAIL DIFFERENTIAL LOGIC WITH SENSE AMPLIFIER AND SHUT-OFF
- Publication number 20040036506
- Publication date Feb 26, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clocked half-rail differential logic with sense amplifier and shut-off
- Publication number 20040036503
- Publication date Feb 26, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clocked full-rail differential logic with shut-off
- Publication number 20040036504
- Publication date Feb 26, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for increasing the power efficiency and noise immunity of cl...
- Publication number 20040036505
- Publication date Feb 26, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clocked half-rail differential logic with sense amplifier
- Publication number 20040027164
- Publication date Feb 12, 2004
- Sun Microsystems Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Control of guard-flops
- Publication number 20040004504
- Publication date Jan 8, 2004
- Paul Alexander Cunningham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ZIPPER DOMINO CARRY GENERATE CELL FOR FAST ADDERS
- Publication number 20030112036
- Publication date Jun 19, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for clock control of half-rail differential logic
- Publication number 20030076133
- Publication date Apr 24, 2003
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SWITCHED IOH AND IOL CURRENT SOURCES FOR CMOS LOW-VOLTAGE PECL DRIV...
- Publication number 20030042980
- Publication date Mar 6, 2003
- David Kwong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clocked logic gate circuit
- Publication number 20010000296
- Publication date Apr 19, 2001
- Kazuo Kanetani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clocked logic gate circuit
- Publication number 20010000017
- Publication date Mar 15, 2001
- Kazuo Kanetani
- H03 - BASIC ELECTRONIC CIRCUITRY

using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

On-chip memory block circuit

Loop optimization for implementing circuit designs in hardware

Techniques for variable latency redundancy

Combinatorial logic circuit

Reconfigurable logic cell made up of double-gate MOSFET transistors

Multiplexer circuit

Dynamic and differential CMOS logic with signal-independent power c...

Dynamic and differential CMOS logic with signal-independent power c...

Low swing current mode logic family

Circuit arrangement and method for producing a dual-rail signal

Power management circuit

Method and system for a glitch-free differential current steering s...

Digital clock manager having cascade voltage switch logic clock paths

Pipelined low-voltage current-mode logic with a switching stack hei...

Synchronous clocked full-rail differential logic with single-rail l...

Method for clock control of clocked half-rail differential logic wi...

Control of guard-flops

Method for clock control of half-rail differential logic

Method for clock control of clocked half-rail differential logic wi...

Method for clock control of clocked full-rail differential logic ci...

Clocked half-rail differential logic with sense amplifier and shut-off

Clocked half-rail differential logic with single-rail logic and sen...

Clocked full-rail differential logic with shut-off

Clocked full-rail differential logic with sense amplifier and singl...

Clocked half-rail differential logic with sense amplifier

Method for clock control of clocked half-rail differential logic wi...

Method for increasing the power efficiency and noise immunity of cl...

Clocked half-rail differential logic with single-rail logic

Clocked full-rail differential logic with sense amplifier and shut-off

Symmetrical CML logic gate system

Patents Applicationslast 30 patents

RECONFIGURABLE LOGIC CELL MADE UP OF DOUBLE-GATE MOSFET TRANSISTORS

MULTIPLEXER CIRCUIT

DYNAMIC AND DIFFERENTIAL CMOS LOGIC WITH SIGNAL-INDEPENDENT POWER C...

Combinatorial Logic Circuit

Low Swing Current Mode Logic Family

Dynamic and differential cmos logic with signal-independent power c...

METHOD AND SYSTEM FOR A GLITCH-FREE DIFFERENTIAL CURRENT STEERING S...

Power management circuit

Circuit arrangement and method for producing a dual-rail signal

Pipelined low-voltage current-mode logic with a switching stack hei...

Synchronous clocked full-rail differential logic with single-rail l...

Methos for clock control of clocked half-rail differential logic wi...

Method for clock control of clocked half-rail differential logic wi...

Method for clock control of clocked full-rail differential logic ci...

Clocked half-rail differential logic with single-rail logic and sen...

CLOCKED HALF-RAIL DIFFERENTIAL LOGIC WITH SINGLE-RAIL LOGIC

CLOCKED FULL-RAIL DIFFERENTIAL LOGIC WITH SENSE AMPLIFIER AND SHUT-OFF

Clocked half-rail differential logic with sense amplifier and shut-off

Clocked full-rail differential logic with shut-off

Method for increasing the power efficiency and noise immunity of cl...

Clocked half-rail differential logic with sense amplifier

Control of guard-flops

ZIPPER DOMINO CARRY GENERATE CELL FOR FAST ADDERS

Method for clock control of half-rail differential logic

SWITCHED IOH AND IOL CURRENT SOURCES FOR CMOS LOW-VOLTAGE PECL DRIV...

Clocked logic gate circuit

Clocked logic gate circuit