using error correcting codes [ECC] or parity check

Industry

CPC
G11C29/42

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/42using error correcting codes [ECC] or parity check

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Indicating a status of a memory built-in self-test using a data mas...
- Patent number 12,340,860
- Issue date Jun 24, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses, systems, and methods for module level error correction
- Patent number 12,340,858
- Issue date Jun 24, 2025
- Micron Technology, Inc.
- Sujeet Ayyapureddi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid memory system with increased bandwidth
- Patent number 12,340,859
- Issue date Jun 24, 2025
- QUALCOMM Incorporated
- Jungwon Suh
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling memory including managing a correction value table
- Patent number 12,334,171
- Issue date Jun 17, 2025
- Kioxia Corporation
- Masanobu Shirakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating and testing semiconductor devices
- Patent number 12,334,170
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Taewook Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with error checking and correcting unit
- Patent number 12,327,600
- Issue date Jun 10, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Weibing Shang
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacity-expanding memory control component
- Patent number 12,323,164
- Issue date Jun 3, 2025
- Astera Labs, Inc.
- Enrique Musoll
- G11 - INFORMATION STORAGE
Information Patent Grant
Vehicle memory system based on 3D memory and method operating thereof
- Patent number 12,322,463
- Issue date Jun 3, 2025
- Hyundai Motor Company
- Hong Yeol Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device including sense amplifying circuit
- Patent number 12,315,579
- Issue date May 27, 2025
- SK Hynix Inc.
- Yeonsu Jang
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test circuitry
- Patent number 12,315,580
- Issue date May 27, 2025
- Micron Technology, Inc.
- William Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and operating method of the memory device
- Patent number 12,315,582
- Issue date May 27, 2025
- SK hynix Inc.
- Min Ho Her
- G11 - INFORMATION STORAGE
Information Patent Grant
In-situ detection of anomalies in integrated circuits using machine...
- Patent number 12,307,747
- Issue date May 20, 2025
- Intel Corporation
- Sriram R. Vangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory devices that support enhanced data recovery op...
- Patent number 12,308,082
- Issue date May 20, 2025
- Samsung Electronics Co., Ltd.
- Seungjun Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Media scan in memory systems
- Patent number 12,300,336
- Issue date May 13, 2025
- Yangtze Memory Technologies Co., Ltd.
- Hua Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing memory testing using error correction code values
- Patent number 12,300,339
- Issue date May 13, 2025
- Micron Technology, Inc.
- Kok Hua Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system including a sub-controller and operating method of th...
- Patent number 12,300,341
- Issue date May 13, 2025
- SK Hynix Inc.
- Jong Joo Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting memory power consumption
- Patent number 12,300,340
- Issue date May 13, 2025
- Microsoft Technology Licensing, LLC
- Ori Laslo
- G11 - INFORMATION STORAGE
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage devices and methods of operating storage devices
- Patent number 12,288,590
- Issue date Apr 29, 2025
- Samsung Electronics Co., Ltd.
- Eun Chu Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having an improved ECC architecture
- Patent number 12,288,591
- Issue date Apr 29, 2025
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit retiring to mitigate bit errors
- Patent number 12,283,333
- Issue date Apr 22, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND data placement schema
- Patent number 12,277,979
- Issue date Apr 15, 2025
- Micron Technology, Inc.
- Carminantonio Manganelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for improving ECC operation of memories
- Patent number 12,266,410
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die-based high and low priority error queues
- Patent number 12,260,927
- Issue date Mar 25, 2025
- Kioxia Corporation
- Gyan Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with serial and parallel testing structure for sensin...
- Patent number 12,254,938
- Issue date Mar 18, 2025
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 12,254,929
- Issue date Mar 18, 2025
- Kioxia Corporation
- Masanobu Shirakawa
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE
- Publication number 20250210123
- Publication date Jun 26, 2025
- Lodestar Licensing Group LLC
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Application
DETECTING ERRORS WITHIN DATA PATH CIRCUITRY OF A MEMORY DEVICE
- Publication number 20250201329
- Publication date Jun 19, 2025
- ADVANCED MICRO DEVICES, INC.
- Michael LITT
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY, MEMORY SYSTEM, PROGRAM METHOD OF MEMORY, AND ELECTRONIC APP...
- Publication number 20250191668
- Publication date Jun 12, 2025
- Yangtze Memory Technologies Co., Ltd.
- Hongtao Liu
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20250190301
- Publication date Jun 12, 2025
- RENESAS ELECTRONICS CORPORATION
- Daiki KITAGATA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20250182828
- Publication date Jun 5, 2025
- KIOXIA Corporation
- Masanobu SHIRAKAWA
- G11 - INFORMATION STORAGE
Information Patent Application
INTERFACE READ AFTER WRITE
- Publication number 20250165191
- Publication date May 22, 2025
- Micron Technology, Inc.
- Yue Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IN-LINE ECC PROTECTION
- Publication number 20250165393
- Publication date May 22, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Denis Roland BEAUDOIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR DETECTION FOR SRAM USED IN A SAFETY-CRITICAL DOMAIN
- Publication number 20250157561
- Publication date May 15, 2025
- ADVANCED MICRO DEVICES, INC.
- Uma Sankara Rao Balla
- G11 - INFORMATION STORAGE
Information Patent Application
STUCK BITS ENCODING AND DECODING ON A STORAGE DEVICE
- Publication number 20250157562
- Publication date May 15, 2025
- Western Digital Technologies, Inc.
- ROBERT MATEESCU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMOR...
- Publication number 20250149105
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Kijun LEE
- G11 - INFORMATION STORAGE
Information Patent Application
AUTOMATED VOLTAGE DEMARCATION (VDM) ADJUSTMENT FOR MEMORY DEVICE
- Publication number 20250149079
- Publication date May 8, 2025
- Micron Technology, Inc.
- Yi-Min Lin
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH STAGGERED ACCESS
- Publication number 20250147875
- Publication date May 8, 2025
- Rambus Inc.
- Torsten Partsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and device for correcting errors in resistive memories
- Publication number 20250131971
- Publication date Apr 24, 2025
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Valentin GHERMAN
- G11 - INFORMATION STORAGE
Information Patent Application
STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS
- Publication number 20250130908
- Publication date Apr 24, 2025
- Micron Technology, Inc.
- Christopher John Kawamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...
- Publication number 20250131970
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Massimo Sutera
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES
- Publication number 20250131972
- Publication date Apr 24, 2025
- Lodestar Licensing Group LLC
- Dong Pan
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND...
- Publication number 20250124997
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Katherine H. CHIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INCLUDING ERROR CORRECTION CIRCUIT
- Publication number 20250118387
- Publication date Apr 10, 2025
- SK HYNIX INC.
- Mun Seon JANG
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METADATA STORAGE AT A MEMORY DEVICE
- Publication number 20250118388
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND MEMORY WITH CONFIGURABLE METADATA PORTION
- Publication number 20250111885
- Publication date Apr 3, 2025
- QUALCOMM Incorporated
- Jungwon Suh
- G11 - INFORMATION STORAGE
Information Patent Application
HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY
- Publication number 20250111884
- Publication date Apr 3, 2025
- Micron Technology, Inc.
- Tomoko Ogura Iwasaki
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND AN OPERATING METHOD THEREOF
- Publication number 20250104788
- Publication date Mar 27, 2025
- Yangtze Memory Technologies Co., Ltd.
- Shuai ZHANG
- G11 - INFORMATION STORAGE
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DROP COMPENSATED MEMORY
- Publication number 20250087289
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Ferdinando Bedeschi
- G11 - INFORMATION STORAGE
Information Patent Application
CRYPTOGRAPHIC KEY MANAGEMENT
- Publication number 20250086329
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING

using error correcting codes [ECC] or parity check

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Indicating a status of a memory built-in self-test using a data mas...

Apparatuses, systems, and methods for module level error correction

Hybrid memory system with increased bandwidth

Controlling memory including managing a correction value table

Operating and testing semiconductor devices

Memory with error checking and correcting unit

Methods and apparatus to facilitate atomic operations in victim cache

Capacity-expanding memory control component

Vehicle memory system based on 3D memory and method operating thereof

Victim cache with write miss merging

Memory device including sense amplifying circuit

Built-in self-test circuitry

Memory device and operating method of the memory device

In-situ detection of anomalies in integrated circuits using machine...

Semiconductor memory devices that support enhanced data recovery op...

Media scan in memory systems

Performing memory testing using error correction code values

Memory system including a sub-controller and operating method of th...

Adjusting memory power consumption

Write merging on stores with different privilege levels

Storage devices and methods of operating storage devices

Memory device having an improved ECC architecture

Bit retiring to mitigate bit errors

NAND data placement schema

Hybrid victim cache and write miss buffer with fence operation

Methods and systems for improving ECC operation of memories

Methods and apparatus for multi-banked victim cache with dual datapath

Die-based high and low priority error queues

Memory device with serial and parallel testing structure for sensin...

Semiconductor memory device

Patents Applicationslast 30 patents

MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE

DETECTING ERRORS WITHIN DATA PATH CIRCUITRY OF A MEMORY DEVICE

MEMORY, MEMORY SYSTEM, PROGRAM METHOD OF MEMORY, AND ELECTRONIC APP...

SEMICONDUCTOR DEVICE

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

SEMICONDUCTOR MEMORY DEVICE

INTERFACE READ AFTER WRITE

METHOD AND SYSTEM FOR IN-LINE ECC PROTECTION

ERROR DETECTION FOR SRAM USED IN A SAFETY-CRITICAL DOMAIN

STUCK BITS ENCODING AND DECODING ON A STORAGE DEVICE

MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMOR...

AUTOMATED VOLTAGE DEMARCATION (VDM) ADJUSTMENT FOR MEMORY DEVICE

MEMORY DEVICE WITH STAGGERED ACCESS

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

Method and device for correcting errors in resistive memories

STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS

EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...

APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES

METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND...

MEMORY INCLUDING ERROR CORRECTION CIRCUIT

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

METADATA STORAGE AT A MEMORY DEVICE

SYSTEM AND MEMORY WITH CONFIGURABLE METADATA PORTION

HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY

MEMORY SYSTEM AND AN OPERATING METHOD THEREOF

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

SIGNAL DROP COMPENSATED MEMORY

CRYPTOGRAPHIC KEY MANAGEMENT