using error correcting codes [ECC] or parity check

Industry

CPC
G11C29/42

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/42using error correcting codes [ECC] or parity check

Industries

Patents Grantslast 30 patents

Information Patent Grant
Mitigation of transistor reliability degradation within memory circ...
- Patent number 11,972,823
- Issue date Apr 30, 2024
- Apple Inc.
- Assaf Shappir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device, controller, memory system and method o...
- Patent number 11,972,824
- Issue date Apr 30, 2024
- SK Hynix Inc.
- Jin Sub Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable ECC for MRAM mixed-read scheme
- Patent number 11,972,822
- Issue date Apr 30, 2024
- SANDISK TECHNOLOGIES LLC
- Martin Hassner
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor apparatus related to a test function
- Patent number 11,967,389
- Issue date Apr 23, 2024
- SK hynix Inc.
- Seon Woo Hwang
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage device and operating method of storage device
- Patent number 11,961,559
- Issue date Apr 16, 2024
- Samsung Electronics Co., Ltd.
- Yunjung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NAND data placement schema
- Patent number 11,955,189
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Carminantonio Manganelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Tracking and refreshing state metrics in memory sub-systems
- Patent number 11,955,194
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Michael Sheperek
- G11 - INFORMATION STORAGE
Information Patent Grant
Early error detection and automatic correction techniques for stora...
- Patent number 11,948,653
- Issue date Apr 2, 2024
- Avago Technologies International Sales Pte. Limited
- Sachin Prabhakarrao Kadu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to reduce read-modify-write cycles for non-al...
- Patent number 11,940,929
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device protection using interleaved multibit symbols
- Patent number 11,942,175
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Paolo Amato
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 11,940,930
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory apparatus and semiconductor system including the same
- Patent number 11,942,173
- Issue date Mar 26, 2024
- SK hynix Inc.
- Heeeun Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Topology-based retirement in a memory system
- Patent number 11,942,174
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Chun S. Yeung
- G11 - INFORMATION STORAGE
Information Patent Grant
Linked XOR flash data protection scheme
- Patent number 11,935,609
- Issue date Mar 19, 2024
- Western Digital Technologies, Inc.
- Oleg Kragel
- G11 - INFORMATION STORAGE
Information Patent Grant
Path based controls for ATE mode testing of multicell memory circuit
- Patent number 11,933,844
- Issue date Mar 19, 2024
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal generation circuit and method, and semiconductor memory
- Patent number 11,935,608
- Issue date Mar 19, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic error monitor and repair
- Patent number 11,935,610
- Issue date Mar 19, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiroki Noguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system
- Patent number 11,923,029
- Issue date Mar 5, 2024
- Kioxia Corporation
- Marie Takada
- G11 - INFORMATION STORAGE
Information Patent Grant
Generation of programming parameters for non-volatile memory device...
- Patent number 11,923,025
- Issue date Mar 5, 2024
- Kioxia Corporation
- Avi Steiner
- G11 - INFORMATION STORAGE
Information Patent Grant
Data storage system with intelligent error management
- Patent number 11,923,026
- Issue date Mar 5, 2024
- Seagate Technology LLC
- Jeremy B. Goolsby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sense amplifier trimming
- Patent number 11,923,036
- Issue date Mar 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Chun Shih
- G11 - INFORMATION STORAGE
Information Patent Grant
Data scrambling method that controls code density
- Patent number 11,923,000
- Issue date Mar 5, 2024
- University of Seoul Industry Cooperation Foundation
- Dong Hee Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Read command fault detection in a memory system
- Patent number 11,923,027
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Melissa I. Uribe
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference voltage adjustment based on post-decoding and pre-decodin...
- Patent number 11,923,028
- Issue date Mar 5, 2024
- Chenrong Xiong
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized storage charge loss management
- Patent number 11,923,030
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Gary F. Besinga
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid memory system with configurable error thresholds and failure...
- Patent number 11,914,481
- Issue date Feb 27, 2024
- Netlist, Inc.
- Scott H. Milton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface read after write
- Patent number 11,907,572
- Issue date Feb 20, 2024
- Micron Technology, Inc.
- Yue Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Counter-based read in memory device
- Patent number 11,901,029
- Issue date Feb 13, 2024
- Micron Technology, Inc.
- Umberto Di Vincenzo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for column repair
- Patent number 11,901,033
- Issue date Feb 13, 2024
- Samsung Electronics Co., Ltd.
- Jooyong Park
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY WITH ERROR CHECKING AND CORRECTING UNIT
- Publication number 20240145022
- Publication date May 2, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Weibing SHANG
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Testing Techniques
- Publication number 20240136006
- Publication date Apr 25, 2024
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MEMORY STORAGE AND ACCESS
- Publication number 20240126640
- Publication date Apr 18, 2024
- INFINEON TECHNOLOGIES AG
- Thomas Kern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING
- Publication number 20240111625
- Publication date Apr 4, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAND DATA PLACEMENT SCHEMA
- Publication number 20240112745
- Publication date Apr 4, 2024
- Micron Technology, Inc.
- Carminantonio MANGANELLI
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20240104026
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK
- Publication number 20240095119
- Publication date Mar 21, 2024
- Micron Technology, Inc.
- Peter Mayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEIGHTED WEAR LEVELING FOR IMPROVING UNIFORMITY
- Publication number 20240096433
- Publication date Mar 21, 2024
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING OPERATIONS FOR MEMORY SYSTEMS
- Publication number 20240094921
- Publication date Mar 21, 2024
- Micron Technology, Inc.
- Yuan He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST CIRCUITRY
- Publication number 20240087663
- Publication date Mar 14, 2024
- Micron Technology, Inc.
- William Yu
- G11 - INFORMATION STORAGE
Information Patent Application
Mitigation of transistor reliability degradation within memory circ...
- Publication number 20240087666
- Publication date Mar 14, 2024
- Apple Inc.
- Assaf Shappir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error Correction for Stacked Memory
- Publication number 20240087667
- Publication date Mar 14, 2024
- ADVANCED MICRO DEVICES, INC.
- Divya Madapusi Srinivas Prasad
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CORRECTION CODE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING...
- Publication number 20240079076
- Publication date Mar 7, 2024
- SK HYNIX INC.
- Hong Ki MOON
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
- Publication number 20240078190
- Publication date Mar 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION
- Publication number 20240071549
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Sujeet Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION
- Publication number 20240071550
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Sujeet Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES THAT SUPPORT ENHANCED DATA RECOVERY OP...
- Publication number 20240071545
- Publication date Feb 29, 2024
- Samsung Electronics Co., Ltd.
- Seungjun Oh
- G11 - INFORMATION STORAGE
Information Patent Application
READ-WRITE METHOD AND APPARATUS FOR LEPS SOFT DECODING ESTIMATION,...
- Publication number 20240038318
- Publication date Feb 1, 2024
- Institute of Microelectronics, Chinese Academy of Sciences
- Qi Wang
- G11 - INFORMATION STORAGE
Information Patent Application
INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST USING A DATA MAS...
- Publication number 20240038320
- Publication date Feb 1, 2024
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20240028523
- Publication date Jan 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR DETERMINING MEMORY CELL DATA STATES
- Publication number 20240029809
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
- Publication number 20240029808
- Publication date Jan 25, 2024
- Samsung Electronics Co., Ltd.
- Yujung Song
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY, MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM
- Publication number 20240029810
- Publication date Jan 25, 2024
- SK HYNIX INC.
- Munseon JANG
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODUL...
- Publication number 20240021261
- Publication date Jan 18, 2024
- Samsung Electronics Co., Ltd.
- EUNHYE OH
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20240020242
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC CIRCUIT AND METHOD FOR SELF-DIAGNOSIS OF A DATA MEMORY
- Publication number 20240013847
- Publication date Jan 11, 2024
- DREAM CHIP TECHNOLOGIES GMBH
- Karl Heinz EICKEL
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR CIRCUIT
- Publication number 20240014810
- Publication date Jan 11, 2024
- Sony Semiconductor Solutions Corporation
- LUI SAKAI
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR MONITORING AND MANAGING MEMORY DEVICES
- Publication number 20240006011
- Publication date Jan 4, 2024
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. ALAM
- G11 - INFORMATION STORAGE
Information Patent Application
Storage System and Method for Proactive Die Retirement by Fatal Wor...
- Publication number 20240006010
- Publication date Jan 4, 2024
- Western Digital Technologies, Inc.
- Xuan Tian
- G11 - INFORMATION STORAGE

using error correcting codes [ECC] or parity check

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Mitigation of transistor reliability degradation within memory circ...

Semiconductor memory device, controller, memory system and method o...

Programmable ECC for MRAM mixed-read scheme

Semiconductor apparatus related to a test function

Storage device and operating method of storage device

Single “A” latch with an array of “B” latches

NAND data placement schema

Tracking and refreshing state metrics in memory sub-systems

Early error detection and automatic correction techniques for stora...

Methods and apparatus to reduce read-modify-write cycles for non-al...

Memory device protection using interleaved multibit symbols

Methods and apparatus to facilitate atomic operations in victim cache

Memory apparatus and semiconductor system including the same

Topology-based retirement in a memory system

Linked XOR flash data protection scheme

Path based controls for ATE mode testing of multicell memory circuit

Signal generation circuit and method, and semiconductor memory

Dynamic error monitor and repair

Memory system

Generation of programming parameters for non-volatile memory device...

Data storage system with intelligent error management

Memory sense amplifier trimming

Data scrambling method that controls code density

Read command fault detection in a memory system

Reference voltage adjustment based on post-decoding and pre-decodin...

Optimized storage charge loss management

Hybrid memory system with configurable error thresholds and failure...

Interface read after write

Counter-based read in memory device

Memory device for column repair

Patents Applicationslast 30 patents

MEMORY WITH ERROR CHECKING AND CORRECTING UNIT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

Memory Testing Techniques

METHOD FOR MEMORY STORAGE AND ACCESS

MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING

NAND DATA PLACEMENT SCHEMA

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK

WEIGHTED WEAR LEVELING FOR IMPROVING UNIFORMITY

TESTING OPERATIONS FOR MEMORY SYSTEMS

BUILT-IN SELF-TEST CIRCUITRY

Mitigation of transistor reliability degradation within memory circ...

Error Correction for Stacked Memory

ERROR CORRECTION CODE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING...

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION

APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION

SEMICONDUCTOR MEMORY DEVICES THAT SUPPORT ENHANCED DATA RECOVERY OP...

READ-WRITE METHOD AND APPARATUS FOR LEPS SOFT DECODING ESTIMATION,...

INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST USING A DATA MAS...

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

APPARATUS FOR DETERMINING MEMORY CELL DATA STATES

SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

MEMORY, MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM

BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODUL...

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

ELECTRONIC CIRCUIT AND METHOD FOR SELF-DIAGNOSIS OF A DATA MEMORY

SEMICONDUCTOR CIRCUIT

SYSTEMS AND METHODS FOR MONITORING AND MANAGING MEMORY DEVICES

Storage System and Method for Proactive Die Retirement by Fatal Wor...