using scanning techniques

Industry

CPC
G01R31/318533

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318533using scanning techniques

Industries

Patents Grantslast 30 patents

Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to implement a boundary scan for shared analo...
- Patent number 12,130,329
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Grant
Reconfigurable JTAG architecture for implementation of programmable...
- Patent number 12,123,912
- Issue date Oct 22, 2024
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G01 - MEASURING TESTING
Information Patent Grant
Array of unit cells having pad structures
- Patent number 12,123,909
- Issue date Oct 22, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Ching Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
System of performing boundary scan test on pin through test point a...
- Patent number 12,025,660
- Issue date Jul 2, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Qiu-Yue Duan
- G01 - MEASURING TESTING
Information Patent Grant
Techniques to enable integrated circuit debug across low power states
- Patent number 11,933,843
- Issue date Mar 19, 2024
- Intel Corporation
- Keith A. Jones
- G01 - MEASURING TESTING
Information Patent Grant
DIMM slot test system without series connection of test board throu...
- Patent number 11,927,632
- Issue date Mar 12, 2024
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Chang-Qing Mu
- G01 - MEASURING TESTING
Information Patent Grant
Interposer instrumentation method and apparatus
- Patent number 11,860,224
- Issue date Jan 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Circuit simulation test method and apparatus, device, and medium
- Patent number 11,846,674
- Issue date Dec 19, 2023
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G01 - MEASURING TESTING
Information Patent Grant
Universal compactor architecture for testing circuits
- Patent number 11,815,555
- Issue date Nov 14, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 11,782,092
- Issue date Oct 10, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable scan chain debug technique
- Patent number 11,754,624
- Issue date Sep 12, 2023
- Seagate Technology LLC
- Bharat Londhe
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for scan testing
- Patent number 11,714,131
- Issue date Aug 1, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Terahertz plasmonics for testing very large-scale integrated circui...
- Patent number 11,675,002
- Issue date Jun 13, 2023
- The Government of the United States, as represented by the Secretary of the Army
- Greg Rupper
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for contemporary test time reduction for JTAG
- Patent number 11,662,382
- Issue date May 30, 2023
- Marvell Asia Pte, Ltd.
- Umesh Prabhakar Hade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for device access port selection
- Patent number 11,656,278
- Issue date May 23, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 11,604,222
- Issue date Mar 14, 2023
- Texas Instmments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power flip-flop
- Patent number 11,575,366
- Issue date Feb 7, 2023
- Samsung Electronics Co., Ltd.
- Hyunchul Hwang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan apparatus capable of fault diagnosis and scan chain fault diag...
- Patent number 11,567,132
- Issue date Jan 31, 2023
- UIF (University Industry Foundation), Yonsei University
- Sungho Kang
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,561,258
- Issue date Jan 24, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTAG bus communication method and apparatus
- Patent number 11,549,982
- Issue date Jan 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended JTAG controller and method for functional debugging using...
- Patent number 11,519,961
- Issue date Dec 6, 2022
- COMMSOLID GMBH
- Uwe Porst
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit
- Patent number 11,519,962
- Issue date Dec 6, 2022
- Realtek Semiconductor Corporation
- Jeong-Fa Sheu
- G01 - MEASURING TESTING
Information Patent Grant
Electronic circuit and corresponding method of testing electronic c...
- Patent number 11,486,928
- Issue date Nov 1, 2022
- STMicroelectronics S.r.l.
- Ignazio Pisello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Side-channel signature based PCB authentication using JTAG architec...
- Patent number 11,480,614
- Issue date Oct 25, 2022
- University of Florida Research Foundation, Inc.
- Swarup Bhunia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and/or system for testing devices in non-secured environment
- Patent number 11,480,613
- Issue date Oct 25, 2022
- ARM Limited
- Richard Andrew Paterson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus for device access port selection
- Patent number 11,448,697
- Issue date Sep 20, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
High speed debug hub for debugging designs in an integrated circuit
- Patent number 11,442,844
- Issue date Sep 13, 2022
- Xilinx, Inc.
- Michael E. Peattie
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ARRAY OF UNIT CELLS HAVING PAD STRUCTURES
- Publication number 20240369626
- Publication date Nov 7, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Yu-Ching CHIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME
- Publication number 20240295603
- Publication date Sep 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chia-En Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUS TO IMPLEMENT A BOUNDARY SCAN FOR SHARED ANALO...
- Publication number 20240288496
- Publication date Aug 29, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Application
INTERPOSER INSTRUMENTATION METHOD AND APPARATUS
- Publication number 20240133947
- Publication date Apr 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR ACCESSING REMOTE TEST DATA REGISTERS
- Publication number 20240103077
- Publication date Mar 28, 2024
- Intel Corporation
- Rakesh KANDULA
- G01 - MEASURING TESTING
Information Patent Application
Terahertz Plasmonics for Testing Very Large-Scale Integrated Circui...
- Publication number 20230393195
- Publication date Dec 7, 2023
- The Government of the United States, as Represented by the Secretary of the Army
- Greg Rupper
- G01 - MEASURING TESTING
Information Patent Application
SCAN COMPRESSION THROUGH PIN DATA ENCODING
- Publication number 20230375617
- Publication date Nov 23, 2023
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
TESTING CIRCUITRY FOR TESTING MULTICYCLE PATH CIRCUIT
- Publication number 20230349971
- Publication date Nov 2, 2023
- REALTEK SEMICONDUCTOR CORPORATION
- CHUN-YI KUO
- G01 - MEASURING TESTING
Information Patent Application
Array of Unit Cells Having Pad Structures
- Publication number 20230333158
- Publication date Oct 19, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Yu-Ching Chiu
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURABLE BOUNDARY SCAN
- Publication number 20230314509
- Publication date Oct 5, 2023
- Intel Corporation
- Rohini Krishnan
- G01 - MEASURING TESTING
Information Patent Application
DEVICE ACCESS PORT SELECTION
- Publication number 20230296670
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT SIMULATION TEST METHOD AND APPARATUS, DEVICE, AND MEDIUM
- Publication number 20230032066
- Publication date Feb 2, 2023
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Feng Lin
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS FOR DEVICE ACCESS PORT SELECTION
- Publication number 20220413041
- Publication date Dec 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
COMMUNICATION METHOD AND ITS SYSTEM BETWEEN INTERCONNECTED DIE AND...
- Publication number 20220276306
- Publication date Sep 1, 2022
- 58th Research Institute of China Electronics Technology Group Corporation
- Jinghe Wei
- G01 - MEASURING TESTING
Information Patent Application
INTERPOSER INSTRUMENTATION METHOD AND APPARATUS
- Publication number 20220260631
- Publication date Aug 18, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER FLIP-FLOP
- Publication number 20220247388
- Publication date Aug 4, 2022
- Samsung Electronics Co., Ltd.
- HYUNCHUL HWANG
- G01 - MEASURING TESTING
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20220146572
- Publication date May 12, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20220113351
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO ENABLE INTEGRATED CIRCUIT DEBUG ACROSS LOW POWER STATES
- Publication number 20220018901
- Publication date Jan 20, 2022
- Keith A. Jones
- G01 - MEASURING TESTING
Information Patent Application
Terahertz Plasmonics for Testing Very Large-Scale Integrated Circui...
- Publication number 20220011363
- Publication date Jan 13, 2022
- The Government of the United States, as Represented by the Secretary of the Army
- Greg Rupper
- G01 - MEASURING TESTING
Information Patent Application
DEBUG DATA COMMUNICATION SYSTEM FOR MULTIPLE CHIPS
- Publication number 20210389371
- Publication date Dec 16, 2021
- Intel Corporation
- Vui Yong Liew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JTAG BUS COMMUNICATION METHOD AND APPARATUS
- Publication number 20210215759
- Publication date Jul 15, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERPOSER INSTRUMENTATION METHOD AND APPARATUS
- Publication number 20210173001
- Publication date Jun 10, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION
- Publication number 20210165042
- Publication date Jun 3, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SIDE-CHANNEL SIGNATURE BASED PCB AUTHENTICATION USING JTAG ARCHITEC...
- Publication number 20210148977
- Publication date May 20, 2021
- University of Florida Research Foundation, Inc.
- SWARUP BHUNIA
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20210088584
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE SCAN COMPRESSION
- Publication number 20210072311
- Publication date Mar 11, 2021
- SEAGATE TECHNOLOGY LLC
- Bharat P. Londhe
- G01 - MEASURING TESTING
Information Patent Application
FPGA DEVICE AND CLOUD SYSTEM BASED ON FPGA DEVICE
- Publication number 20200233982
- Publication date Jul 23, 2020
- ALIBABA GROUP HOLDING LIMITED
- Xin Long
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20200217888
- Publication date Jul 9, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING

using scanning techniques

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Commanded JTAG test access port operations

Methods and apparatus to implement a boundary scan for shared analo...

Reconfigurable JTAG architecture for implementation of programmable...

Array of unit cells having pad structures

Scan compression through pin data encoding

System of performing boundary scan test on pin through test point a...

Techniques to enable integrated circuit debug across low power states

DIMM slot test system without series connection of test board throu...

Interposer instrumentation method and apparatus

Circuit simulation test method and apparatus, device, and medium

Universal compactor architecture for testing circuits

Scan compression through pin data encoding

Wafer scale testing using a 2 signal JTAG interface

Programmable scan chain debug technique

Circuit and method for scan testing

Terahertz plasmonics for testing very large-scale integrated circui...

Method and apparatus for contemporary test time reduction for JTAG

Apparatus for device access port selection

Commanded JTAG test access port operations

Low power flip-flop

Scan apparatus capable of fault diagnosis and scan chain fault diag...

Wafer scale testing using a 2 signal JTAG interface

JTAG bus communication method and apparatus

Extended JTAG controller and method for functional debugging using...

Test circuit

Electronic circuit and corresponding method of testing electronic c...

Side-channel signature based PCB authentication using JTAG architec...

Method and/or system for testing devices in non-secured environment

Apparatus for device access port selection

High speed debug hub for debugging designs in an integrated circuit

Patents Applicationslast 30 patents

ARRAY OF UNIT CELLS HAVING PAD STRUCTURES

DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME

METHODS AND APPARATUS TO IMPLEMENT A BOUNDARY SCAN FOR SHARED ANALO...

INTERPOSER INSTRUMENTATION METHOD AND APPARATUS

METHOD AND APPARATUS FOR ACCESSING REMOTE TEST DATA REGISTERS

Terahertz Plasmonics for Testing Very Large-Scale Integrated Circui...

SCAN COMPRESSION THROUGH PIN DATA ENCODING

TESTING CIRCUITRY FOR TESTING MULTICYCLE PATH CIRCUIT

Array of Unit Cells Having Pad Structures

CONFIGURABLE BOUNDARY SCAN

DEVICE ACCESS PORT SELECTION

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

CIRCUIT SIMULATION TEST METHOD AND APPARATUS, DEVICE, AND MEDIUM

APPARATUS FOR DEVICE ACCESS PORT SELECTION

COMMUNICATION METHOD AND ITS SYSTEM BETWEEN INTERCONNECTED DIE AND...

INTERPOSER INSTRUMENTATION METHOD AND APPARATUS

LOW POWER FLIP-FLOP

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

TECHNIQUES TO ENABLE INTEGRATED CIRCUIT DEBUG ACROSS LOW POWER STATES

Terahertz Plasmonics for Testing Very Large-Scale Integrated Circui...

DEBUG DATA COMMUNICATION SYSTEM FOR MULTIPLE CHIPS

JTAG BUS COMMUNICATION METHOD AND APPARATUS

INTERPOSER INSTRUMENTATION METHOD AND APPARATUS

METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION

SIDE-CHANNEL SIGNATURE BASED PCB AUTHENTICATION USING JTAG ARCHITEC...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

PROGRAMMABLE SCAN COMPRESSION

FPGA DEVICE AND CLOUD SYSTEM BASED ON FPGA DEVICE

COMMANDED JTAG TEST ACCESS PORT OPERATIONS