with a plurality of cache hierarchy levels

Industry

CPC
G06F12/0897

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0897with a plurality of cache hierarchy levels

Industries

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation support for a virtual cache
- Patent number 12,141,076
- Issue date Nov 12, 2024
- International Business Machines Corporation
- Markus Helms
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource-aware compression
- Patent number 12,130,741
- Issue date Oct 29, 2024
- Advanced Micro Devices, Inc.
- SeyedMohammad SeyedzadehDelcheh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One-dimensional zero padding in a stream of matrix elements
- Patent number 12,118,358
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forward caching memory systems and methods
- Patent number 12,111,764
- Issue date Oct 8, 2024
- Micron Technology, Inc.
- Harold Robert George Trout
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for vector permutation
- Patent number 12,105,635
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-based system for allocating cache lines to a higher-level...
- Patent number 12,093,184
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching techniques for deep learning accelerator
- Patent number 12,094,531
- Issue date Sep 17, 2024
- Micron Technology, Inc.
- Aliasger Tayeb Zaidy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing memory reads when computing video quality metrics
- Patent number 12,086,972
- Issue date Sep 10, 2024
- Meta Platforms, Inc.
- Deepa Palamadai Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling of threads for execution utilizing load balancing of thr...
- Patent number 12,086,602
- Issue date Sep 10, 2024
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for permuting streamed data elements
- Patent number 12,086,074
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Soujanya Narnur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load-store pipeline selection for vectors
- Patent number 12,086,067
- Issue date Sep 10, 2024
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Banked memory architecture for multiple parallel datapath channels...
- Patent number 12,079,137
- Issue date Sep 3, 2024
- Microsoft Technology Licensing, LLC
- Stephen Sangho Youn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache look up during packet processing by uniformly caching non-uni...
- Patent number 12,079,136
- Issue date Sep 3, 2024
- Fortinet, Inc.
- Shushan Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with fetch ahead hysteresis
- Patent number 12,079,470
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 12,072,812
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable latency instructions
- Patent number 12,067,396
- Issue date Aug 20, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual data streams sharing dual level two cache access ports to maxi...
- Patent number 12,061,908
- Issue date Aug 13, 2024
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cryptographic isolation of memory compartments in a computing envir...
- Patent number 12,050,701
- Issue date Jul 30, 2024
- Intel Corporation
- Michael E. Kounavis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache management operations using streaming engine
- Patent number 12,050,914
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage organization for transposing a matrix using a streaming engine
- Patent number 12,045,616
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Jonathan (Son) Hung Tran
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
- Publication number 20240385840
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
- Publication number 20240378158
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Soujanya Narnur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20240378058
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE
- Publication number 20240370264
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Jonathan (Son) Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector Based Matrix Multiplication
- Publication number 20240354259
- Publication date Oct 24, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SORTING VECTOR ELEMENTS USING A COUNT VALUE
- Publication number 20240354260
- Publication date Oct 24, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...
- Publication number 20240330203
- Publication date Oct 3, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS
- Publication number 20240330196
- Publication date Oct 3, 2024
- ADVANCED MICRO DEVICES, INC.
- Skyler J. SALEH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE CACHES FOR IMPROVING PERFORMANCE OF GRAPHICS PROCESS...
- Publication number 20240330195
- Publication date Oct 3, 2024
- QUALCOMM Incorporated
- Suryanarayana Murthy Durbhakula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART
- Publication number 20240320094
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TRANSFER IN PORT SWITCH MEMORY
- Publication number 20240319909
- Publication date Sep 26, 2024
- Lodestar Licensing Group LLC
- Frank F. Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Dual Issue Multiply Instructions
- Publication number 20240311313
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING A STREAM OF DATA USING A LOOKASIDE BUFFER
- Publication number 20240296050
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CO-COMPUTE UNIT IN LOWER-LEVEL CACHE ARCHITECTURE
- Publication number 20240264942
- Publication date Aug 8, 2024
- DaZheng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL...
- Publication number 20240248851
- Publication date Jul 25, 2024
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-AWARE PRE-FETCHING AND CACHE BYPASSING SYSTEMS AND METHODS
- Publication number 20240248849
- Publication date Jul 25, 2024
- Lodestar Licensing Group, LLC
- David Andrew Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR USING A STORAGE SYSTEM AS MAIN MEMORY
- Publication number 20240220411
- Publication date Jul 4, 2024
- FLC Technology Group, Inc.
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIERED MEMORY CACHING
- Publication number 20240220415
- Publication date Jul 4, 2024
- ADVANCED MICRO DEVICES, INC.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Multiplication Units in a Data Path
- Publication number 20240211411
- Publication date Jun 27, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL...
- Publication number 20240202131
- Publication date Jun 20, 2024
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH VARIABLE STREAM TEMPLATE FORMAT
- Publication number 20240202123
- Publication date Jun 20, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED MEMORY FOR GLASS CORE PACKAGES
- Publication number 20240203805
- Publication date Jun 20, 2024
- Intel Corporation
- Mohammad Mamunur RAHMAN
- G06 - COMPUTING CALCULATING COUNTING

with a plurality of cache hierarchy levels

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus for read-modify-write support in multi-banked...

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Atomic operations and histogram operations in a cache pipeline

Translation support for a virtual cache

Resource-aware compression

One-dimensional zero padding in a stream of matrix elements

Forward caching memory systems and methods

Methods and apparatus for eviction in dual datapath victim cache sy...

Method and apparatus for vector permutation

Multi-tile memory management

Compression techniques

Processor-based system for allocating cache lines to a higher-level...

Caching techniques for deep learning accelerator

Optimizing memory reads when computing video quality metrics

Scheduling of threads for execution utilizing load balancing of thr...

Method and apparatus for permuting streamed data elements

Load-store pipeline selection for vectors

Banked memory architecture for multiple parallel datapath channels...

Graphics processor operation scheduling for deterministic latency

Cache look up during packet processing by uniformly caching non-uni...

Streaming engine with fetch ahead hysteresis

Methods and apparatus to facilitate read-modify-write support in a...

Highly integrated scalable, flexible DSP megamodule architecture

Cache structure and utilization

Variable latency instructions

Dual data streams sharing dual level two cache access ports to maxi...

Cryptographic isolation of memory compartments in a computing envir...

Cache management operations using streaming engine

Storage organization for transposing a matrix using a streaming engine

Patents Applicationslast 30 patents

CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

Vector Based Matrix Multiplication

SORTING VECTOR ELEMENTS USING A COUNT VALUE

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...

GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS

RECONFIGURABLE CACHES FOR IMPROVING PERFORMANCE OF GRAPHICS PROCESS...

STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART

DATA TRANSFER IN PORT SWITCH MEMORY

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

Method and Apparatus for Dual Issue Multiply Instructions

VICTIM CACHE WITH WRITE MISS MERGING

CONVERTING A STREAM OF DATA USING A LOOKASIDE BUFFER

CO-COMPUTE UNIT IN LOWER-LEVEL CACHE ARCHITECTURE

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL...

MEMORY-AWARE PRE-FETCHING AND CACHE BYPASSING SYSTEMS AND METHODS

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

METHOD AND APPARATUS FOR USING A STORAGE SYSTEM AS MAIN MEMORY

TIERED MEMORY CACHING

Multiple Multiplication Units in a Data Path

PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL...

STREAMING ENGINE WITH VARIABLE STREAM TEMPLATE FORMAT

EMBEDDED MEMORY FOR GLASS CORE PACKAGES