with a plurality of cache hierarchy levels

Industry

CPC
G06F12/0897

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0897with a plurality of cache hierarchy levels

Industries

Patents Grantslast 30 patents

Information Patent Grant
Entering protected pipeline mode with clearing
- Patent number 12,321,750
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implicit fence for write messages
- Patent number 12,321,310
- Issue date Jun 3, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slot/sub-slot prefetch architecture for multiple memory requestors
- Patent number 12,321,282
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with stream metadata saving for context switching
- Patent number 12,299,446
- Issue date May 13, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for altering the path of data movement for larg...
- Patent number 12,299,301
- Issue date May 13, 2025
- QUALCOMM Incorporated
- Hithesh Hassan Lepaksha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for limiting data traffic while processing comp...
- Patent number 12,287,970
- Issue date Apr 29, 2025
- Mellanox Technologies, Ltd.
- Yamin Friedman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for facilitating external cache in a cloud storage environm...
- Patent number 12,287,763
- Issue date Apr 29, 2025
- NetApp, Inc.
- Brian Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing a cache based on an address translation buffer result
- Patent number 12,287,739
- Issue date Apr 29, 2025
- Advanced Micro Devices, Inc.
- Jagadish B. Kotra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cryptographic computing using encrypted base addresses and used in...
- Patent number 12,282,567
- Issue date Apr 22, 2025
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data flow-based neural network multi-engine synchronous calculation...
- Patent number 12,271,326
- Issue date Apr 8, 2025
- SHENZHEN CORERAIN TECHNOLOGIES CO., LTD.
- Li Jiao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-based system for allocating cache lines to a higher-level...
- Patent number 12,259,820
- Issue date Mar 25, 2025
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two address translations from a single table look-aside buffer read
- Patent number 12,235,773
- Issue date Feb 25, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable caches for improving performance of graphics process...
- Patent number 12,229,054
- Issue date Feb 18, 2025
- QUALCOMM Incorporated
- Suryanarayana Murthy Durbhakula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Draining operation for draining dirty cache lines to persistent memory
- Patent number 12,216,589
- Issue date Feb 4, 2025
- ARM Limited
- Wei Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor data cache with shared mid-level cache and low-level cache
- Patent number 12,210,457
- Issue date Jan 28, 2025
- Marvell Asia Pte, Ltd.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting predefined pad values into a stream of vectors
- Patent number 12,204,905
- Issue date Jan 21, 2025
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for storage virtualization
- Patent number 12,204,451
- Issue date Jan 21, 2025
- Dynavisor, Inc.
- Sreekumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Canceling prefetch of cache blocks based on an address and a bit field
- Patent number 12,197,335
- Issue date Jan 14, 2025
- SiFive, Inc.
- Eric Andrew Gouldey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for resource bandwidth enforcement
- Patent number 12,198,186
- Issue date Jan 14, 2025
- Intel Corporation
- Andrew Herdrich
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION
- Publication number 20250173266
- Publication date May 29, 2025
- Dynavisor, Inc.
- Sreekumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20250173308
- Publication date May 29, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS
- Publication number 20250156185
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CANCELING PREFETCH OF CACHE BLOCKS BASED ON AN ADDRESS AND A BIT FIELD
- Publication number 20250147761
- Publication date May 8, 2025
- SiFive, Inc.
- Eric Andrew Gouldey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR HANDLING CACHE UPDATES
- Publication number 20250130945
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Benjamin Crawford CHAFFIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING SYSTEM AND METHOD FOR POWER-SAVING COMPUTE-IN-MEMORY DESIGN
- Publication number 20250130950
- Publication date Apr 24, 2025
- MEDIATEK INC.
- Tso WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Preemptive Flushing of Processing-in-Memory Data Structures
- Publication number 20250110887
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- David Andrew Werner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Speculative Cache Invalidation for Processing-in-Memory Instructions
- Publication number 20250110886
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- Travis Henry Boraten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TEC...
- Publication number 20250112204
- Publication date Apr 3, 2025
- Intel Corporation
- Adel Elsherbini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING WRITE BUFFER SIZE IN NON-VOLATILE...
- Publication number 20250110888
- Publication date Apr 3, 2025
- KIOXIA Corporation
- Nigel David Horspool
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USER CONTROLLED ALLOCATION OF A SPECIFIC CACHE LINE AT TIME OF ACCESS
- Publication number 20250103507
- Publication date Mar 27, 2025
- International Business Machines Corporation
- Scot RIDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...
- Publication number 20250103510
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE RING CACHE ARCHITECTURE
- Publication number 20250077428
- Publication date Mar 6, 2025
- ARKOSE LABS HOLDINGS, INC.
- Du Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL-TIME SNOOP STATUS
- Publication number 20250077430
- Publication date Mar 6, 2025
- International Business Machines Corporation
- Scot RIDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSISTENT FILE SYSTEM SEMANTICS WITH CLOUD OBJECT STORAGE
- Publication number 20250068593
- Publication date Feb 27, 2025
- ORACLE INTERNATIONAL CORPORATION
- Mark Maybee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20250036411
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THR...
- Publication number 20250036451
- Publication date Jan 30, 2025
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING

with a plurality of cache hierarchy levels

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Entering protected pipeline mode with clearing

Methods and apparatus to facilitate atomic operations in victim cache

Implicit fence for write messages

Slot/sub-slot prefetch architecture for multiple memory requestors

Victim cache with write miss merging

Streaming engine with stream metadata saving for context switching

Methods and systems for altering the path of data movement for larg...

Write merging on stores with different privilege levels

Methods and systems for limiting data traffic while processing comp...

Methods for facilitating external cache in a cloud storage environm...

Accessing a cache based on an address translation buffer result

Cryptographic computing using encrypted base addresses and used in...

Data flow-based neural network multi-engine synchronous calculation...

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Processor-based system for allocating cache lines to a higher-level...

Data initialization techniques

Two address translations from a single table look-aside buffer read

Reconfigurable caches for improving performance of graphics process...

Draining operation for draining dirty cache lines to persistent memory

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Processor data cache with shared mid-level cache and low-level cache

Inserting predefined pad values into a stream of vectors

Graphics processor data access and sharing

Method and system for storage virtualization

Canceling prefetch of cache blocks based on an address and a bit field

Methods and apparatus to reduce bank pressure using aggressive writ...

Systems, apparatuses, and methods for resource bandwidth enforcement

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS

DATA INITIALIZATION TECHNIQUES

CANCELING PREFETCH OF CACHE BLOCKS BASED ON AN ADDRESS AND A BIT FIELD

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

SYSTEM AND METHOD FOR HANDLING CACHE UPDATES

COMPUTING SYSTEM AND METHOD FOR POWER-SAVING COMPUTE-IN-MEMORY DESIGN

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

Preemptive Flushing of Processing-in-Memory Data Structures

Speculative Cache Invalidation for Processing-in-Memory Instructions

DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TEC...

SYSTEMS AND METHODS FOR REDUCING WRITE BUFFER SIZE IN NON-VOLATILE...

USER CONTROLLED ALLOCATION OF A SPECIFIC CACHE LINE AT TIME OF ACCESS

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

DOUBLE RING CACHE ARCHITECTURE

REAL-TIME SNOOP STATUS

CONSISTENT FILE SYSTEM SEMANTICS WITH CLOUD OBJECT STORAGE

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PADDING IN A STREAM OF MATRIX ELEMENTS

SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THR...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES