Patent Application
20250112204
In semiconductor manufacturing, layer transfer techniques are used to transfer a layer from one substrate to another, typically at wafer-level scale. These techniques require a full layer to be transferred in its entirety regardless of whether the entire layer is needed. As a result, any unneeded portions of a transferred layer must be etched off after the transfer, which increases costs and process complexity.
In semiconductor manufacturing, layer transfer techniques are used to transfer a layer from one substrate to another, typically at wafer-level scale. Layer transfers are useful for a variety of applications in semiconductor manufacturing, including two-dimensional (2D) material fabrication, Group III-V semiconductors over complementary metal-oxide semiconductors (CMOS), and traditional CMOS applications such as metal-insulator-metal (MIM) devices and thin device and/or interconnect layer transfers. Current layer transfer techniques are limited to full layer transfers, however, which may impact cost and performance when the full layer is not needed. For example, blanket layer transfer techniques, such as ion-cut and laser debonding layer transfers, require a full layer to be transferred in its entirety. As a result, any unneeded areas of the transferred layer must be etched off after the transfer, which results in added cost and process complexity.
Alternatively, pick-and-place techniques can be used to transfer specific dies or chiplets. For example, a chiplet generally refers to an integrated circuit (IC) that contains a well-defined subset of functionality, which is designed to be combined with other chiplets to form a single IC package. To transfer chiplets (e.g., for MIM chiplet integration in a system-on-a-chip (SoC)), chiplet devices are fabricated on a donor substrate (e.g., a wafer or panel), the donor substrate is singulated into chiplets, and the chiplets are then individually attached to a receiver substrate (e.g., an SoC wafer or package) using pick-and-place machines. This adds significant cost due to the extra processing required to singulate the wafer and individually attach the respective chiplet dies. For example, chiplets are generally manufactured on relatively thick substrates to enable them to be handled during the singulation and attach steps without being damaged, and after the attach step, additional processing is performed to thin the chiplets and/or remove the carrier substrate, which further increases the cost and process complexity. In particular, chiplets are typically manufactured on substrates that are over 700 micrometers (μm or microns) thick to provide structural and mechanical stability during fabrication, and after the singulation/attach steps, they may be thinned to approximately 20-100 μm by grinding the backside. However, grinding typically causes chipping along the edges of the chiplet dies. Further, it can be challenging to thin chiplets beyond 20 μm without producing defects. Similarly, chiplets are typically singulated with a die area on the millimeter level scale, as pick-and-place assembly becomes very challenging for chiplets smaller than 1 millimeter (mm)2.
Integrated circuits can also be manufactured monolithically, where all IC components and interconnections are fabricated sequentially on the same underlying substrate or wafer. Monolithic ICs have various limitations, however, including design limitations due to incompatible processes, lack of flexibility, and low yield.
Accordingly, this disclosure presents selective layer transfer techniques for selectively transferring portions of a layer between substrates, along with devices and systems formed using the same. For example, one or more of the described techniques enable select areas on a donor substrate to be transferred to a receiver substrate, which enables the donor substrate to be reused multiple times, while also addressing the limitations described above for blanket layer transfers and pick and place techniques. In particular, the described solution (e.g., one or more of the embodiments described herein) uses a selective release technology on a donor substrate (e.g., wafer, panel, or die) in conjunction with a patterned bonding template on a receiver substrate (e.g., wafer, panel, or die) to allow select areas of a layer on the donor substrate to be transferred to the receiver substrate. For purposes of this disclosure, the term layer may sometimes be used to refer to a single layer of a single material or multiple layers of one or more materials. For example, a selective transfer layer may be formed on a substrate, and may be an individual layer of material, or a stack of layers that collectively form a layer of IC components (e.g., dies, interconnects, bridges, capacitors, and/or other semiconductor devices). A layer may also include stacked wafers, such as wafer-to-wafer bonded and stacked logic and/or memory wafers. As an example, a donor wafer may include a layer of IC components (e.g., IC dies), and a selective layer transfer may be used to selectively and simultaneously transfer a specific subset of those IC components to a receiver wafer.
The described solution provides various advantages. For example, the described solution enables select areas of a donor wafer to be transferred as opposed to an entire layer, which enables the donor wafer to be reused for multiple products, thus amortizing the cost of expensive devices (e.g., high-density MIM capacitors or high-density passive interposers) across multiple wafers. This solution also eliminates the need to etch away superfluous areas as required by full layer transfers (and as a result, unlike the etched areas after a full layer transfer, selectively transferred areas may not have tapered edges from etching or may have reversed tapering due to the etch to singulate before transfer).
Further, in various examples, layers of IC components can be selectively transferred at any suitable level of granularity, including full IC dies and packages, interconnects, transistors, resistors, capacitors, partial layers or layer stacks, etc.
This solution also enables areas of ultra-thin layers to be selectively transferred without the added processing and yield loss resulting from the handling challenges of chiplet pick-and-place methods (e.g., singulation, individually attaching each chiplet, post-attach thinning of chiplets). This helps reduce the Z-height of a product (e.g., for form factor, thermal, and/or power delivery reasons) as well as the overall process complexity. For example, very thin IC dies or chiplets can be formed on any substrate and selectively transferred directly from that substrate. As a result, selectively transferring the dies not only eliminates the need for post-attach thinning, it also enables the dies to be much thinner than dies that are singulated, pick-and-place attached, and then subsequently thinned. In some cases, for example, the described solution may enable transfers of dies with thicknesses ranging from 100 nanometers (nm) to 5 μm or more. Further, since no post-attach thinning is needed, the selectively transferred dies may have no or minimal chipping on the die edges since no grinding is performed, unlike chiplets that are thinned after attachment.
Similarly, the described solution supports selective transfers of very small areas on a donor substrate, such as very small dies or chiplets, which is extremely challenging using pick-and-place techniques. In some cases, for example, the described solution may enable transfers of dies (or other IC components) with an area less than 1 mm2, such as 100 μm2 (10×10 μm), 10,000 μm2 (100×100 μm), 810,000 μm2 (900×900 μm), etc. (with no limits on the maximum size of an area that can be selectively transferred).
This solution also supports selective transfers of dies with non-standard shapes and designs that are difficult to handle using pick-and-place machines, such as dies with atypical, arbitrary, irregular, or non-convex shapes (e.g., L shape, U shape, shapes with acute angles), dies with high aspect ratios (e.g., 8:1 aspect ratio or higher), dies with holes, and so forth.
Further, this solution has very low topography and supports high surface cleanliness and planarization (e.g., using chemical mechanical polishing (CMP) processing), which makes it compatible with hybrid bonding and fusion bonding processing. Additional advantages are described throughout this disclosure and apparent from the description below.
Accordingly, this solution enables complex IC packages and products to be manufactured by selectively transferring certain components (e.g., active circuitry such as IC dies, passive circuitry) instead of incorporating them using traditional processes, such as: (i) full layer transfers with superfluous areas etched away; (ii) pick-and-place assembly of individual IC components; and/or (iii) monolithic IC fabrication.
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The layer 104 to be selectively transferred is formed over the release layer 102 on the donor substrate 100, such as by fabricating the layer 104 directly (e.g., over the release layer 102) or blanket transferring the layer 104. The selective transfer layer 104 may include one or more layers of material, such as a single layer of material or a stack of layers that collectively form a layer of IC components (e.g., full IC dies, chiplets, interconnects, bridges, capacitors, transistors, and/or other semiconductor devices). In some embodiments, for example, the selective transfer layer 104 may be a prefabricated semiconductor wafer containing unsingulated integrated circuit (IC) dies, which is blanket transferred to the release layer 102 on a donor substrate 100.
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Next, a bonding template comprising bonding features 114 is formed on the surface of the receiver substrate 110 (e.g., above the release layer 112, if included). The bonding template includes a pattern of bonding features 114 or adhesive areas that enable specific areas on the donor substrate 100 to be selectively transferred to the receiver substrate 110. For example, the positions of the bonding features 114 or adhesive areas on the receiver substrate 110 correspond to the areas or IC components 106 on the donor substrate 100 that will be transferred to the receiver substrate 110.
In some embodiments, for example, the bonding features 114 may include “island” or “mesa” structures that are similar in size to the target areas to be transferred from the donor substrate 100. For example, each island or mesa structure may be a raised structure on the surface of the receiver substrate 110 with a similar footprint (e.g., shape/surface area) as a corresponding IC component 106 on the donor substrate 100. In other embodiments, the bonding features 114 may be replaced by lithographically or additively manufactured surface treatments that enhance the adhesion in the target areas of the receiver substrate 110 (e.g., the areas where the bonding features 114 are shown) and prevents adhesion in the other areas, including, without limitation, surface topography variations, use of materials with high and/or low adhesion, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques, among other examples.
In various embodiments, these bonding features 114 may be made of dielectric materials, conductive materials (e.g., metal), or both, depending on whether electrical connections are needed between the bonded IC components 106 and the receiver substrate 110. For example, the bonding features 114 may be blanket dielectric structures with no electrical contacts, or they may be dielectric structures with electrical contacts through them (e.g., hybrid bonding pads) if electrical connections are needed through the bonding interface.
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It should be appreciated that the illustrated process flow for selective layer transfers is merely presented as an example and many other process variations are also possible. For example, the donor and receiver substrates 100, 110 may be wafers, panels, IC packages, chiplets, dies, or any combination thereof (e.g., for transfers from wafer to panel, chiplet to wafer, etc.). Moreover, each substrate 100, 110 may be made of a variety of materials, including, without limitation, inorganic materials such as silicon, silicon on insulator (SOI), quartz, glass, and/or Group III-V materials, organic materials such as IR or UV transparent epoxies, and so forth.
The materials used in the release layers 102, 112 may vary depending on the type of release or debonding technology used. For example, for infrared (IR) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing and/or reflecting infrared (IR) light, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For ultraviolet (UV) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing UV light (e.g., a wide range of organic polymers, including, but not limited to, polyimides). In some embodiments, the release layers 102, 112 may additionally or alternatively include one or more layers of dielectric materials (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)), which may be used to buffer laser ablation and thermal energy, control thin film interference or adhesion, and/or provide residual adhesion after other materials and/or layers in the release layers 102, 112 are weakened, removed, and/or ablated by a laser.
The number of layers 104 on the donor substrate 100, the arrangement/structure of the layers 104, the materials in each layer 104, and the type of IC components 106 formed in those layers 104 may vary.
The adhesive areas or bonding features 114 on the receiver substrate 110 may be formed using any suitable surface treatments or other techniques to control the level of adhesion in different areas, including, without limitation, surface topography variations (e.g., mesas, recesses), use of materials with high and/or low adhesion, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques, among other examples. Moreover, the bonding features 114 or adhesive areas on the receiver substrate 110 may vary in size, shape, height, topography, pattern, and materials. For example, the bonding features 114 may be formed using inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxy nitride (SiON), and/or silicon carbon nitride (SiCN), organic dielectrics such as photoresists and adhesives, conductive materials such as metals, and combinations thereof.
The donor and receiver substrates 100, 110 may be (partially) bonded using any suitable bonding techniques, including, without limitation, hybrid bonding, fusion bonding, and adhesive bonding. The donor and receiver substrates 100, 110 may be debonded or released using any suitable debonding techniques, including, without limitation, IR and UV laser debonding. Further, there may be additional cleaning steps to reuse the donor substrate 100 before or after each selective layer transfer to a receiver substrate 110.
Further, in some embodiments, additional bonding and/or alignment features may be included at the wafer level and/or die level (e.g., on the donor dies, donor wafer, receiver wafer, and/or final product). For example, the donor and/or receiver wafer may include ridge or cross structures to facilitate bonding, such as a single ridge (e.g., a line or strip of dielectric material) extending across and/or through the center of the wafer, or multiple orthogonal ridges forming a cross-like pattern. Alignment features for wafers, die-lets, and/or die arrays may also be included to facilitate bonds with proper alignment. Further, multiple dies may be connected by small (e.g., dielectric) bridges to help them collectively bond and transfer together. For example, if some of the bridge-connected dies successfully bond to the receiver, the bridges may help others bond as well. Thus, these inter-die bridges may be present on the donor before the transfer, and on the receiver and final product after the transfer.
Further, in some cases, the debonding process may cause some unique damage or delamination near the edge and/or on the back of the dies, which does not impact process performance but may be indicative of this solution being used.
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Next, a bonding template 214 is formed on the surface of the receiver substrate 210 (e.g., above the release layer 212, if included). The bonding template 214 includes a pattern of bonding features or adhesive areas, such as mesas, that enable specific areas on the donor substrate 200 to be selectively transferred to the receiver substrate 210. In various embodiments, however, any suitable surface treatments or other techniques may be used to control the level of adhesion on different areas of the receiver substrate 210 (e.g., to form adhesive and non-adhesive areas for selective transfers), including, without limitation, surface topography variations (e.g., mesas, recesses), use of materials with high and/or low adhesion, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques, among other examples.
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Alternatively, in some embodiments, instead of (or in addition to) performing blanket laser exposure in
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Alternatively, in some embodiments, instead of (or in addition to) performing a blanket laser exposure in
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The process may repeat in this manner until all IC components 306 on the donor die 301 have been transferred. At that point, the bond head 320 may pick up another donor die 301 and continue transferring IC components 306 from the new donor die 301 to the same or different receiver substrate 310.
After all transfers to the receiver substrate 310 are complete, the receiver 310 may be ready for continued processing, such as dielectric fill around the transferred IC components 306, planarization, selectively transferring or pick-and-place attaching additional IC dies or other IC components, via formation, formation of interconnect/metallization layers, attaching a structural substrate, debonding the receiver substrate (e.g., via the optional receiver release layer 312), and/or any other processing required for the finished product (e.g., an IC package).
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Additional processing may then be performed on the receiver substrate 450, such as cleaning steps (e.g., removing the leftover bonding structures 424, 444 from the transferred IC components 414, 434), dielectric fill around the transferred IC components 414, 434, planarization, selectively transferring or pick-and-place attaching additional IC dies or other IC components, via formation, formation of interconnect/metallization layers, attaching a structural substrate, debonding the receiver substrate (e.g., via the optional receiver release layer 452), and/or any other processing required for the finished product (e.g., an IC package).
It should be appreciated that the illustrated process flow for selective layer transfers is merely presented as an example and many other process variations are also possible, including, but not limited to, the process variations described throughout this disclosure.
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The bonding mesa of the transfer template 516 is used to selectively transfer a D2D interconnect 506 from the donor 502 to the receiver 512 (e.g., using any of the selective transfer flows described throughout this disclosure). For example, the donor 502 and receiver 512 are aligned face to face, stacked, and then partially bonded together such that one of the D2D interconnects 506 on the donor 502 is bonded to the bonding mesa of the transfer template 516 on the receiver 512.
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Notably, since the D2D interposer 506 was selectively transferred while the surrounding dielectric layers 510 were fabricated directly on the receiver 512, there is a seam 511 between the transferred D2D interposer 506 and the surrounding layers 510, as shown in
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The dies 518a-b may be attached using standard assembly techniques, such as pick and place, or using the selective transfer techniques described herein (e.g., similar to the transferred D2D interconnect 506).
If the dies 518a-b are attached using pick-and-place assembly, they are typically formed on a thick substrate for handling purposes and then subsequently thinned after the attach.
If the dies 518a-b are selectively transferred, however, they can be formed on—and transferred directly from—a very thin substrate. As a result, selectively transferring the dies 518a-b not only eliminates the need for post-attach thinning, it also enables the dies 518a-b to be much thinner than dies that are pick-and-place attached and subsequently thinned. Further, if the dies 518a-b are selectively transferred, there may be a seam 511 between the dies 518a-b and portions of the layers 510 surrounding the dies 518a-b, similar to the seam 511 shown around the transferred D2D interconnect 506, as described above. Moreover, because the dies 518a-b are selectively transferred, they can be different types of dies, formed on separate pieces of substrate material (e.g., separate wafers or panels) using separate processes, and then selectively transferred to the same layer of an IC device 500.
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At this point, the IC package 500 may be complete, or alternatively, additional processing may be performed. For example, if the processing is performed at the wafer or panel level, the resulting IC packages 500 on the structural substrate 520 may be singulated.
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While the illustrated example depicts a selective transfer between two wafers, selective transfers can be performed between panels or other substrates of any shape or size, including substrates with mismatched shapes and sizes.
The flowchart begins at block 702 by receiving a first substrate with a layer of integrated circuit (IC) components, which may be referred to as the donor substrate. In some embodiments, the donor substrate may include a base substrate, a release layer over the base substrate, and a (partially singulated) layer of IC components over the release layer.
In some embodiments, the donor substrate may be formed by receiving the base substrate, forming the release layer over the base substrate, forming the layer of IC components over the release layer (e.g., by fabricating or transferring the layer of IC components over the release layer), and partially singulating the layer of IC components (e.g., by dicing through the layer of IC components without dicing through the base substrate).
In various embodiments, the layer of IC components may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical components, and/or any other active or passive circuitry or components.
The base substrate may be made of one or more materials that include elements such as silicon (Si), oxygen (O), carbon (C), hydrogen (H), and/or Group III-V elements (e.g., aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), including, without limitation, silicon (Si), silicon dioxide (silica or SiO2), silicon on insulator (SOI), quartz, glass, Group III-V materials (e.g., gallium nitride (GaN), aluminum gallium nitride (GaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP)), and epoxies/resins (e.g., IR or UV transparent epoxies).
The release layer may include one or more layers of varying materials depending on the type of release or debonding technology used. For example, for IR laser debonding, the release layer may include one or more layers of material(s) capable of absorbing and/or reflecting infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser debonding, the release layer may include one or more layers of material(s) capable of absorbing ultraviolet (UV) electromagnetic radiation (e.g., organic polymers such as polyimides). In some embodiments, the release layer may additionally or alternatively include one or more layers of dielectric materials to buffer laser ablation and thermal energy, control thin film interference or adhesion, and/or provide residual adhesion after other materials and/or layers in the release layers are weakened, removed, and/or ablated by a laser (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)). Thus, in some embodiments, the release layer(s) may be made of one or more materials that include elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H), and carbon (C), including, without limitation, any of the materials referenced above.
The flowchart then proceeds to block 704 to receive a second substrate with one or more adhesive areas, which may be referred to as the receiver substrate. In some embodiments, the receiver substrate may include a base substrate patterned with one or more adhesive areas on the surface, such as a layer of raised bonding structures or “mesas” over the base substrate. The receiver substrate may also optionally include a release layer over the base substrate (e.g., to enable the base substrate to be subsequently debonded after the transfer) and/or one or more additional buildup layers and/or IC components.
In some embodiments, the receiver substrate may be formed by receiving the base substrate, optionally forming a release layer over the base substrate, optionally forming additional buildup layers and/or IC components over the base substrate (e.g., over the optional release layer, if included), and forming the adhesive areas (e.g., bonding structures) on the surface of the receiver substrate (e.g., over the previously referenced layers, if included). In some embodiments, the base substrate and the optional release layer of the receiver may be made of any of the materials referenced above for the base substrate and the release layer of the donor, respectively.
In some embodiments, the adhesive areas may include mesa structures with similar footprints as the corresponding IC components to be transferred from the donor (although, in some cases, the mesas may be slightly larger or smaller than the IC components to accommodate alignment and manufacturing tolerances). The mesa structures may be made of varying materials depending on the type of bond and/or whether electrical connections are needed through the bond interface for the subsequently bonded IC components (e.g., dielectric material, metal, or both). For example, the mesa structures may include blanket dielectric structures with no conductive contacts (e.g., for dielectric-to-dielectric bonds), dielectric structures with conductive contacts (e.g., for hybrid dielectric and metal bonds), and/or conductive contacts by themselves (e.g., for metal-to-metal bonds). Thus, in some embodiments, the mesa structures may be made of one or more materials that include elements such as silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), including, without limitation, inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), and/or silicon carbon nitride (SiCN), organic dielectrics such as photoresists and adhesives, and/or conductive materials such as metals and alloys (e.g., any of the foregoing metal elements and/or compounds/alloys thereof).
In various embodiments, however, any suitable technique(s) may be used to control the level of adhesion on different areas of the receiver substrate. For example, a variety of surface treatments (e.g., lithographically or additively manufactured) can be used to enhance and/or reduce adhesion in select areas of the receiver substrate, including, without limitation, modifying the surface topography (e.g., raised vs. recessed areas, smooth vs. rough areas), use of materials with high and/or low adhesion (e.g., forming layers with adhesive and non-adhesive materials in select areas), treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques (e.g., plasma or wet activation), among other examples.
For example, the surface topography of the receiver substrate may be modified (e.g., using techniques such as deposition, lithography, etching, roughening) to form areas with different levels of adhesion, such as raised (e.g., adhesive) and recessed (e.g., non-adhesive) areas, smooth (e.g., adhesive) and rough (e.g., non-adhesive) areas, etc.
As another example, the surface of the receiver substrate may be patterned with materials having high and/or low adhesion in select areas. For example, a layer patterned with different areas of adhesive and non-adhesive materials may be formed on the receiver substrate. In some embodiments, the adhesive material may include silicon dioxide (SiO2) or silicon carbon nitride (SiCN) to promote strong oxide fusion bonds, silicon carbide (SiC) to provide lower thermal contact resistance compared to SiO2 or SiCN, and/or metal to form electrical connections. Further, in some embodiments, the non-adhesive material may include silicon nitride (Si3N4) to form weak or no bonds.
As another example, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs) may be used to enhance and/or reduce adhesion in select areas of the receiver substrate (e.g., using a SAM treatment to create monolayers with high and/or low adhesion in select areas). In some embodiments, the hydrophobic material may include a SAM material such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecane thiol), a phosphonic acid (e.g., octadecyl or perfluorooctane phosphonic acid), or an alkanoic acid (e.g., heptadecanoic acid). However, non-SAM based materials or films may also be used. In some embodiments, the hydrophobic material may include a thin polymer film such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized films, etc.). Other hydrophobic materials may be used in other embodiments.
As another example, surface activation techniques may be used to enhance and/or reduce adhesion in select areas of the receiver substrate, including, without limitation, plasma or wet activation.
The flowchart then proceeds to block 706 to partially bond the donor substrate to the receiver substrate (e.g., face to face), such that one or more target IC components on the donor substrate are selectively bonded to the one or more adhesive areas on the receiver substrate. The donor and receiver substrates may be partially bonded using any suitable bonding techniques, including, without limitation, hybrid bonding, fusion bonding, and/or adhesive bonding.
The flowchart then proceeds to block 708 to release the target IC components from the donor substrate and separate the donor substrate from the receiver substrate. In this manner, when the donor and receiver substrates are separated, the target IC components are separated from the donor substrate and remain on the receiver substrate.
In some embodiments, the donor and receiver substrates may be debonded/separated from each other by releasing, at least partially, the target IC components from the release layer of the donor substrate and then mechanically separating the donor and receiver substrates. For example, in some embodiments, the target IC components may be fully released from the donor substrate by selectively debonding them from the donor release layer using a laser (e.g., an IR or UV laser), or alternatively, the target IC components may be partially released from the donor substrate by weakening the donor release layer using a laser (e.g., an IR or UV laser). After fully or partially releasing the target IC components from the donor, the donor and receiver substrates are mechanically separated, and post separation, the target IC components remain bonded to the receiver and are no longer on the donor.
Alternatively, or additionally, the donor release layer and the receiver bonding structures may be formed with respective materials that have disparate bond strengths-such that the target IC components have a stronger bond to the receiver than the donor-thus causing the target IC components to debond from the donor and remain on the receiver when the donor and receiver are mechanically separated.
The flowchart then proceeds to block 710 to perform any remaining processing, such as dielectric filling and planarization, attaching additional IC dies or components (e.g., via selective transfers or pick-and-place assembly), forming interconnects (e.g., vias, traces), attaching a structural substrate, debonding the receiver base substrate (e.g., via the optional receiver release layer), and/or any other processing required for the finished product (e.g., an IC package, device, system, etc.).
The completed product may include a variety of components and circuitry (some of which may have been selectively transferred), including electrical components (e.g., electronic integrated circuits (EICs), processors (including XPUs), controllers, memory), optical components (e.g., optical interfaces, photonic integrated circuits (PICs), optical connectors, fibers), and/or radio frequency (RF) or high-voltage components (e.g., high-voltage electrostatic discharge (ESD) devices, power amplifiers (PAs), low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), surface acoustic wave (SAW)/bulk acoustic wave (BAW) devices or filters, bandpass filters (BPFs), intermediate-frequency (IF) amplifiers, frequency synthesizers, mixers, RF digital-to-analog converters (DACs), RF analog-to-digital converters (ADCs), thick gate oxide devices, Group III-V devices/chiplets, passive RF devices such as interconnects, antennas, and inductors).
Further, in some embodiments, the resulting IC package or product may be electrically coupled to a circuit board and/or incorporated into an electronic device or system (e.g., with other electronic components).
At this point, the flowchart may be complete. In some embodiments, however, the flowchart may restart and/or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block 702 to continue performing selective transfers.
To achieve overall system performance improvement every generation, the silicon process node needs to offer improvements in performance, power, and density. The intrinsic limitations in process scaling in the angstrom nodes and the need to support multiple types of circuits in the silicon chip present obstacles to achieving consistent performance improvements.
One potential solution to enable power improvements is to utilize special purpose CPUs or special accelerators for commonly used instructions. However, these components may require a larger area of silicon, result in added leakage, and may result in inefficient utilization depending on the workload.
Another potential solution is heterogeneous integration, where the memory and the CPU are disaggregated onto different dies and stacked. Unfortunately, this approach generally results in thermal challenges and power delivery challenges. Furthermore, this approach only enables coarse level disaggregation, since fine level disaggregation is very challenging with general techniques.
Yet another potential solution includes special process features, such as back end of line transistors, novel memories, and other innovations to enable separate logic and memory scaling. This approach may be lower cost than heterogeneous integration, but it suffers from similar challenges.
Various embodiments of the present disclosure utilize selective transfer technology (such as any of the techniques described above) to enable ultra-fine grain heterogeneous integration of different CPU components, wherein various components of one or more CPUs may be placed on individual dies next to and/or stacked on each other and coupled together.
Various embodiments may provide technical advantages such as one or more of the following. Circuits may be disaggregated onto dies and die stacks in a very flexible manner, enabling each type of circuit to be optimized separately. Unlike standard 3D stacking, a circuit may comprise a 2D or 3D set of dies (also referred to herein as chiplets), enabling optimization of the power and thermal characteristics for each component to avoid thermal hotspots or areas with power delivery chokepoints. Unlike standard heterogeneous integration approaches, the proposed techniques enable very low cost re-integration. Due to the fine pitch and high throughput made possible using the proposed techniques, very low overhead integration of a very large number of chiplets may be enabled. Flexibility to disaggregate a full system or parts of the system may enable improved testability of subsystems.
Further disaggregation of the CPU onto additional dies or die stacks using traditional assembly techniques is difficult due to the speed of assembly tools. For example, a wafer including dies that each include a single processing core could have up to ˜500,000 individual dies. Assembly of dies from such a wafer using traditional assembly techniques may be time prohibitive. However, use of selective transfer technology makes finer grain disaggregation of a CPU feasible by allowing the transfer of multiple dies at once, significantly speeding up the assembly process.
In
The bonding features 902 enable non-template based transfer of interconnect dies (e.g., interconnect bridges 906). In various embodiments, interconnect bridges 906 are transferred from a donor substrate using a selective transfer technique (such as any of those described above). For example, each of the bridges 906 may be on a separate die of the donor substrate and the dies may be transferred to the bonding features 902 concurrently (e.g., while other dies comprising other bridges 906 are left behind on the donor substrate).
A bridge 906 may comprise a plurality of vias, metal layers, and conductive pads (e.g., hybrid bonding pads). The bridges 906 provide a high connection density for die-to-die interconnects. A bridge 906 may be active or passive. In alternative embodiments, one or more passive interposers may be used in addition to or as an alternative to the bridges for the die-to-die interconnect.
In
A first hybrid bonding pad layer 914 is then created by forming hybrid bonding pads at the top portion of the dielectric 908 in locations at which dies are to be bonded. A protection layer (e.g., an etch stop) may then be formed over the layer 914. Subsequently, a second hybrid bonding pad layer 916 is formed over the first bonding pad layer 914. The second layer 916 may include hybrid bonding pads within a dielectric 918 in areas 920 where bonding features (e.g., mesas) are desired (e.g., for the selective transfer of dies), but just the dielectric over bonding pads of the first layer 914 in areas 922 where the bonding features are not desired. The protection layer may be removed where the pads of the second layer 916 are formed so that they can connect to the pads of the first layer 914. Other types of very fine pitch assembly are also possible such as direct metal to metal bonding.
The dielectric 918 may be the same material as dielectric 908 or may be a different material. In either event, a seam would likely be present between the dielectric 908 and 918. If certain materials are used as the dielectric (e.g., silicon dioxide), then a thin adhesion layer (e.g., silicon nitride) may be placed between dielectric 908 and 918.
In
At this stage, hybrid bondable surfaces are now available at two different heights, with one height including the bonding features 924, and one height omitting the bonding features. These hybrid bonding planes with different steps may be used to enable both template based (with an intermediate carrier) and non-template based (without intermediate carrier) die transfer techniques. In some embodiments, multiple sets of bonding features 924 may be separated from each other by a common pitch (facilitating selective transfer from a donor wafer). The structure shown here assumes no intermediate carrier is used. In scenarios where intermediate carriers are used, the additional structures 924 may be omitted.
In
In
A support carrier 940 may be bonded on top to provide structural stability. The bonding may be provided through an inorganic layer (e.g., SiO2, SiN), organic adhesive, or other suitable mechanism.
In
The resulting system 900 may then be assembled to a package (e.g., an organic package) or connected directly to a printed circuit board (e.g., motherboard), silicon or glass interposer, or any other type of interconnect.
In some embodiments, the manufacturing flow may be performed in a different order. For example, as shown in
The dies and die stacks of system 900 (or other systems shown herein) may represent any suitable disaggregation of a CPU. As just one example, the dies 926 and 928 may each include one CPU core, die stacks 930 and 932 may collectively include an L1 and L2 cache, and die stacks 934 and 936 may include an L3 cache.
Any suitable dies (including die stacks) may be assembled together in the manner described above. For example, such dies may include standard dies with a substrate, transistors on top of the substrate, and interconnects on one side of the transistors. As another example, such dies may include dies with interconnects on both sides of the transistors (e.g., with backside power delivery network architectures).
In various examples, a die may include logic that implements one or more components (or a portion of a component) of a computing system such as a processing element, a memory element, or general logic (further examples of which will be provided below in connection with
The granularity of the individual dies may also allow the dies to be manufactured using separate processes. For example, one or more dies may be on a first process such as the latest logic node to optimize performance, one or more other dies may be on an older node to optimize cost, one or more other dies may be on a node designed for analog components (e.g., for I/O or RF applications), or one or more other dies may be on a memory specific process (e.g., DRAM, RRAM, FE-RAM, etc.).
Any two dies providing a particular component (or set of components) or portion thereof may be homogeneous or heterogenous (e.g., one die may include a core that is optimized for speed, while another die may include a core that is optimized for power efficiency).
Use of selective transfer may allow for various unique characteristics in the dies that can be used in the system 900. For example, in various embodiments, one or more of the dies may be very thin (e.g., less than 5 micrometers (μm) in width) or have a very small area (e.g., <100×100 μm). In some examples, one or more of the dies may have a high aspect ratio. In some examples, one or more of the dies may be non-rectilinear polygons or could have a non-convex shape or one of more holes inside the perimeter of the die.
In some examples, the dies that include circuits that are sensitive to thermal and/or power conditions (e.g., high frequency logic or power conversion circuits) are implemented as a single layer in the architecture (e.g., they don't have other dies stacked on top of them). This enables those dies to more easily receive power from the package and conduct heat. The less sensitive circuits (e.g., memory, since it runs at relatively low power and has a relatively uniform arrangement so it's easier to stack than CPU cores) may be stacked in two or more layers.
In various embodiments, the stacking of dies may also be customized based on desired characteristics. For example, if high density memory is desired, then several memory dies may be stacked together, whereas if high speed memory is desired, then stacking may be limited.
The stacking characteristics may also be based on the power delivery plan. For example, stacking of multiple dies (e.g., memory dies) may be significantly easier if they all operate at the same voltage (e.g., as SRAM and DRAM stacks typically do).
Assembly of a subsystem 1002 may allow the subsystem to be tested before it is assembled into a larger system. After the testing, the subsystem 1002 may be assembled into the overall system 1000 using any suitable assembly techniques including selective transfer. Thus, the subsystem 1002 may be similar to a die created using a monolithic approach. Any suitable components (e.g., dies including individual cores and dies or die stacks including memories or other processing element, memory element, or general logic) may be included in a subsystem 1002. The testing may include, e.g., checking to see if each component is functional, recording indications of performance, making optimizations to components based on the testing, or other suitable operations.
In the embodiment depicted, the different subsystems 1002A and 1002B are connected together with a TSV interposer of a base die 1001. In other embodiments, subsystems could be connected together with one or more interconnect bridges or other suitable circuitry.
In this embodiment, there are multiple layers 1102 (e.g., 1102A and 1102B) that each may include dies and/or die stacks. For example, layer 1102A includes die 1104, two-die stack 1106, die 1108, and two-die stack 1110; while layer 1102B includes two die stack 1111 and two die stack 1112. Bridges 1114 that interconnect dies from the first layer and/or second layer may be placed at the intersection of the layers. This may provide an advantage of avoiding added signal TSVs in the die stacks.
This technique may be particularly useful for memories. This technique may also be used for processing elements and other logic circuits, especially if the top and bottom logic are not active simultaneously to avoid potential thermal issues.
In the embodiment depicted, dies 1202 include processing elements 1204, memory elements 1206, and general logic 1207, which may be arranged in any suitable manner. In some embodiments, one or more of the shown locations for dies in the tiled architecture may be depopulated, a single die or die stack could occupy two spots, the dies may have different footprint sizes, or other suitable modifications may be made. For example, where connectivity to components (e.g., DDR) outside of a CPU are desired, one or more of the locations may be used for a larger device (e.g., a memory controller).
In various examples, a die comprising a processing element 1204 may include an instance (or portion thereof) of any of the following: a processor core, an XPU, a memory controller, an FPGA, a graphics processing unit, a memory controller, an on package or on-board IO controller (e.g., for PCIE, UCIE, CXL, AIB, etc.), a custom accelerator (e.g., for artificial intelligence (AI)/machine learning (ML), security, compression, etc.), a tensor/vector/matrix processing unit, a digital signal processor (DSP) (e.g., for radio frequency (RF) baseband), a network controller, a memory with integrated compute logic (compute in memory), or other suitable circuitry to perform or support data processing. In some examples, a die including a processing element 1204 may include multiple instances of any of the above examples. In yet other examples, a die including a processing element 1204 may include one or more instances of two or more of the above examples.
In various examples, a die including a memory element 1206 may include one or more instances (or portions thereof) of one or more of an L1 cache (e.g. SRAM), an L2 cache (e.g., SRAM), an L3 cache (e.g., SRAM), an L4 cache (e.g., DRAM), or other suitable memory.
In various examples, a die including general logic 1207 may include one or more of (or portions of) a voltage regulator, a high speed communication circuit, non-CMOS logic, an FPGA, or other suitable logic.
The connectivity architecture 1200 may be based on on-die interconnect 1208 and routers 1210 as well as die-to-die interconnect bridge dies 1212 (which may correspond, e.g., to bridges 906 or 1114). In other embodiments, the die-to-die interconnect may be provided in any other suitable manner (e.g., through an interposer, a base die, etc.).
The on-die routers may couple the on-die interconnect 1208 to respective bridge dies 1212. The bridge dies 1212 may be passive (e.g., for lower cost) or active (e.g., to provide improved capabilities such as redundancy, repair, or higher bandwidth). A bridge die 1212 may have any suitable shape. For example, the footprint of the bridge die 1212 may be generally rectilinear (e.g., a square) or may have an “L” shape with two legs (e.g., one extending from the footprint of a first die to a footprint of a second die and one extending from the footprint of the first die to a footprint of a third die). In various embodiments, the mesa structure to which a bridge die 1212 is bonded may generally have the same shape as the footprint of the bridge die 1212.
In other embodiments, other suitable connection architectures may be used. For example, other mesh architectures, a ring architecture, or other suitable connection architecture may be used.
Although various embodiments herein focus on disaggregated CPU architectures, the teachings herein may be applied to manufacture any suitable disaggregated processor architecture. For example, the techniques may be used to manufacture an FPGA SoC comprising discrete dies comprising or more FPGA fabric (e.g., including configurable logic blocks and/or programmable interconnects), processor cores, memory, I/O controllers, network controllers, etc.
The flowchart begins at block 1302, where a stepped hybrid bonding surface comprising a first level and a second level is formed. For example, the stepped hybrid bonding surface may have more than one height. For example, one level of the stepped hybrid bonding surface may be formed by a plurality of bonding features (e.g., mesa structures) comprising hybrid bonding pads within a dielectric material.
At block 1304, a first plurality of dies is transferred from a donor substrate to the first level of the stepped hybrid bonding surface. For example, a selective transfer process as described herein may be used to transfer dies each comprising an instance of a processor component to the first level of the stepped hybrid bonding surface.
At block 1306, a second plurality of dies is transferred to the second level of the stepped hybrid bonding surface. For example, an intermediate carrier wafer may be used to transfer the second plurality of dies.
At block 1308, additional processing is performed. For example, a dielectric material may fill in gaps between the dies, a carrier support structure may be added, bonding pads may be formed, or other suitable processes may be performed to complete the processor.
At this point, the flowchart may be complete. In some embodiments, however, the flowchart may restart and/or certain blocks may be repeated. In various embodiments, some of the blocks may be skipped, e.g., blocks 1302 and 1304 may be skipped if an intermediate carrier approach is used. It will be appreciated in light of the present disclosure that the illustrated process flow is only one example methodology for forming a disaggregated processor architecture or other electronic system. Moreover, the steps of the illustrated process flow may be performed using any suitable semiconductor fabrication techniques such as those described herein or other suitable techniques.
The integrated circuit device 1500 may include one or more device layers 1504 disposed on the die substrate 1502. The device layer 1504 may include features of one or more transistors 1540 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1502. The transistors 1540 may include, for example, one or more source and/or drain (S/D) regions 1520, a gate 1522 to control current flow between the S/D regions 1520, and one or more S/D contacts 1524 to route electrical signals to/from the S/D regions 1520. The transistors 1540 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1540 are not limited to the type and configuration depicted in
Returning to
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1540 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of or comprise a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1540 along the source-channel-drain direction, the gate electrode may consist of or comprise a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1502 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1502 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, the gate electrode may consist of or comprise a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1520 may be formed within the die substrate 1502 adjacent to the gate 1522 of individual transistors 1540. The S/D regions 1520 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1502 to form the S/D regions 1520. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1502 may follow the ion-implantation process. In the latter process, the die substrate 1502 may first be etched to form recesses at the locations of the S/D regions 1520. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1520. In some implementations, the S/D regions 1520 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1520 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1520.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1540) of the device layer 1504 through one or more interconnect layers disposed on the device layer 1504 (illustrated in
The interconnect structures 1528 (e.g., lines) may be arranged within the interconnect layers 1506-1510 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1528 depicted in
In some embodiments, the interconnect structures 1528 may include lines 1528a and/or vias 1528b filled with an electrically conductive material such as a metal. The lines 1528a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1502 upon which the device layer 1504 is formed. For example, the lines 1528a may route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias 1528b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate 1502 upon which the device layer 1504 is formed. In some embodiments, the vias 1528b may electrically couple lines 1528a of different interconnect layers 1506-1510 together.
The interconnect layers 1506-1510 may include a dielectric material 1526 disposed between the interconnect structures 1528, as shown in
A first interconnect layer 1506 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1504. In some embodiments, the first interconnect layer 1506 may include lines 1528a and/or vias 1528b, as shown. The lines 1528a of the first interconnect layer 1506 may be coupled with contacts (e.g., the S/D contacts 1524) of the device layer 1504. The vias 1528b of the first interconnect layer 1506 may be coupled with the lines 1528a of a second interconnect layer 1508.
The second interconnect layer 1508 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1506. In some embodiments, the second interconnect layer 1508 may include via 1528b to couple the lines 1528 of the second interconnect layer 1508 with the lines 1528a of a third interconnect layer 1510. Although the lines 1528a and the vias 1528b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 1528a and the vias 1528b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 1510 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1508 according to similar techniques and configurations described in connection with the second interconnect layer 1508 or the first interconnect layer 1506. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1519 in the integrated circuit device 1500 (i.e., farther away from the device layer 1504) may be thicker that the interconnect layers that are lower in the metallization stack 1519, with lines 1528a and vias 1528b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit device 1500 may include a solder resist material 1534 (e.g., polyimide or similar material) and one or more conductive contacts 1536 formed on the interconnect layers 1506-1510. In
In some embodiments in which the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1504. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1506-1510, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536.
In other embodiments in which the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include one or more through silicon vias (TSVs) through the die substrate 1502; these TSVs may make contact with the device layer(s) 1504, and may provide conductive pathways between the device layer(s) 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536 to the transistors 1540 and any other components integrated into the integrated circuit device (e.g., die) 1500, and the metallization stack 1519 can be used to route I/O signals from the conductive contacts 1536 to transistors 1540 and any other components integrated into the integrated circuit device (e.g., die) 1500.
Multiple integrated circuit devices 1500 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate. The integrated circuit device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an integrated circuit component 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single integrated circuit component 1720 is shown in
The integrated circuit component 1720 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (e.g., the die 1402 of
In embodiments where the integrated circuit component 1720 comprises multiple integrated circuit dies, the dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).
In addition to comprising one or more processor units, the integrated circuit component 1720 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.
Generally, the interposer 1704 may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer 1704 may couple the integrated circuit component 1720 to a set of ball grid array (BGA) conductive contacts of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in
In some embodiments, the interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to through hole vias 1710-1 (that extend from a first face 1750 of the interposer 1704 to a second face 1754 of the interposer 1704), blind vias 1710-2 (that extend from the first or second faces 1750 or 1754 of the interposer 1704 to an internal metal layer), and buried vias 1710-3 (that connect internal metal layers).
In some embodiments, the interposer 1704 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer 1704 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer 1704 to an opposing second face of the interposer 1704.
The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The integrated circuit device assembly 1700 may include an integrated circuit component 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the integrated circuit component 1724 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1720.
The integrated circuit device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include one or more processor units 1802 (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that is located on the same integrated circuit die as the processor unit 1802. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 1800 can comprise one or more processor units 1802 that are heterogeneous or asymmetric to another processor unit 1802 in the electrical device 1800. There can be a variety of differences between the processing units 1802 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 1802 in the electrical device 1800.
In some embodiments, the electrical device 1800 may include a communication component 1812 (e.g., one or more communication components). For example, the communication component 1812 can manage wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as amplitude modulation (AM) or frequency modulation (FM) radio transmissions).
In some embodiments, the communication component 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 1812 may include multiple communication components. For instance, a first communication component 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1812 may be dedicated to wireless communications, and a second communication component 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 1800 may include a Global Navigation Satellite System (GNSS) device 1818 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1818 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 1800 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 1800 may be any other electronic device that processes data. In some embodiments, the electrical device 1800 may comprise multiple discrete physical components. Given the range of devices that the electrical device 1800 can be manifested as in various embodiments, in some embodiments, the electrical device 1800 can be referred to as a computing device or a computing system.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
It will also be understood that, although the terms “first,” “second,” and so forth may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the present example embodiments. The first contact and the second contact are both contacts, but they are not the same contact.
As used in the description of the example embodiments and the appended examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. For example, the phrase “A and/or B” means (A), (B), or (A and B), while the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of”′ can mean any combination of the listed terms.
It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The description may use the phrases “in an embodiment,” “according to some embodiments,” “in accordance with embodiments,” or “in embodiments,” which may each refer to one or more of the same or different embodiments.
As used herein, the term “module” refers to being part of, or including an ASIC, an electronic circuit, a system on a chip, a processor (shared, dedicated, or group), a solid state device, a memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
As used herein, “electrically conductive” in some examples may refer to a property of a material having an electrical conductivity greater than or equal to 107 Siemens per meter (S/m) at 20 degrees Celsius. Examples of such materials include Cu, Ag, Al, Au, W, Zn and Ni.
The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the elements that are connected, without any intermediary devices. The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the elements that are connected or an indirect connection, through one or more passive or active intermediary devices.
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or layer over or under another may be directly in contact or may have one or more intervening materials or layers. Moreover, one material between two materials or layers may be directly in contact with the two materials/layers or may have one or more intervening materials/layers. In contrast, a first material or layer “on” a second material or layer means that at least a part of the first material or layer is in direct physical contact with at least a part of that second material/layer. Similar distinctions are to be made in the context of component assemblies.
As used herein, “A is adjacent to B” means that at least part of A is in direct physical contact with at least a part of B.
As used herein, “A is proximate to B” may mean that A is adjacent to B or A is otherwise near to B.
Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition (e.g., by volume) is the first constituent (e.g., >50 at. %). The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent (e.g., by volume) than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent. The term “substantially” in this context means there is only incidental variation. For example, composition that is substantially a first constituent means the composition may further include<1% of any other constituent. A composition that is substantially first and second constituents means the composition may further include<1% of any constituent substituted for either the first or second constituent.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified).
Unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” or “approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value.
In the corresponding drawings of the embodiments, signals, currents, electrical biases, or magnetic or electrical polarities may be represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, polarity, current, voltage, etc., as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
Although the figures may illustrate embodiments where structures are substantially aligned to Cartesian axes (e.g., device structures having substantially vertical sidewalls), positive and negative (re-entrant) sloped feature sidewalls often occur in practice. For example, manufacturing non-idealities may cause one or more structural features to have sloped sidewalls. Thus, attributes illustrated are idealized merely for the sake of clearly describing salient features. It is to be understood that schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.
Illustrative examples of the technologies described throughout this disclosure are provided below. Embodiments of these technologies may include any one or more, and any combination of, the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the following examples.
The foregoing description, for the purpose of explanation, has been described with reference to specific example embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The example embodiments were chosen and described in order to best explain the principles involved and their practical applications, to thereby enable others skilled in the art to best utilize the various example embodiments with various modifications as are suited to the particular use contemplated.
