with a staggered arrangement

Industry

CPC
H01L2224/14163

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Parent Industries

HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/14163with a staggered arrangement

Industries

Patents Grantslast 30 patents

Information Patent Grant
Optical electronic-chip identification writer using dummy C4 bumps
- Patent number 10,242,951
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Daniel Piper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic package for wafer-level chip scale packaging with f...
- Patent number 10,181,457
- Issue date Jan 15, 2019
- Invensas Corporation
- Ashok S. Prabhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming IPD in fan-out wafer lev...
- Patent number 9,343,396
- Issue date May 17, 2016
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder bump arrangements for large area analog circuitry
- Patent number 9,343,418
- Issue date May 17, 2016
- Xilinx, Inc.
- Donnacha Lowney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming IPD in fan-out level chi...
- Patent number 8,241,952
- Issue date Aug 14, 2012
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHIP AND ITS MANUFACTURING, MOUNTING METHOD AND PRINTED CIRCUIT BOARD
- Publication number 20240153858
- Publication date May 9, 2024
- Lingxin Electronic Technology (Wuxi) Co., Ltd.
- Zhengyu YE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP PACKAGE AND SUBSTRATE THEREOF
- Publication number 20240014118
- Publication date Jan 11, 2024
- Chipbond Technology Corporation
- Chun-Te Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL PILLAR CONNECTION TOPOLOGIES FOR HETEROGENEOUS PACKAGING
- Publication number 20230075505
- Publication date Mar 9, 2023
- Wolfspeed, Inc.
- Fabian Radulescu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASSORTMENT OF SUBSTRATES FOR SEMICONDUCTOR CIRCUITS, CORRESPONDING...
- Publication number 20210167029
- Publication date Jun 3, 2021
- STMicroelectronics S.r.l
- Cristina SOMMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGE FOR WAFER-LEVEL CHIP SCALE PACKAGING WITH F...
- Publication number 20190096861
- Publication date Mar 28, 2019
- Invensas Corporation
- Rajesh Katkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Microelectronic Package for Wafer-Level Chip Scale Packaging with F...
- Publication number 20170117260
- Publication date Apr 27, 2017
- Invensas Corporation
- Ashok S. Prabhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Insulated Bump Bonding
- Publication number 20140264796
- Publication date Sep 18, 2014
- MICROCHIP TECHNOLOGY INCORPORATED
- Gregory Dix
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INTERCONNECT
- Publication number 20130105993
- Publication date May 2, 2013
- GENERAL ELECTRIC COMPANY
- Raj BAHADUR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Lev...
- Publication number 20120267800
- Publication date Oct 25, 2012
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming IPD in Fan-Out Level Chi...
- Publication number 20110204509
- Publication date Aug 25, 2011
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS

with a staggered arrangement

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Optical electronic-chip identification writer using dummy C4 bumps

Microelectronic package for wafer-level chip scale packaging with f...

Semiconductor device and method of forming IPD in fan-out wafer lev...

Solder bump arrangements for large area analog circuitry

Semiconductor device and method of forming IPD in fan-out level chi...

Patents Applicationslast 30 patents

CHIP AND ITS MANUFACTURING, MOUNTING METHOD AND PRINTED CIRCUIT BOARD

FLIP CHIP PACKAGE AND SUBSTRATE THEREOF

METAL PILLAR CONNECTION TOPOLOGIES FOR HETEROGENEOUS PACKAGING

ASSORTMENT OF SUBSTRATES FOR SEMICONDUCTOR CIRCUITS, CORRESPONDING...

MICROELECTRONIC PACKAGE FOR WAFER-LEVEL CHIP SCALE PACKAGING WITH F...

Microelectronic Package for Wafer-Level Chip Scale Packaging with F...

Insulated Bump Bonding

SEMICONDUCTOR DEVICE INTERCONNECT

Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Lev...

Semiconductor Device and Method of Forming IPD in Fan-Out Level Chi...