with concurrent directory accessing

Industry

CPC
G06F12/0828

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0828with concurrent directory accessing

Industries

Patents Grantslast 30 patents

Information Patent Grant
System and method for event messages in a cache coherent interconnect
- Patent number 12,164,428
- Issue date Dec 10, 2024
- ARTERIS, INC.
- Michael Frank
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,159,030
- Issue date Dec 3, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for coherent system
- Patent number 12,141,435
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive cache indexing for a storage device
- Patent number 12,105,629
- Issue date Oct 1, 2024
- Samsung Electronics Co., Ltd.
- Zongwang Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ferroelectric memory chiplet in a multi-dimensional packaging with...
- Patent number 12,086,410
- Issue date Sep 10, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive credit-based replenishment threshold used for transaction...
- Patent number 12,079,471
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Daniel Brad Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ferroelectric memory chiplet in a multi-dimensional packaging
- Patent number 12,079,475
- Issue date Sep 3, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to enter and exit a cache coherent interconnect
- Patent number 12,072,805
- Issue date Aug 27, 2024
- ARTERIS, INC.
- Mohammed Khaleeluddin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag update bus for updated coherence state
- Patent number 12,056,051
- Issue date Aug 6, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-random way selection
- Patent number 12,045,644
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level cache security
- Patent number 12,038,840
- Issue date Jul 16, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network entities and methods performed therein for handling cache c...
- Patent number 12,032,481
- Issue date Jul 9, 2024
- Telefonaktiebolaget LM Ericsson (publ)
- Chakri Padala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline arbitration
- Patent number 12,014,206
- Issue date Jun 18, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory device and method for implementing cache scheduling us...
- Patent number 11,994,991
- Issue date May 28, 2024
- MetisX CO., Ltd.
- Do Hun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, device and method for accessing device-attached memory
- Patent number 11,983,115
- Issue date May 14, 2024
- Samsung Electronics Co., Ltd.
- Jeongho Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherency protocol for encoding a cache line with a domain sh...
- Patent number 11,954,034
- Issue date Apr 9, 2024
- WOVEN BY TOYOTA, INC.
- Jean-Francois Bastien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive hardware transactional memory based concurrency control
- Patent number 11,947,994
- Issue date Apr 2, 2024
- SAP SE
- Thomas Legler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using cache coherent FPGAS to track dirty cache lines
- Patent number 11,947,458
- Issue date Apr 2, 2024
- VMware, Inc.
- Irina Calciu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multipath memory with static or dynamic mapping to coherent or MMIO...
- Patent number 11,947,459
- Issue date Apr 2, 2024
- Xilinx, Inc.
- Jaideep Dastidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controller with caching and non-caching modes
- Patent number 11,907,753
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor bridge with cache allocate awareness
- Patent number 11,907,528
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing cache transfer overhead in a system
- Patent number 11,892,949
- Issue date Feb 6, 2024
- International Business Machines Corporation
- Christian Zoellin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System coherency protocol
- Patent number 11,868,259
- Issue date Jan 9, 2024
- International Business Machines Corporation
- Vesselina Papazova
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delayed snoop for improved multi-process false sharing parallel thr...
- Patent number 11,822,786
- Issue date Nov 21, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 11,816,032
- Issue date Nov 14, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining real-time cache coherency during distributed computatio...
- Patent number 11,809,323
- Issue date Nov 7, 2023
- Seagate Technology LLC
- Marc Timothy Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level cache coherency protocol for cache line evictions
- Patent number 11,803,470
- Issue date Oct 31, 2023
- Advanced Micro Devices, Inc.
- Amit Apte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 11,789,868
- Issue date Oct 17, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SNOOP FILTER WITH DISAGGREGATED VECTOR TABLE
- Publication number 20240419594
- Publication date Dec 19, 2024
- Microsoft Technology Licensing, LLC
- Jason Lawrence PANAVICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COHERENT HIERARCHICAL CACHE LINE TRACKING
- Publication number 20240419595
- Publication date Dec 19, 2024
- Akeana, Inc.
- Sanjay Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACK...
- Publication number 20240402908
- Publication date Dec 5, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE USING DYNAMIC COARSE-GRAINED TRACKING
- Publication number 20240403219
- Publication date Dec 5, 2024
- Microsoft Technology Licensing, LLC
- Dimitrios KASERIDIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computing Device, Data Processing Method and System, and Related De...
- Publication number 20240362165
- Publication date Oct 31, 2024
- Huawei Cloud Computing Technologies Co., Ltd.
- Xiao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORY DEVICE AND METHOD FOR IMPLEMENTING CACHE SCHEDULING US...
- Publication number 20240354252
- Publication date Oct 24, 2024
- MetisX CO., Ltd.
- Do Hun KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL CACHE SECURITY
- Publication number 20240320154
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FERROELECTRIC MEMORY CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH...
- Publication number 20240311006
- Publication date Sep 19, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CXL MEMORY MODULE, MEMORY DATA SWAP METHOD AND COMPUTER SYSTEM
- Publication number 20240311305
- Publication date Sep 19, 2024
- Beijing Superstring Academy of Memory Technology
- Jin DAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARBITRATION
- Publication number 20240281278
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MANAGEMENT USING SHARED CACHE LINE STORAGE
- Publication number 20240241830
- Publication date Jul 18, 2024
- Akeana, Inc.
- Sanjay Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR CCIX INTERFACE BASED ON USE OF QoS FIELD
- Publication number 20240241829
- Publication date Jul 18, 2024
- ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Jin-Suk MA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
- Publication number 20240184446
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Coherency State Request Vector Encoding and Use Thereof
- Publication number 20240184698
- Publication date Jun 6, 2024
- Wesley Waylon Terpstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST MANAGED MEMORY SHARED BY MULTIPLE HOST SYSTEMS IN A HIGH AVAIL...
- Publication number 20240176740
- Publication date May 30, 2024
- Intel Corporation
- Krishna Kumar SIMMADHARI RAMADASS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND NETWORK-ON-CHIP COHERENCY MANAGEMENT
- Publication number 20240168882
- Publication date May 23, 2024
- Akeana, Inc.
- Sanjay Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER WITH CACHING AND NON-CACHING MODES
- Publication number 20240152385
- Publication date May 9, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COHERENCE PROTOCOL FOR COMMUNICATING DATA ASSOCIATED WITH A...
- Publication number 20240143506
- Publication date May 2, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SIZE CHANGE
- Publication number 20240095169
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THR...
- Publication number 20240086065
- Publication date Mar 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHASSIS SERVICING AND MIGRATION IN A SCALE-UP NUMA SYSTEM
- Publication number 20240069742
- Publication date Feb 29, 2024
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Thomas Edward McGee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20240045803
- Publication date Feb 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE CACHE INDEXING FOR A STORAGE DEVICE
- Publication number 20240028512
- Publication date Jan 25, 2024
- Samsung Electronics Co., Ltd.
- Zongwang Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE TO OFFLOAD PROCESSING FROM AN ADVANCED DRIVER ASSISTA...
- Publication number 20240012757
- Publication date Jan 11, 2024
- Micron Technology, Inc.
- Abhilash Nag
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MERGING DATA FOR WRITE ALLOCATE
- Publication number 20240004694
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER
- Publication number 20240004793
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20230418469
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20230409376
- Publication date Dec 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING

with concurrent directory accessing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

System and method for event messages in a cache coherent interconnect

Multicore shared cache operation engine

Global coherence operations

Configurable cache for coherent system

Cache coherence shared state suppression

Adaptive cache indexing for a storage device

Ferroelectric memory chiplet in a multi-dimensional packaging with...

Adaptive credit-based replenishment threshold used for transaction...

Ferroelectric memory chiplet in a multi-dimensional packaging

System and method to enter and exit a cache coherent interconnect

Tag update bus for updated coherence state

Pseudo-random way selection

Multi-level cache security

Network entities and methods performed therein for handling cache c...

Pipeline arbitration

Cache memory device and method for implementing cache scheduling us...

System, device and method for accessing device-attached memory

Cache coherency protocol for encoding a cache line with a domain sh...

Adaptive hardware transactional memory based concurrency control

Using cache coherent FPGAS to track dirty cache lines

Multipath memory with static or dynamic mapping to coherent or MMIO...

Controller with caching and non-caching modes

Multi-processor bridge with cache allocate awareness

Reducing cache transfer overhead in a system

System coherency protocol

Delayed snoop for improved multi-process false sharing parallel thr...

Cache size change

Maintaining real-time cache coherency during distributed computatio...

Multi-level cache coherency protocol for cache line evictions

Hardware coherence signaling protocol

Patents Applicationslast 30 patents

SNOOP FILTER WITH DISAGGREGATED VECTOR TABLE

COHERENT HIERARCHICAL CACHE LINE TRACKING

METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACK...

CACHE COHERENCE USING DYNAMIC COARSE-GRAINED TRACKING

Computing Device, Data Processing Method and System, and Related De...

CACHE MEMORY DEVICE AND METHOD FOR IMPLEMENTING CACHE SCHEDULING US...

PSEUDO-RANDOM WAY SELECTION

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

MULTI-LEVEL CACHE SECURITY

FERROELECTRIC MEMORY CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH...

CXL MEMORY MODULE, MEMORY DATA SWAP METHOD AND COMPUTER SYSTEM

PIPELINE ARBITRATION

CACHE MANAGEMENT USING SHARED CACHE LINE STORAGE

APPARATUS AND METHOD FOR CCIX INTERFACE BASED ON USE OF QoS FIELD

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS

Cache Coherency State Request Vector Encoding and Use Thereof

HOST MANAGED MEMORY SHARED BY MULTIPLE HOST SYSTEMS IN A HIGH AVAIL...

PROCESSOR AND NETWORK-ON-CHIP COHERENCY MANAGEMENT

CONTROLLER WITH CACHING AND NON-CACHING MODES

MEMORY COHERENCE PROTOCOL FOR COMMUNICATING DATA ASSOCIATED WITH A...

CACHE SIZE CHANGE

DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THR...

CHASSIS SERVICING AND MIGRATION IN A SCALE-UP NUMA SYSTEM

HARDWARE COHERENCE SIGNALING PROTOCOL

ADAPTIVE CACHE INDEXING FOR A STORAGE DEVICE

MEMORY DEVICE TO OFFLOAD PROCESSING FROM AN ADVANCED DRIVER ASSISTA...

MERGING DATA FOR WRITE ALLOCATE

SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER

MULTICORE SHARED CACHE OPERATION ENGINE

GLOBAL COHERENCE OPERATIONS