with multilevel cache hierarchies

Industry

CPC
G06F12/0811

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0811with multilevel cache hierarchies

Industries

Patents Grantslast 30 patents

Information Patent Grant
Remote acceleration for data dependent address calculation
- Patent number 12,367,145
- Issue date Jul 22, 2025
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with early and late address and loop count registe...
- Patent number 12,367,150
- Issue date Jul 22, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redirection in a processor cache
- Patent number 12,360,898
- Issue date Jul 15, 2025
- Nokia Solutions and Networks Oy
- Pranjal Kumar Dutta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer-implemented method for managing cache utilization
- Patent number 12,360,905
- Issue date Jul 15, 2025
- Robert Bosch GmbH
- Arne Hamann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,360,843
- Issue date Jul 15, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Credit aware central arbitration for multi-endpoint, multi-core system
- Patent number 12,360,844
- Issue date Jul 15, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scoreboard for register data cache
- Patent number 12,360,899
- Issue date Jul 15, 2025
- Apple Inc.
- Winnie W. Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region pattern-matching hardware prefetcher
- Patent number 12,360,907
- Issue date Jul 15, 2025
- Advanced Micro Devices, Inc.
- Gabriel H. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor, system, and method for dynamic cache allocation
- Patent number 12,360,900
- Issue date Jul 15, 2025
- Samsung Electronics Co., Ltd.
- Jin Jung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preemption techniques for memory-backed registers
- Patent number 12,353,330
- Issue date Jul 8, 2025
- Apple Inc.
- Benjiman L. Goodman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and methods for direct data reads from memory
- Patent number 12,353,329
- Issue date Jul 8, 2025
- Intel Corporation
- Robert Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache resource prioritization for heterogeneous multi-processing (H...
- Patent number 12,346,259
- Issue date Jul 1, 2025
- QUALCOMM Incorporated
- Aiqun Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pointer based data encryption
- Patent number 12,346,463
- Issue date Jul 1, 2025
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling operating voltage of a processor
- Patent number 12,339,723
- Issue date Jun 24, 2025
- Daedalus Prime LLC
- Ryan D. Wells
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero value memory access optimization
- Patent number 12,339,776
- Issue date Jun 24, 2025
- Advanced Micro Devices, Inc.
- Varun Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system performing cache bypassing operation and cache manage...
- Patent number 12,332,787
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Shinhaeng Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple level caching of user level thread stacks for user level t...
- Patent number 12,332,789
- Issue date Jun 17, 2025
- International Business Machines Corporation
- Oluwatobi Ajila
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System setting including operating frequency of random access memor...
- Patent number 12,332,788
- Issue date Jun 17, 2025
- SK hynix Inc.
- Yong Wan Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level cache security
- Patent number 12,332,790
- Issue date Jun 17, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative request indicator in request message
- Patent number 12,332,799
- Issue date Jun 17, 2025
- SiFive, Inc.
- Wesley Waylon Terpstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stage cache tag with first stage tag size reduction
- Patent number 12,332,802
- Issue date Jun 17, 2025
- Intel Corporation
- Kermin ChoFleming
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor unit resource exhaustion detection and remediation
- Patent number 12,326,810
- Issue date Jun 10, 2025
- Intel Corporation
- John J. Browne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch management in a hierarchical cache system
- Patent number 12,321,277
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implicit fence for write messages
- Patent number 12,321,310
- Issue date Jun 3, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence for memory controller
- Patent number 12,321,270
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed system level cache
- Patent number 12,321,271
- Issue date Jun 3, 2025
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slot/sub-slot prefetch architecture for multiple memory requestors
- Patent number 12,321,282
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascading execution of atomic operations
- Patent number 12,321,273
- Issue date Jun 3, 2025
- Advanced Micro Devices, Inc.
- Jimshed Mirza
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUE FOR STORING DATA IN A CACHE
- Publication number 20250238374
- Publication date Jul 24, 2025
- ARM Limited
- Håkan Lars-Göran PERSSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS RELATING TO CONFIDENTIAL COMPUTING KEY MIXING H...
- Publication number 20250240156
- Publication date Jul 24, 2025
- ADVANCED MICRO DEVICES, INC.
- Amit P. Apte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DEDUPLICATION IN A METADATA DELTA LOG ARCHITECTURE
- Publication number 20250238372
- Publication date Jul 24, 2025
- DELL PRODUCTS L.P.
- Vladimir Shveidel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORIES IN VERTICALLY INTEGRATED MEMORY SYSTEMS AND ASSOCIAT...
- Publication number 20250231877
- Publication date Jul 17, 2025
- Micron Technology, Inc.
- Raghukiran Sreeramaneni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SIZE CHANGE
- Publication number 20250231878
- Publication date Jul 17, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL NETWORK PRE-ARBITRATION
- Publication number 20250231684
- Publication date Jul 17, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIORITY-BASED CACHE EVICTION POLICY GOVERNED BY LATENCY CRITICAL C...
- Publication number 20250225081
- Publication date Jul 10, 2025
- QUALCOMM Incorporated
- Kalangi Fredy SUNDAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Configuration of Address Translation Cache
- Publication number 20250217302
- Publication date Jul 3, 2025
- MELLANOX TECHNOLOGIES, LTD.
- Gal Shalom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO USE DATA OBJECT E...
- Publication number 20250217291
- Publication date Jul 3, 2025
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Zero Value Memory Access Optimization
- Publication number 20250209000
- Publication date Jun 26, 2025
- ADVANCED MICRO DEVICES, INC.
- Varun Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDIRECTION IN A PROCESSOR CACHE
- Publication number 20250209001
- Publication date Jun 26, 2025
- Nokia Solutions and Networks Oy
- Pranjal Kumar Dutta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multilevel Memory System with Copied Error Detection Bits
- Publication number 20250199907
- Publication date Jun 19, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Ruchi Shankar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF HANDLING MODIFICATION TRACKING DATA IN TIMESTE...
- Publication number 20250190377
- Publication date Jun 12, 2025
- Samsung Electronics Co., Ltd.
- Thomas Labonte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ACCOUNTING OF CACHE FOR GPU SCRATCH MEMORY USAGE
- Publication number 20250190347
- Publication date Jun 12, 2025
- ADVANCED MICRO DEVICES, INC.
- Nicolai Haehnle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Injection and Prefetch Mechanisms for Improving Multi-Die Pro...
- Publication number 20250190367
- Publication date Jun 12, 2025
- ADVANCED MICRO DEVICES, INC.
- Shaju Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND ELECTRONIC DEVICE INCLUDING THE SAME
- Publication number 20250190348
- Publication date Jun 12, 2025
- Samsung Electronics Co., Ltd.
- Kil Ho LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOK-UP TABLE INITIALIZE
- Publication number 20250190218
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WARP ACCESS PATTERN-AWARE CACHES
- Publication number 20250191112
- Publication date Jun 12, 2025
- QUALCOMM Incorporated
- Darshan Kumar NANDANWAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR HANDLING PREFETCHING
- Publication number 20250181508
- Publication date Jun 5, 2025
- ARM Limited
- Natalya BONDARENKO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
- Publication number 20250181238
- Publication date Jun 5, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION
- Publication number 20250173266
- Publication date May 29, 2025
- Dynavisor, Inc.
- Sreekumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20250173308
- Publication date May 29, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT OF PROGRAMMING MODE TRANSITIONS TO ACCOMMODATE A CONSTAN...
- Publication number 20250165403
- Publication date May 22, 2025
- Micron Technology, Inc.
- Sanjay Subbarao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY MEMORY ACCESS FOR CPUS IN AUTONOMOUS VEHICLES
- Publication number 20250156327
- Publication date May 15, 2025
- Apollo Autonomous Driving USA LLC
- ZHENWEI YU
- B60 - VEHICLES IN GENERAL
Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING A SYSTEM LEVEL CACHE
- Publication number 20250156326
- Publication date May 15, 2025
- NVIDIA Corporation
- Ashutosh PANDEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TIERED CACHE SYSTEM
- Publication number 20250147887
- Publication date May 8, 2025
- PAYPAL, INC.
- Sharmili Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20250147888
- Publication date May 8, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING

with multilevel cache hierarchies

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Remote acceleration for data dependent address calculation

Streaming engine with early and late address and loop count registe...

Redirection in a processor cache

Computer-implemented method for managing cache utilization

Multicore shared cache operation engine

Credit aware central arbitration for multi-endpoint, multi-core system

Scoreboard for register data cache

Region pattern-matching hardware prefetcher

Processor, system, and method for dynamic cache allocation

Preemption techniques for memory-backed registers

System, apparatus and methods for direct data reads from memory

Cache resource prioritization for heterogeneous multi-processing (H...

Pointer based data encryption

Controlling operating voltage of a processor

Zero value memory access optimization

Memory system performing cache bypassing operation and cache manage...

Multiple level caching of user level thread stacks for user level t...

System setting including operating frequency of random access memor...

Multi-level cache security

Speculative request indicator in request message

Multi-stage cache tag with first stage tag size reduction

Processor unit resource exhaustion detection and remediation

Prefetch management in a hierarchical cache system

Methods and apparatus to facilitate atomic operations in victim cache

Implicit fence for write messages

Hardware coherence for memory controller

Distributed system level cache

Slot/sub-slot prefetch architecture for multiple memory requestors

Victim cache with write miss merging

Cascading execution of atomic operations

Patents Applicationslast 30 patents

TECHNIQUE FOR STORING DATA IN A CACHE

SYSTEMS AND METHODS RELATING TO CONFIDENTIAL COMPUTING KEY MIXING H...

EFFICIENT DEDUPLICATION IN A METADATA DELTA LOG ARCHITECTURE

CACHE MEMORIES IN VERTICALLY INTEGRATED MEMORY SYSTEMS AND ASSOCIAT...

CACHE SIZE CHANGE

VIRTUAL NETWORK PRE-ARBITRATION

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

PRIORITY-BASED CACHE EVICTION POLICY GOVERNED BY LATENCY CRITICAL C...

Adaptive Configuration of Address Translation Cache

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO USE DATA OBJECT E...

Zero Value Memory Access Optimization

REDIRECTION IN A PROCESSOR CACHE

Multilevel Memory System with Copied Error Detection Bits

SYSTEM AND METHOD OF HANDLING MODIFICATION TRACKING DATA IN TIMESTE...

DYNAMIC ACCOUNTING OF CACHE FOR GPU SCRATCH MEMORY USAGE

Cache Injection and Prefetch Mechanisms for Improving Multi-Die Pro...

PROCESSOR AND ELECTRONIC DEVICE INCLUDING THE SAME

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

LOOK-UP TABLE INITIALIZE

WARP ACCESS PATTERN-AWARE CACHES

TECHNIQUE FOR HANDLING PREFETCHING

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

MANAGEMENT OF PROGRAMMING MODE TRANSITIONS TO ACCOMMODATE A CONSTAN...

LOW LATENCY MEMORY ACCESS FOR CPUS IN AUTONOMOUS VEHICLES

DATA INITIALIZATION TECHNIQUES

MANAGING A SYSTEM LEVEL CACHE

MULTI-TIERED CACHE SYSTEM

HARDWARE COHERENCE SIGNALING PROTOCOL