Memory system component that enables clock-to-strobe skew compensation

Information

  • Patent Grant
  • 11664067
  • Patent Number
    11,664,067
  • Date Filed
    Monday, August 2, 2021
    3 years ago
  • Date Issued
    Tuesday, May 30, 2023
    a year ago
Abstract
An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.
Description
FIELD OF THE INVENTION

The disclosure herein relates generally to memory systems and methods. In particular, this disclosure relates to systems and methods for transferring information among memory components and a memory controller.


BACKGROUND

High-speed processor-based electronic systems have become all-pervasive in computing, communications, and consumer electronic applications to name a few. The pervasiveness of these systems, many of which are based on multi-gigahertz processors, has led in turn to an increased demand for high performance memory systems. As one example, FIG. 8 is a block diagram of a high performance memory system 800 under the prior art. This memory system 800 includes a memory controller 802 coupled to one or more memory component(s) 804. The memory controller 802 includes address circuitry 812 to drive address/control information outputs and write data circuitry 822 to drive write data information outputs to the memory component(s) 804.


Information is carried on signal paths between the memory controller 802 and the memory component(s) 804 by a signal, where the signal includes a symbol (such as a bit) that propagates along the signal path. The symbol is present at a particular point on the signal path for a characteristic time, called the symbol interval or symbol time. A signal path is typically composed of a conductive interconnect. A signal path may use one or two (or more) interconnects to encode the signal, along with return paths through adjacent power conductors.


The memory system 800 uses a variety of signals to couple the memory controller 802 and the memory component(s) 804. One set of signals are address/control signals A and the corresponding timing signals TA (also referred to as address/control timing signals TAX). The address/control signals A carry address and control information, and are labeled as A0, A1, and A2 to show the address/control signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. The timing signals TA carry timing information that indicates when information is valid on the address/control signals A. The timing signals are labeled as TA0, TA1, and TA2 to show the timing signals at different points along the signal path between the memory controller 802 and the memory component(s) 804.


Another set of signals that couple the memory controller 802 and the memory component(s) 804 are write data signals W and the corresponding data valid or timing signals TW (also referred to as write data valid signals or write data timing signals TW). The write data signals W carry write data information, and are labeled as W0, W1, and W2 to show the write data signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. The timing signals TW carry timing information that indicates when information is valid on the write data signals W. The timing signals are labeled as TW0, TW1, and TW2 to show the timing signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. Note that the label for address/control timing signal TA0 is shortened to T0 in the memory system 800, and likewise, the label for write data timing signal TW0 is shortened to T0 because the address circuitry 812 and the write data circuitry 822 operate within a common timing domain in the memory controller 802.


The timing signals TA and TW carry timing information in the form of events, such as a transition between two symbol values (such as a rising edge). A timing signal indicates when valid information is present on a set of related signals. Each timing event may be related to one symbol on each signal of the set, or it may be related to more than one symbol on each signal. The timing signal may only have timing events when there are valid symbols on the associated set of signals, or it may have timing events when there are no valid symbols. Consequently, each bit on the address/control signal A is associated with a timing event on the corresponding address timing signal TA (a rising edge for example). Similarly, each bit on the write data signal W is associated with a timing event on the write data timing signal TW.


The address and control information A2 is received at the memory component(s) 804 with the timing signal TA2, and is coupled to the core circuitry 814 of the memory component(s) 804. This core circuitry 814 operates in the TA2 timing domain. The TA2 timing domain is delayed from the T0 timing domain of the memory controller 802 by the propagation delay time tPD-A (the time required by the signals at A1 and TA1 to propagate to A2 and TA2, respectively).


Further, the write data information W2 is received at the write circuitry 824 of the memory component(s) 804 with the timing signal TW2. The write circuitry 824 operates in the TW2 timing domain, where the TW2 timing domain is delayed from the T0 timing domain of the memory controller 802 by the propagation delay time tPD-W (the time required by the signals at W1 and TW1 to propagate to W2 and TW2, respectively).


In writing data to the core circuitry 814 of the memory component 804, write data received at the write circuitry 824 (TW2 timing domain) must be transferred to the core circuitry 814 (TA2 timing domain). This transfer is accomplished by the interface circuitry 834, where the interface circuitry 834 compensates for timing differences between the TW2 timing domain and the TA2 timing domain (determined by taking the difference between tPD-A and tPD-W propagation delay times). The interface circuitry 834 typically compensates for timing differences between the TW2 timing domain and the TA2 timing domain of approximately +/−tDQSS (data sheet term representing system offsets and pin-to-pin offsets in a dynamic random access memory (DRAM)). Therefore, if the value of tDQSS is made large, it relaxes the signal path matching constraints imposed on tPD-A and tPD-W, but increases the burden on the interface circuitry 834 to resolve timing discrepancies between the different timing domains.


If, however the value of tDQSS is reduced in order to reduce the burden on the interface circuitry 834, it increases the signal path matching constraints imposed on tPD-A and tPD-W. Typically, the A and TA signal paths must be routed together and matched relatively tightly so the timing information on TA can be used to reliably sample the address and control information on the A signals. Similarly, the W and TW signal paths must be routed together and matched relatively tightly so the timing information on TW can be used to reliably sample the address and control information on the W signals. Thus, if the tDQSS value is made small, the tPD-A and tPD-W values of all the A/TA and W/TW signals must be simultaneously matched.



FIG. 9 is a timing diagram 900 showing signals for a write operation in the memory system 800 under the prior art. Address/control information, “addr,” is placed on the address/control signal A0 by the memory controller in response to the first rising edge of the T0 timing signal. The address/control signal A0 is then driven onto the signal path as the A1 signal along with a rising edge of the corresponding TA1 signal. The A1 and TA1 signals propagate to the core circuitry of the memory component and become the A2 and TA2 signals at time tPD-A later.


Additionally, write data is placed on the write data signal W0 by the memory controller in response to the first rising edge of the T0 timing signal. The write data signal W0 is held in the memory controller for a time tWL (where tWL is a fixed delay of two (2) cycles or periods for example) before being driven onto the W1 signal (along with a rising edge of the corresponding TW1 signal). The W1 and TW1 signals propagate to the write circuitry of the memory component and become the W2 and TW2 signals at time tPD-W later.


The write operation in the memory system 800 results in a mismatch between the timing of the TA2 and TW2 timing signals at the memory component(s). In order for the interface circuitry to compensate for this timing mismatch, the magnitude of the mismatch must not exceed the difference between the value tDQSS and the value tWL (the quantity (tDQSS−tWL)); when the mismatch exceeds the difference between the value tDQSS and the value tWL the write data cannot be reliably transferred from the write circuitry to the core circuitry within the memory component. Consequently, there is a need in high performance memory systems to increase the reliability and accuracy of data writes to memory components while relaxing the signal path matching constraints (relating to the tPD-A and tPD-W values) and reducing the burden on the interface circuitry.





BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 150 is first introduced and discussed with respect to FIG. 1).



FIG. 1 is a block diagram of a memory system that includes variable delay write circuitry for generating write data signals and data valid signals with variable delays, under an embodiment.



FIG. 2 is another block diagram of the memory system that includes variable delay write circuitry for generating variably delayed write data signals and variably delayed data valid signals, under an embodiment.



FIG. 3 is a timing diagram showing the delayed data valid along with the corresponding write data valid signals selected for output by the variable delay write circuitry, under an embodiment.



FIG. 4 is a block diagram for generating write data signals and write data valid signals with selectable delays for use in memory write operations, under an embodiment.



FIG. 5 is a timing diagram for signals of an example write operation in a memory system that generates write data signals with variable delays, under an embodiment.



FIG. 6 is a block diagram of a multiple-slice memory system that includes the variable delay write circuitry for generating write data signals and data valid signals with variable delays, under an embodiment.



FIG. 7 is a block diagram of a multiple-rank memory system that includes the variable delay write circuitry for generating write data signals and data valid signals with variable delays, under an embodiment.



FIG. 8 is a block diagram of a high performance memory system under the prior art.



FIG. 9 is a timing diagram showing signals for a write operation in the memory system under the prior art.





DETAILED DESCRIPTION

Systems and methods for generating write data signals having variable delays for use in writing data to memory components are provided below. These systems and methods, also referred to herein as variable delay write circuitry, receive a write data signal and a corresponding data valid or timing signal (also referred to as a write data valid signal or write data timing signal) and in turn generate multiple delayed versions of the write data signals and delayed valid signals. The memory system selects one of these delayed write data signals and delayed data valid signals for use in writing data to memory components.


In operation the variable delay write circuitry receives a write data signal and a corresponding data valid signal, and uses circuitry including register storage elements and calibrated delay elements to generate delayed write data signals and delayed valid signals with variable delays. The write data signal and the corresponding multiple delayed write data signals include data to be transferred to the memory components during a write operation. The data valid signal and corresponding delayed valid signals indicate when data of the write data signal is valid. The variable delays of the delayed write data signals and delayed valid signals of an embodiment are in a range of approximately 1.00 to 2.75 clock periods or cycles, but are not so limited.


The variable delay write circuitry selects one of the delayed write data signals and one of the delayed valid signals for output. Each of the selected output signals has a delay that best compensates for the mismatch of the propagation delay values resulting from differences in the signal paths used to couple signals between the variable delay write circuitry and the memory component. In this manner the variable delay write circuitry allows for relaxed signal path matching constraints (propagation delay values) and also reduces the burden on circuitry of the memory component to compensate for misalignment between the timing events of the various received signals. The variable delay write circuitry is for use in memory systems which include, for example, double data rate (DDR) systems like DDR SDRAM as well as DDR2 SDRAM and other DDR SDRAM variants, such as reduced latency DRAM (RLDRAM), RLDRAM2, Graphics DDR (GDDR) and GDDR2, GDDR3, but is not limited to these memory systems.


In the following description, numerous specific details are introduced to provide a thorough understanding of, and enabling description for, embodiments of the variable delay write circuitry. One skilled in the relevant art, however, will recognize that these embodiments can be practiced without one or more of the specific details, or with other components, systems, etc. In other instances, well-known structures or operations are not shown, or are not described in detail, to avoid obscuring aspects of the disclosed embodiments.



FIG. 1 is a block diagram of a memory system 100 that includes variable delay write circuitry 150 for generating write data signals and data valid signals with variable delays, under an embodiment. This memory system 100 includes a memory controller 102 coupled to one or more memory components 104-2 and 104-3; while two memory components 104-2/104-3 are shown the embodiment is not limited to any number of memory components. The memory system 100 operates in a number of modes including calibration, transmitter, and receiver modes. The memory controller 102 includes address circuitry 112 to drive address/control information to circuits or components that include the memory components 104-2/104-3. The address/control information includes but is not limited to address/control signals A0 and address/control valid signals T0.


The memory controller 102 of an embodiment includes the variable delay write circuitry 150 to drive write data information signals W0 and T0 to the memory components 104-2/104-3. The variable delay write circuitry 150 of an embodiment includes delay circuits 152, storage circuits 154, and output circuits 156, but is not limited to these circuits. The delay circuits 152 receive write data valid signals T0 and in response generate a number of delayed data valid signals T0+Y. The multiple delayed data valid signals T0+Y include delayed versions of the write data valid signals T0, as described below. The delayed data valid signals T0+Y couple to the storage circuits 154 and the output circuits 156, as described below.


The storage circuits 154 of an embodiment couple to receive the delayed data valid signals T0+Y from the delay circuits 152 as well as write data signal W0, data valid signal T0, and control signal Sel[2, 1, 0]. The storage circuits in turn generate a number of delayed write data signals WD. Each delayed write data signal WD is delayed a period of time in a range of approximately 1.00 to 2.75 clock periods or cycles, as described below, but is not so limited. The delayed write data signals WD couple to the output circuits 156.


The output circuits 156 couple to receive the delayed write data signals WD from the storage circuits 154 and the delayed data valid signals T0+Y from the delay circuits 152. Additionally, the output circuits 156 couple to receive the control signal Sel[2, 1, 0]. The output circuits 156 in response to information of the control signal Sel[2, 1, 0] select one of the delayed write data signals WD for the transfer of write data information as write data signal W1 to the memory components 104-2/104-3, as described below. Further, the output circuits 156 select one of the delayed data valid signals T0+Y for output to the memory components 104-2/104-3 as write data valid signal TW1 (also referred to as delayed write data valid signal TW1).


Information is carried on signal paths between the memory controller 102 and the memory components 104-2/104-3 by a signal, where the signal includes a symbol that propagates along the signal path. The memory system 100 uses a variety of signals to couple the memory controller 102 and the memory components 104-2/104-3, as described above. One set of signals include address/control signals A and the corresponding valid signals TA (also referred to as address/control valid signals TA). The address/control signals A carry address and control information, and are labeled as A0, A1, and A2 to show the address/control signals at different points along the signal path between the memory controller 102 and the memory components 104-2/104-3. The valid signals TA carry timing information that indicates when information is valid on the address/control signals A. The valid signals are labeled as TA0, TA1, and TA2 to show the valid signals at different points along the signal path between the memory controller 102 and the memory components 104-2/104-3.


Another set of signals that couple the memory controller 102 and the memory components 104-2/104-3 include write data signals W and the corresponding data valid signals TW (also referred to as write data valid signals TW). The write data signals W carry write data information, and are labeled as W0, W1, and W2 to show the write data signals at different points along the signal path between the memory controller 102 and the memory components 104-2/104-3. The data valid signals TW carry timing information that indicates when information is valid on the write data signals W. The valid signals are labeled as TW0, TW1, and TW2 to show the valid signals at different points along the signal path between the memory controller 102 and the memory components 104-2/104-3. Note that the label for address/control timing signal TA0 is shortened to T0 in the memory system 100, and likewise, the label for data valid signal TW0 is shortened to T0 because the address circuitry 112 and the write data circuitry 150 operate within a common timing domain in the memory controller 102.


The valid signals TA and TW carry timing information in the form of events, such as a transition between two symbol values. The transition between two symbol values can include, for example, a falling edge or a rising edge of the signal. A valid signal indicates when valid information is present on a set of related signals. Each timing event may be related to one symbol on each signal of the set, or it may be related to more than one symbol on each signal. The valid signal may only have timing events when there are valid symbols on the associated set of signals, or it may have timing events when there are no valid symbols. Consequently, each bit on the address/control signal A is associated with a timing event on the corresponding address valid signal TA (a rising edge for example). Similarly, each bit on the write data signal W is associated with a timing event on the data valid signal TW.


Alternative embodiments of the memory system described herein associate each rising edge on an address valid signal TA and/or data valid signal TW with two successive bits on each address and control signal A and/or write data signal W signal. Other alternative embodiments of the memory system described herein associate each rising edge and each falling edge on an address valid signal TA and/or data valid signal TW with each successive bit on each address and control signal A and/or write data signal W signal.


Taking one memory component as an example, the address and control signal A2 is received at the memory component 104-2 along with the address valid signal TA2, and is coupled to the core circuitry 114-2 of the memory component 104-2. This core circuitry 114-2 operates in the TA2 timing domain. The TA2 timing domain is delayed from the T0 timing domain of the memory controller 102 by the propagation delay time tPD-A (the time required by the signals at A1 and TA1 to propagate to A2 and TA2, respectively).


Additionally, the write data signal W2 is received at the write circuitry 124-2 of the memory component 104-2 with the data valid signal TW2. The write circuitry 124-2 operates in the TW2 timing domain, where the TW2 timing domain is delayed from the T0 timing domain of the memory controller 102 by the propagation delay time tPD-W (the time required by the signals at W1 and TW1 to propagate to W2 and TW2, respectively).


In writing data to the core circuitry 114-2 of the memory component 104-2 during a write operation, write data W2 received at the write circuitry 124-2 (TW2 timing domain) must be transferred to the core circuitry 114-2 (TA2 timing domain). This transfer is accomplished by the interface circuitry 134-2, where the interface circuitry 134-2 compensates for timing differences between the TW2 timing domain and the TA2 timing domain. The timing difference between the timing domains TW2 and TA2 is determined by taking the difference between tPD-A and tPD-W propagation delay times.


The interface circuitry 134-2 typically compensates for timing differences between the TW2 timing domain and the TA2 timing domain of approximately +/−tDQSS. During write operations the variable delay write circuitry 150, using information of the control signal Sel[2,1,0], selects one signal of the delayed write data signals WD for transmission to memory component 104-2 as signal W1 and one delayed data valid signal T0+Y for transmission to memory component 104-2 as signal TW1. Each of the selected signals W1 and TW1 has a delay that best compensates for the mismatch of the propagation delay values (tPD-A and tPD-W values) resulting from differences in the respective signal paths that couple the data W1 and valid TW1 signals to the memory component 104-2. In this manner the variable delay write circuitry 150 allows for relaxed signal path matching constraints (for the tPD-A and tPD-W values) while reducing the burden on the interface circuitry to compensate for misalignment between the timing events of the data valid signals TW2 and the corresponding address/control valid signals TA2.


Operation of memory component 104-3 is similar to that of memory component 104-2. The address and control signal A3 is received at the memory component 104-3 along with the address valid signal TA3, and is coupled to the core circuitry 114-3 of the memory component 104-3. This core circuitry 114-3 operates in the TA3 timing domain. The write data signal W3 is received at the write circuitry 124-3 along with the data valid signal TW3. The write circuitry 124-3 operates in the TW3 timing domain. In writing data to the core circuitry 114-3 of the memory component 104-3 during a write operation, write data W3 received at the write circuitry 124-3 (TW3 timing domain) must be transferred to the core circuitry 114-3 (TA3 timing domain). This transfer is accomplished by the interface circuitry 134-3, where the interface circuitry 134-3 compensates for timing differences between the TW3 timing domain and the TA3 timing domain.



FIG. 2 is another block diagram of the memory system 100 that includes variable delay write circuitry 150 for generating variably delayed write data signals W1 and variably delayed data valid signals TW1, under an embodiment. As described above the variable delay write circuitry 150 includes delay circuits 152, storage circuits 154, and output circuits 156. The delay circuits 152 receive write data valid signals T0 and in response generate a plurality of data valid signals T0+Y.


The delay circuits 152 of an embodiment include a delay line 202, a compare circuit or comparator 204, and a delay control signal 206 that function as a delay-locked-loop (DLL) to produce a number of accurate delay signals. The delay line 202 includes four unit delay elements DE1, DE2, DE3, and DE4 coupled in series; alternative embodiments can include any number of unit delay elements. Each unit delay element DE1-DE4 delays the input signal by an amount that is approximately equal to the median delay of the variable delay element DE1-DE4, such as one-fourth of the timing signal period (i.e., 90 degrees), but alternative embodiments will use other delay values.


The first unit delay element DE1 in the series of delay elements couples to receive the write data valid signal T0 as an input. The delay line 202 provides a delayed signal having a total delay that is approximately one period of the write data timing signal T0. Therefore, each of the four unit delay elements DE1-DE4 delays the write data valid signal T0 by an amount that is approximately one-fourth of the write data valid signal T0 period.


The delay line 202 (delayed signal) couples to a first input of the comparator 204 while the write data valid signal T0 (undelayed signal) couples to a second input of the comparator 204. The comparator uses information of a comparison between the write data valid signal T0 and the delayed write data valid signal of the delay line 202 (one clock period delay) to generate the control signal 206. The comparator outputs the control signal 206 for use in controlling delays or timing offsets of one or more of the unit delay elements DE1-DE4. The control signal 206 can be any of a variety of signal types known in the art, such as voltage bias signals, current bias signals, or digital delay-control signals. The offsets of the delay elements DE1-DE4 are controlled within a pre-specified range in response to variations in operating parameters of the memory system 100.


The delay circuits 152 output four data valid signals that couple to each of the storage circuits 154 and output circuits 156. In addition to outputting the write data valid signal T0 (alternatively referred to herein as T0+0.00), the delay circuits 152 provide three delayed valid signals with delays of +0.25, +0.50, and +0.75 clock periods or cycles of the write data valid signal T0. The output of the first unit delay element DE1 provides the first delayed valid signal with a +0.25 period delay (T0+0.25), the output of the second unit delay element DE2 provides the second delayed valid signal with a +0.50 period delay (T0+0.50), and the output of the third unit delay element DE3 provides the third delayed valid signal with a +0.75 period delay (T0+0.75), but the embodiment is not so limited.


The delay circuits of various alternative embodiments can include one or more phase-locked-loops (PLLs) instead of the DLL to generate the delayed valid signals. The PLLs produce phase-aligned signals having four times the frequency of the write data valid signal, but are not so limited.


The storage circuits 154 of an embodiment include a 2-to-1 multiplexer 220 that couples to receive input signals comprising the write data signal W0 and a delayed write data signal W0+1.00. The multiplexer 220 receives the delayed write data signal W0+1.00 via a coupling with a first register storage element 222. The first register storage element 222 couples to receive and load the write data signal W0 in response to a rising edge on the write data valid signal T0, but is not limited to loading on a rising edge. The first register storage element 222 outputs the delayed write data signal W0+1.00, which is delayed by approximately 1.00 clock period. The delayed write data signal W0+1.00 of alternative embodiments can be delayed by different clock periods.


The multiplexer 220 selects one of the write data signal W0 and the delayed write data signal W0+1.00 as an output data signal 226 in response to information of a control signal Sel[2], as described below. Consequently, the multiplexer 220 provides output data signals 226 having a variable delay of approximately zero (0.00) or 1.00 clock periods or cycles.


The output data signal 226 of the multiplexer couples to an input of a second register storage element 228. The second register storage element 228 receives and loads the output data signal 226 in response to a rising edge on the write data valid signal T0, but is not limited to loading the signal on the rising edge. The second register storage element 228 outputs a delayed write data signal 230 delayed by approximately 1.00 clock period relative to the received data signal 226. The delayed write data signal 230 of alternative embodiments can be delayed by different time periods.


The delayed write data signal 230 output of the second register storage element 228 couples to a series coupling of four register storage elements 232/236/240/244; alternative embodiments can include any number/combination of register storage elements. Each of the series storage elements 232/236/240/244 generally couples to receive and load a delayed write data signal in response to a falling edge of a data valid signal received from the delay circuits 152, but is not limited to loading the signal on the falling edge. Further, each of the series storage elements 232/236/240/244 outputs a delayed write data signal that is delayed relative to its input in accordance with the data valid signal used as the clock signal of the series storage element as described below; alternative embodiments can use different values and/or combinations of delay periods.


For example, the first series storage element 232 of the series couples to receive and load the delayed write data signal 230 from the second register storage element 228 in response to a falling edge on the write data valid signal T0+0.00. The first series storage element 232 outputs a delayed write data signal 234 that is undelayed relative to the delayed write data signal 230. The delayed write data signal 234, which has a delay of either approximately 1.00 or 2.00 clock periods relative to the write data signal W0 (depending on control signal Sel[2]), couples to the input of the second series storage element 236 as well as an input of the output circuitry 156.


The second series storage element 236 of the series couples to receive and load the delayed write data signal 234 from the first series storage element 232 in response to a falling edge on the write data valid signal T0+0.25. The second series storage element 236 therefore outputs a delayed write data signal 238 that is further delayed by one-quarter clock period relative to the delayed write data signal 234. The delayed write data signal 238, which has a delay of either approximately 1.25 or 2.25 clock periods relative to the write data signal W0 (depending on control signal Sel[2]), couples to the input of the third series storage element 240 as well as an input of the output circuitry 156.


The third series storage element 240 of the series couples to receive and load the delayed write data signal 238 from the second series storage element 236 in response to a falling edge on the write data timing valid T0+0.50. The third series storage element 240 thus outputs a delayed write data signal 242 that is further delayed by one-quarter clock period relative to the delayed write data signal 238. The delayed write data signal 242, which has a delay of either approximately 1.50 or 2.50 clock periods relative to the write data signal W0 (depending on control signal Sel[2]), couples to the input of the fourth series storage element 244 as well as an input of the output circuitry 156.


The fourth series storage element 244 of the series couples to receive and load the delayed write data signal 242 from the third series storage element 240 in response to a falling edge on the write data valid signal T0+0.75. The fourth series storage element 244 therefore outputs a delayed write data signal 246 that is further delayed by one-quarter clock period relative to the delayed write data signal 242. The delayed write data signal 246, which has a delay of either approximately 1.75 or 2.75 clock periods relative to the write data signal W0 (depending on control signal Sel[2]), couples to an input of the output circuitry 156.


The output circuitry 156 of an embodiment includes two multiplexers 262 and 264 which, under control of control signal Sel[1,0], allow selection of one of the four delayed versions of the write data signal W0 and one of the four data valid signals T0, respectively, for output to the memory components. A first 4-to-1 multiplexer 262 couples to receive input signals 234/238/242/246 from the storage circuits 154. The input signals 234/238/242/246 include the four delayed versions of the write data signal W0. When the input multiplexer 220 of the storage circuits 154 selects the write data signal W0 as the output data signal 226 in response to information of control signal Sel[2], the input signals 234/238/242/246 have delays of approximately 1.00/1.25/1.50/1.75 periods, respectively. Alternatively, when the input multiplexer 220 of the storage circuits 154 selects the delayed write data signal W0+1.00 as the output data signal 226 in response to information of control signal Sel[2], the input signals 234/238/242/246 have delays of approximately 2.00/2.25/2.50/2.75 periods, respectively. The write data signal selected for output from the first multiplexer 262 is driven onto the write data signal path as variable delay write data signal W1 for transmission to the memory components 104.


A second 4-to-1 multiplexer 264 of the output circuitry 156 couples to receive input signals T0+0.00/T0+0.25/T0+0.50/T0+0.75 from the delay circuits 152. The input signals T0+0.00/T0+0.25/T0+0.50/T0+0.75 include four different versions of the write data valid signal T0. The data valid signal selected for output from the second multiplexer 264 is driven onto the write data signal path as variable delay valid signal TW1 for transmission to the memory components 104.



FIG. 3 is a timing diagram 300 showing the delayed data valid signals T0+Y (where “Y” is one of 0.00 (+1.00), +0.25, +0.50, and +0.75) along with the corresponding write data valid signals TW1 selected for output by the variable delay write circuitry, under an embodiment. With further reference to FIG. 2, the delay circuits 152 output the write data valid signal T0 (T0+0.00) along with three delayed data valid signals, as described above. The first delayed data valid signal T0+0.25 has a +0.25 period delay, the second delayed data valid signal T0+0.050 has a +0.50 period delay, and the third delayed data valid signal T0+0.075 has a +0.75 period delay (T0+0.75), but the embodiment is not so limited. The T0+1.00 timing signal will be approximately the same as the T0+0.00 signal, since T0 is periodic in this example.


The write data valid signals T0+Y are used as described above to generate numerous variable delay write data signals for use as data write signal W1. The write data signal W1 is therefore a selectively delayed version of the write data signal W0 which can be selectively delayed in approximately 0.25-period increments over a range of 1.00 to 2.75 periods using the control signal Sel[2,1,0]. Note that only the data valid signal TW1 is shown in the timing diagram 300 to represent each of the eight delayed write data signals because the corresponding write data signal W1 remains centered on the variable delay write data timing signal TW1 in each case (as the relationship is shown with the signal combination W0 relative to T0320).


The variable delay write circuitry outputs a write data valid signal TW1302 delayed by approximately 1.00 period when the control signal Sel[2,1,0] includes logic values “000”. With further reference to FIG. 2, the first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“00”) of control signal Sel[1,0] select the timing signal T0+1.00 as the valid signal TW1 output 302 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.00 is generated using the next timing event (a rising edge in this example); the circuitry to do this is a component of enabling logic that creates timing events on the TW1 signal when the TW1 signal is not periodic). The control signal Sel[1,0] also selects the write data signal 234 (W0+1.00) as the write data signal W1 output from multiplexer 262.


The variable delay write circuitry outputs a write data valid signal TW1304 delayed by approximately 1.25 periods when the control signal Sel[2,1,0] includes logic values “001”. The first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“01”) of control signal Sel[1,0] select the timing signal T0+0.25 as the valid signal TW1 output 304 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.25 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 238 (W0+1.25) as the write data signal W1 output of multiplexer 262.


The variable delay write circuitry outputs a write data timing signal TW1306 delayed by approximately 1.50 periods when the control signal Sel[2,1,0] includes logic values “010”. The first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“10”) of control signal Sel[1,0] select the timing signal T0+0.50 as the valid signal TW1 output 306 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.50 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 242 (W0+1.50) as the write data signal W1 output of multiplexer 262.


The variable delay write circuitry outputs a write data timing signal TW1308 delayed by approximately 1.75 periods when the control signal Sel[2,1,0] includes logic values “011”. The first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“11”) of control signal Sel[1,0] select the timing signal T0+0.75 as the valid signal TW1 output 308 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.75 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 246 (W0+1.75) as the write data signal W1 output of multiplexer 262.


The variable delay write circuitry outputs a write data timing signal TW1310 delayed by approximately 2.00 periods when the control signal Sel[2,1,0] includes logic values “100”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“00”) of control signal Sel[1,0] select the timing signal T0+1.00 as the valid signal TW1 output 310 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.00 is generated using the next timing event (a rising edge in this example); the circuitry to do this is a component of enabling logic that creates timing events on the TW1 signal when the TW1 signal is not periodic). The control signal Sel[1,0] also selects the write data signal 234 (W0+2.00) as the write data signal W1 output of multiplexer 262.


The variable delay write circuitry outputs a write data timing signal TW1312 delayed by approximately 2.25 periods when the control signal Sel[2,1,0] includes logic values “101”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“01”) of control signal Sel[1,0] select the timing signal T0+0.25 as the valid signal TW1 output 312 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.25 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 238 (W0+2.25) as the write data signal W1 output of multiplexer 262.


The variable delay write circuitry outputs a write data timing signal TW1314 delayed by approximately 2.50 periods when the control signal Sel[2,1,0] includes logic values “110”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“10”) of control signal Sel[1,0] select the timing signal T0+0.50 as the valid signal TW1 output 314 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.50 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 242 (W0+2.50) as the write data signal W1 output of multiplexer 262.


The variable delay write circuitry outputs a write data timing signal TW1316 delayed by approximately 2.75 periods when the control signal Sel[2,1,0] includes logic values “111”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“11”) of control signal Sel[1,0] select the timing signal T0+0.75 as the valid signal TW1 output 316 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.75 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 246 (W0+2.75) as the write data signal W1 output of multiplexer 262.


As described above, control signals Sel[2,1,0] control selection of a write data signal W1 and the corresponding write data valid signal TW1 having a delay value appropriate to the signal paths between the memory controller and the memory components. The control signals are provided by one or more control circuits (not shown) that are components of and/or coupled to the memory controller. As an example, the control circuits of one or more embodiments can include one or more programmable registers. The content of the programmable registers, which control selection of the write data signal W1 and corresponding write data valid signal TW1 provided by the variable delay write circuitry, is determined in accordance with several approaches, including both automatic and user-programmable processes.


In one embodiment the content of the programmable registers is determined using information of a calibration process and automatically programmed into the registers of the control circuits. Generally, a calibration process can evaluate and compare the relative propagation delay information of each of the address/control signals and the corresponding write data signals across the respective signal paths. In so doing, the calibration process determines which of the delayed write data signals and delayed write data valid signals is optimal for use in writing data to the memory components. Alternatively, the content of the programmable registers is manually programmed into the registers of the control circuits by a user.


Regarding the calibration process of an embodiment, and taking one memory component as an example, a memory controller or other component of a host system places one or more components of the memory system in a calibration mode. In the calibration mode, the memory controller performs a series of dummy write operations to the memory component during which a number of write operation are performed, with each write operation using a different one of the delayed versions of the write data signal. A dummy write is generally defined to include a process in which a memory controller writes pre-specified data to a memory component, independent of any data needs of components of the memory system or other higher layer machine-readable code; these writes are performed at power-up, or other intervals in which the memory component was otherwise not being utilized.


Following completion of the dummy write operations the memory controller reads the data of all dummy write operations from the memory component and compares the read data with the actual data written to identify successful write operations. Timing information of the successful dummy write operations allows for identification of the particular delayed write data signal providing the best timing margin. The logic values that identify the delayed write data signal providing the best timing margin are then programmed into the programmable registers.


Generally the memory system selects a delayed data signal for write operations that minimizes the difference between the propagation delay times of the data signals and the corresponding address/control signals. The propagation delay times are as measured across signal paths between the memory controller and one or more memory components but are not so limited. FIG. 4 is a block diagram 400 for generating write data signals and write data valid signals with selectable delays for use in memory write operations, under an embodiment. Circuitry or components of a memory system, for example a memory controller, select data for write operations to memory components or devices, at block 402. The memory system of an embodiment generates data signals and data valid signals for use in transferring the selected data of the write operation to the memory components via a first signal path, at block 404. The memory system uses the data valid signals to generate delayed data valid signals that include multiple delayed versions of the data valid signal, at block 406, where each delayed data valid signal has a different amount of delay. The memory system, using the delayed data valid signals, generates delayed data signals that include multiple delayed versions of the data signal, at block 408. Each delayed data signal also has a different amount of delay, but the embodiment is not so limited.


During memory write operations, components of the memory system transfer the data signals and data valid signals to the memory components via a first signal path. Additionally, address/control signals and address/control valid signals are generated and transferred to the memory components via a second signal path. Control signals select one of the delayed data signals and one of the delayed data valid signals for use in driving data of the write operations to the memory components, at block 410. Selection of a particular delayed data signal and corresponding delayed data valid signal is in accordance with pre-determined differences in propagation delay times between the first and second signal paths. Thus, the memory system selects the delayed data signal and delayed data valid signal that minimizes the difference between the propagation delay times of the data signals across the first signal path and the address/control signals across the second signal path. The selected data is transferred to the memory components using the delayed data signal, at block 412.



FIG. 5 is a timing diagram 500 for signals of an example write operation in a memory system that generates write data signals with variable delays, under an embodiment. As described above, a memory controller selects write data for a write operation to a memory component and generates data signals W0 and corresponding data valid signals T0 for use in transferring the data to the memory components via a write data signal path. Additionally, the memory controller generates address/control signals A0 and address/control valid signals T0 corresponding to the data signals W0, and transfers the signals A0 and T0 to the memory components via an address/control signal path.


The memory controller uses the data valid signals T0 to generate a number of delayed data valid signals. The delayed data valid signals of an embodiment include a data valid signal delayed approximately 0.00 (1.00) clock periods, a data valid signal delayed approximately 0.25 clock periods, a data valid signal delayed approximately 0.50 clock periods, and a data valid signal delayed approximately 0.75 clock periods, but are not so limited. The memory system also uses the delayed data valid signals along with the data signals W0 to generate a number of delayed data signals. The delayed data signals of an embodiment include a data signal delayed approximately 1.00 clock period, a data signal delayed approximately 1.25 clock periods, a data signal delayed approximately 1.50 clock periods, a data signal delayed approximately 1.75 clock periods, a data signal delayed approximately 2.00 clock periods, a data signal delayed approximately 2.25 clock periods, a data signal delayed approximately 2.50 clock periods, and a data signal delayed approximately 2.75 clock periods, but are not so limited.


The memory controller uses control signals to select one of the delayed data signals and one of the delayed data valid signals for use in the write operation. The selection of the delayed signals is in accordance with pre-determined differences between signal propagation times across the address/control signal path (tPD-A) and signal propagation times across the write data signal path (tPD-w). In particular, the memory controller selects the signals having a delay value that minimizes the difference between the propagation delay times tPD-A and tPD-w.


The pre-determined differences between the signal propagation times are determined during a calibration process, as described above, but are not so limited. This example assumes a difference between propagation delay times that results in selection of a 2.25 clock period delay (corresponding to control signal Sel[2,1,0] that includes logic values “101”).


The memory controller drives the address/control signals A0 and address/control valid signals T0 onto the address/control signal path as address/control signals A1 and address/control valid signals TA1. The memory component receives the address/control signals A2 and address/control valid signals TA2 at time tPD-A later following propagation across the address/control signal path.


Under control of control signal Sel[2,1,0] the memory controller drives each of the data signals W1 and data valid signals TW1 onto the write data signal path at a time that is 2.25 clock periods after driving the address/control signals A1 and address/control valid signals TA1. The memory component receives the data signals W2 and data valid signals TW2 at time tPD-W later following propagation across the write data signal path.


While write operations result in a mismatch between the timing of the address/control signals and data signals at the memory component(s), the memory system using variable delay write circuitry reduces the magnitude of this mismatch. A comparison of the signal timing 500 of the memory system using data write signals with variable delays to signal timing 900 of the memory system using data signals with fixed delays, with reference to FIG. 5 and FIG. 9, shows a reduction in the timing mismatch between the timing events in the two systems when using the variable delays. The additional 0.25 clock period delay of the variable delay signal (relative to the fixed delay signal in memory system 800 of FIG. 8) compensates for the fact that the tPD-A delay is greater than the tPD-W delay. Consequently, the difference 502 in rising edge timing events of the address/control signals TA2 and the data signals TW2 using variable delays is reduced when compared to the difference 902 in rising edge timing events of the address/control signals and the data signals using fixed delays. The closer alignment of the rising edge timing events allows the interface circuitry to readily compensate for the timing mismatch thus increasing the reliability and accuracy of data writes to memory components while relaxing the signal path matching constraints.


One or more alternative embodiments can apply a select delay to independent sets of write data signals WX and timing signals TWX. For example, a memory controller can generate/use one delayed timing signal TW1 for every eight data signals W1. Each group of nine TW1/W1 signals therefore would use the same amount of delay.


Furthermore, the variable delay write circuitry of an embodiment also provides increased control over propagation delay differences in write operations to memory components of multiple-slice memory systems. FIG. 6 is a block diagram of a multiple-slice memory system 600 that includes the variable delay write circuitry 150 for generating write data signals and data valid signals with variable delays, under an embodiment. This memory system 600 includes a memory controller 602 coupled to one or more memory components 604-a in memory slice Sa and one or more memory components 604-b in memory slice Sb; while two memory slices are shown the embodiment is not limited to any number of memory slices and/or components. The memory controller 602 drives address/control signals A and address/control valid signals TA to the memory components 604-a/604-b.


Difficulty can be found in controlling the difference between the propagation delays of the TA/A signals and the TW/W signals in this multi-slice memory system because the TA/A signals are coupled to two or more memory components (slices). Each slice Sa and Sb therefore sees a different propagation delay on the TA/A signals (tPD-Aa, tPD-Ab) as a result. The delay of the TW/W signal groups (tPD-Wa, tPD-Wb) will however tend to be approximately the same, since these signal groups have a similar routing topology.


The memory controller 602 of an embodiment can use the variable delay write circuitry 150 to accommodate the different propagation delay values between memory slices Sa and Sb. The variable delay write circuitry 150 can be programmed to different delay values for each TW/W signal group in order to accommodate the differences in propagation delays between the TA/A signals to the respective memory slices. For example, the variable delay write circuitry 150 operating generally as described above with reference to FIGS. 1-5 transfers write data signals Wa and write data valid signals TWa to memory component 604-a where signals Wa/TWa are delayed using a first variable delay. Likewise, variable delay write circuitry 150 transfers write data signals Wb and write data valid signals TWb to memory component 604-b where signals Wb/TWb are delayed using a second variable delay.


The variable delay write circuitry of an embodiment also provides increased control over propagation delay differences in write operations to memory components of multiple-rank memory systems. FIG. 7 is a block diagram of a multiple-rank memory system 700 that includes the variable delay write circuitry 150 for generating write data signals and data valid signals with variable delays, under an embodiment. This memory system 700 includes a memory controller 702 coupled to one or more memory components 704-z in memory rank Rz and one or more memory components 704-y in memory rank Ry; while two memory ranks are shown the embodiment is not limited to any number of memory ranks and/or components. The memory controller 702 drives write data signals W and write data valid signals TW to the memory components 704-z/704-y.


Difficulty can be found in controlling the difference between the propagation delays of the TA/A signals and the TW/W signals in this multi-rank memory system because the TW/W signals are coupled to two or more memory components (ranks). Each rank Rz and Ry therefore sees a different propagation delay on the TW/W signals (tPD-Wz, tPD-Wy) as a result. The delay of the TA/A signal groups (tPD-Az, tPD-Ay) will however tend to be approximately the same, since these signal groups have a similar routing topology.


The memory controller 702 of an embodiment can use the variable delay write circuitry 150 to accommodate the different propagation delay values between memory ranks Rz and Ry. The variable delay write circuitry 150 can be programmed to different delay values for each TA/A signal group in order to accommodate the differences in propagation delays between the TW/W signals to the respective memory ranks. For example, the variable delay write circuitry 150 operating generally as described above with reference to FIGS. 1-5 transfers address/control signals Az and address/control valid signals TAz to memory component 704-z where signals Az/TAz are delayed using a first variable delay. Likewise, variable delay write circuitry 150 transfers address/control signals Ay and address/control valid signals TAy to memory component 704-y where signals Ay/TAy are delayed using a second variable delay.


The components of the memory systems described above include any collection of computing components and devices operating together. The components of the memory systems can also be components or subsystems within a larger computer system or network. The memory system components can also be coupled among any number of components (not shown), for example other buses, controllers, memory devices, and data input/output (I/O) devices, in any number of combinations. Many of these system components may be soldered to a common printed circuit board (for example, a graphics card or game console device), or may be integrated in a system that includes several printed circuit boards that are coupled together in a system, for example, using connector and socket interfaces such as those employed by personal computer motherboards and dual inline memory modules (“DIMM”). In other examples, complete systems may be integrated in a single package housing using a system in package (“SIP”) type of approach. Integrated circuit devices may be stacked on top of one another and utilize wire bond connections to effectuate communication between chips or may be integrated on a single planar substrate within the package housing.


Further, functions of the memory system components can be distributed among any number/combination of other processor-based components. The memory systems described above include, for example, various dynamic random access memory (DRAM) systems. As examples, the DRAM memory systems can include double data rate (“DDR”) systems like DDR SDRAM as well as DDR2 SDRAM and other DDR SDRAM variants, such as Graphics DDR (“GDDR”) and further generations of these memory technologies, i.e., GDDR2, and GDDR3, but is not limited to these memory systems.


Aspects of the system for per-bit offset control and calibration described herein may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits (ASICs). Some other possibilities for implementing aspects of the per-bit offset control and calibration system include: microcontrollers with memory (such as electronically erasable programmable read only memory (EEPROM)), embedded microprocessors, firmware, software, etc.


Furthermore, aspects of the per-bit offset control and calibration system may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course the underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (MOSFET) technologies like complementary metal-oxide semiconductor (CMOS), bipolar technologies like emitter-coupled logic (ECL), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, etc.


It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.).


When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.


Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number, respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.


The above description of illustrated embodiments of the memory systems and methods is not intended to be exhaustive or to limit the memory systems and methods to the precise form disclosed. While specific embodiments of, and examples for, the memory systems and methods are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the memory systems and methods, as those skilled in the relevant art will recognize. The teachings of the memory systems and methods provided herein can be applied to other processing systems and methods, not only for the memory systems and methods described above.


The elements and acts of the various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the memory systems and methods in light of the above detailed description.


In general, in the following claims, the terms used should not be construed to limit the memory systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Accordingly, the memory systems and methods is not limited by the disclosure, but instead the scope of the memory systems and methods is to be determined entirely by the claims.


While certain aspects of the memory systems and methods are presented below in certain claim forms, the inventor contemplates the various aspects of the memory systems and methods in any number of claim forms. For example, while only one aspect of the system is recited as embodied in computer-readable medium, other aspects may likewise be embodied in computer-readable medium. Accordingly, the inventor reserves the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the memory systems and methods.

Claims
  • 1. An integrated circuit device comprising: a clock signal driver to output a clock signal to a dynamic random access memory device (DRAM) via a clock signal line; anda data timing signal driver to output to the DRAM via a data timing signal line: a sequence of calibration data timing signals having respective phase offsets relative to the clock signal to enable, during a timing calibration operation, identification of a phase offset of one of the calibration data timing signals that compensates for a difference in signal propagation times over the clock signal line and data timing signal line; andduring a memory write operation, a write data timing signal having the identified phase offset.
  • 2. The integrated circuit device of claim 1 wherein the identified phase offset provides increased write data timing margin relative to phase offsets of others of the calibration data timing signals.
  • 3. The integrated circuit device of claim 1 wherein the one of the calibration data timing signals having the identified phase offset arrives at the DRAM with less skew relative to arrival of the clock signal at the DRAM than others of the calibration data timing signals.
  • 4. The integrated circuit device of claim 1 wherein the data timing signal driver to output the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises a chain of delay elements and circuitry to select, during each of a sequence of time intervals that transpires during the timing calibration operation, an output of a respective delay element within the chain of delay elements and circuitry to transmit the output of the respective delay element onto the data timing signal line.
  • 5. The integrated circuit device of claim 1 further comprising signaling circuitry to effect a sequence of dummy write operations within the DRAM as part of the timing calibration operation and wherein the data timing signal driver to output the sequence of calibration data timing signals to the DRAM via the data timing signal line during the timing calibration operation comprises circuitry to output each of the calibration data timing signals to the DRAM via the data timing signal line as part of a respective one of the dummy write operations.
  • 6. The integrated circuit device of claim 5 further comprising signaling circuitry to effect, during the timing calibration operation, a sequence of memory read operations within the DRAM corresponding to the sequence of dummy write operations, and circuitry to determine, based on information obtained via the sequence of memory read operations, which calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations.
  • 7. The integrated circuit device of claim 6 further comprising circuitry to identify the phase offset that compensates for the difference in signal propagation times over the clock signal line and data timing signal line based at least in part on the determination of which calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations.
  • 8. The integrated circuit device of claim 1 further comprising a data signal driver to output a data signal to the DRAM during the memory write operation at a time indicated by the one of the calibration data timing signals having the identified phase offset.
  • 9. The integrated circuit device of claim 1 wherein the data timing signal driver to output the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises circuitry to output a sequence of calibration data timing signals having respective phase offsets that collectively span an interval equal to or greater than a period of the clock signal.
  • 10. A method of operation within an integrated circuit device, the method comprising: outputting a clock signal to a dynamic random access memory device (DRAM) via a clock signal line; andoutputting to the DRAM, via a data timing signal line and during a timing calibration operation, a sequence of calibration data timing signals having respective phase offsets relative to the clock signal to enable identification of a phase offset of one of the calibration data timing signals that compensates for a difference in signal propagation times over the clock signal line and data timing signal line; andoutputting to the DRAM, via the data timing signal line and during a memory write operation, a write data timing signal having the identified phase offset.
  • 11. The method of claim 10 wherein the identified phase offset provides increased write data timing margin relative to phase offsets of others of the calibration data timing signals.
  • 12. The method of claim 10 wherein the one of the calibration data timing signals having the identified phase offset arrives at the DRAM with less skew relative to arrival of the clock signal at the DRAM than others of the calibration data timing signals.
  • 13. The method of claim 10 wherein outputting the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises selecting, during each of a sequence of time intervals that transpires during the timing calibration operation, an output of a respective delay element within a chain of delay elements and transmitting the output of the respective delay element onto the data timing signal line.
  • 14. The method of claim 10 further comprising outputting signals to perform a sequence of dummy write operations as part of the timing calibration operation and wherein outputting the sequence of calibration data timing signals to the DRAM via the data timing signal line during the timing calibration operation comprises outputting each of the calibration data timing signals to the DRAM via the data timing signal line as part of a respective one of the dummy write operations.
  • 15. The method of claim 14 further comprising determining, through execution of memory read operations directed to the DRAM during the timing calibration operation, which calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations.
  • 16. The method of claim 15 further comprising identifying the phase offset that compensates for the difference in signal propagation times over the clock signal line and data timing signal line based at least in part on the determination of which calibration data timing signals within the sequence of calibration data timing signals enabled successful completion of the dummy write operations.
  • 17. The method of claim 10 further comprising outputting a data signal to the DRAM during the memory write operation at a time indicated by the one of the calibration data timing signals having the identified phase offset.
  • 18. The method of claim 10 wherein outputting the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises outputting a sequence of calibration data timing signals having respective phase offsets that collectively span an interval equal to or greater than a period of the clock signal.
  • 19. The method of claim 10 wherein outputting the sequence of calibration data timing signals having respective phase offsets relative to the clock signal comprises outputting a sequence of calibration data timing signals having respective phase offsets temporally staggered relative to one another by a predetermined fraction of a period of the clock signal.
  • 20. An integrated circuit device comprising: means for outputting a clock signal to a dynamic random access memory device (DRAM) via a clock signal line; andmeans for outputting to the DRAM, via a data timing signal line and during a timing calibration operation, a sequence of calibration data timing signals having respective phase offsets relative to the clock signal to enable identification of a phase offset of one of the calibration data timing signals that compensates for a difference in signal propagation times over the clock signal line and data timing signal line; andmeans for outputting to the DRAM, via the data timing signal line and during a memory write operation, a write data timing signal having the identified phase offset.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 16/897,157 filed Jun. 9, 2020 (now U.S. Pat. No. 11,100,976), which is a continuation of U.S. patent application Ser. No. 16/418,316 filed May 21, 2019 (now U.S. Pat. No. 10,755,764), which is a continuation of U.S. patent application Ser. No. 15/805,009 filed Nov. 6, 2017 (now U.S. Pat. No. 10,325,645), which is a continuation of U.S. patent application Ser. No. 15/242,425 filed Aug. 19, 2016 (now U.S. Pat. No. 9,830,971), which is a continuation of U.S. patent application Ser. No. 14/951,190 filed Nov. 24, 2015 (now U.S. Pat. No. 9,437,279), which is a continuation of U.S. patent application Ser. No. 14/267,446 filed May 1, 2014 (now U.S. Pat. No. 9,229,470), which is a continuation of U.S. patent application Ser. No. 13/890,801 filed May 9, 2013 (now U.S. Pat. No. 8,743,636), which is a continuation of U.S. patent application Ser. No. 13/741,255 filed Jan. 14, 2013 (now U.S. Pat. No. 8,493,802), which is a continuation of U.S. patent application Ser. No. 13/554,967 filed Jul. 9, 2012 (now U.S. Pat. No. 8,363,493), which is a continuation of U.S. patent application Ser. No. 13/228,070 filed Sep. 8, 2011 (now U.S. Pat. No. 8,218,832), which is a division of U.S. patent application Ser. No. 12/757,035 filed Apr. 8, 2010 (now U.S. Pat. No. 8,045,407), which is a division of U.S. patent application Ser. No. 12/246,415 filed Oct. 6, 2008 (now U.S. Pat. No. 7,724,590), which is a division of U.S. patent application Ser. No. 11/746,007 filed May 8, 2007 (now U.S. Pat. No. 7,480,193), which is a continuation of U.S. patent application Ser. No. 10/942,225 filed Sep. 15, 2004 (now U.S. Pat. No. 7,301,831). Each of the above-referenced U.S. patent applications is hereby incorporated by reference.

US Referenced Citations (313)
Number Name Date Kind
3820081 Donahue Jun 1974 A
3950735 Patel Apr 1976 A
4183095 Ward Jan 1980 A
4266282 Henle et al. May 1981 A
4280221 Chun et al. Jul 1981 A
4315308 Jackson Feb 1982 A
4330852 Redwine et al. May 1982 A
4337523 Hotta et al. Jun 1982 A
4445204 Nishiguchi Apr 1984 A
4499536 Gemma et al. Feb 1985 A
4567545 Mettler Jan 1986 A
4637018 Flora et al. Jan 1987 A
4646270 Voss Feb 1987 A
4654790 Woffinden Mar 1987 A
4656605 Clayton Apr 1987 A
4712190 Guglielmi et al. Dec 1987 A
4719602 Hag et al. Jan 1988 A
4755937 Glier Jul 1988 A
4763249 Bomba et al. Aug 1988 A
4785206 Hoshi Nov 1988 A
4792926 Roberts Dec 1988 A
4792929 Olson et al. Dec 1988 A
4799199 Scales, III et al. Jan 1989 A
4800530 Itoh et al. Jan 1989 A
4821226 Christopher et al. Apr 1989 A
4825411 Hamano Apr 1989 A
4845664 Aichelmann, Jr. et al. Jul 1989 A
4845677 Chappell et al. Jul 1989 A
4849937 Yoshimoto Jul 1989 A
4866675 Kawashima Sep 1989 A
4866676 Crisp et al. Sep 1989 A
4866677 Sakurai Sep 1989 A
4866678 Pinkham et al. Sep 1989 A
4866679 Chambers Sep 1989 A
4866680 Scherbatskoy Sep 1989 A
4875192 Matsumoto Oct 1989 A
4882712 Ohno et al. Nov 1989 A
4891791 Iijima Jan 1990 A
4916670 Suzuki et al. Apr 1990 A
4920483 Pogue et al. Apr 1990 A
4928265 Higuchi et al. May 1990 A
4937734 Bechtolsheim Jun 1990 A
4945516 Kashiyama Jul 1990 A
4953128 Kawai et al. Aug 1990 A
5001672 Ebbers et al. Mar 1991 A
5077693 Hardee et al. Dec 1991 A
5083296 Hara et al. Jan 1992 A
5097489 Tucci Mar 1992 A
5111386 Fujishima et al. May 1992 A
5117389 Yiu May 1992 A
5124589 Shiomi et al. Jun 1992 A
5140688 White et al. Aug 1992 A
5164916 Wu et al. Nov 1992 A
5179687 Hidaka et al. Jan 1993 A
5239639 Fischer et al. Aug 1993 A
5260905 Mori Nov 1993 A
5276858 Oak et al. Jan 1994 A
5301278 Bowater et al. Apr 1994 A
5305278 Inoue Apr 1994 A
5311483 Takasugi May 1994 A
5319755 Horowitz et al. Jun 1994 A
5323358 Toda et al. Jun 1994 A
5327390 Takasugi Jul 1994 A
5329484 Tsuiki Jul 1994 A
5339276 Takasugi Aug 1994 A
5341341 Fukuzo Aug 1994 A
5343427 Teruyama Aug 1994 A
5345573 Bowden, III et al. Sep 1994 A
5357621 Cox Oct 1994 A
5365489 Jeong Nov 1994 A
5379438 Bell et al. Jan 1995 A
5381376 Kim et al. Jan 1995 A
5381538 Amini et al. Jan 1995 A
5384745 Konishi et al. Jan 1995 A
5386375 Smith Jan 1995 A
5386385 Stephens, Jr. Jan 1995 A
5390149 Vogley et al. Feb 1995 A
5392239 Margulis et al. Feb 1995 A
5404338 Murai et al. Apr 1995 A
5404463 McGarvey Apr 1995 A
5406518 Sun et al. Apr 1995 A
5422858 Mizukami et al. Jun 1995 A
5428389 Ito Jun 1995 A
5430676 Ware et al. Jul 1995 A
5444667 Obara et al. Aug 1995 A
5455803 Kodama Oct 1995 A
5475690 Burns et al. Dec 1995 A
5504874 Galles et al. Apr 1996 A
5511024 Ware et al. Apr 1996 A
5511025 Smith et al. Apr 1996 A
5530623 Sanwo et al. Jun 1996 A
5533204 Tipley Jul 1996 A
5548786 Amini et al. Aug 1996 A
5553248 Melo et al. Sep 1996 A
5560000 Vogley Sep 1996 A
5568445 Park et al. Oct 1996 A
5577236 Johnson et al. Nov 1996 A
5578940 Dillon et al. Nov 1996 A
5579352 Llewellyn Nov 1996 A
5606717 Farmwald et al. Feb 1997 A
5611058 Moore et al. Mar 1997 A
5615358 Vogley Mar 1997 A
5638531 Crump et al. Jun 1997 A
5646904 Ohno et al. Jul 1997 A
5649161 Andrade et al. Jul 1997 A
5655113 Leung et al. Aug 1997 A
5663661 Dillon et al. Sep 1997 A
5680361 Ware et al. Oct 1997 A
5708297 Clayton Jan 1998 A
5742798 Goldrian Apr 1998 A
5748914 Ware et al. May 1998 A
5764963 Ware et al. Jun 1998 A
5778419 Hansen et al. Jul 1998 A
5796624 Sridhar et al. Aug 1998 A
5819076 Jeddeloh et al. Oct 1998 A
5844855 Ware et al. Dec 1998 A
5857095 Jeddeloh Jan 1999 A
5867541 Tanaka et al. Feb 1999 A
5880998 Tanimura et al. Mar 1999 A
5892981 Wiggers Apr 1999 A
5917760 Millar Jun 1999 A
5928343 Farmwald et al. Jul 1999 A
5933379 Park et al. Aug 1999 A
5933387 Worley Aug 1999 A
5943573 Wen Aug 1999 A
5952691 Yamaguchi Sep 1999 A
5966343 Thurston Oct 1999 A
5987576 Johnson et al. Nov 1999 A
6003118 Chen Dec 1999 A
6005776 Holman et al. Dec 1999 A
6016282 Keeth Jan 2000 A
6029250 Keeth Feb 2000 A
6034878 Osaka et al. Mar 2000 A
6041419 Huang et al. Mar 2000 A
6044429 Ryan et al. Mar 2000 A
6049238 Shimizu et al. Apr 2000 A
6049467 Tamarkin et al. Apr 2000 A
6057743 Aekins May 2000 A
6065092 Roy May 2000 A
6067594 Perino et al. May 2000 A
6070217 Connolly May 2000 A
6075393 Tomita et al. Jun 2000 A
6075728 Inoue Jun 2000 A
6075730 Anderson et al. Jun 2000 A
6088774 Gillingham Jul 2000 A
6105144 Wu Aug 2000 A
6111757 Dell et al. Aug 2000 A
6115318 Keeth Sep 2000 A
6124727 Bridgewater, Jr. et al. Sep 2000 A
6125419 Umemura et al. Sep 2000 A
6131149 Lu et al. Oct 2000 A
6137734 Schoner et al. Oct 2000 A
6151271 Lee Nov 2000 A
6154417 Kim Nov 2000 A
6154821 Barth et al. Nov 2000 A
6160754 Suh Dec 2000 A
6172895 Brown et al. Jan 2001 B1
6178517 Bertin et al. Jan 2001 B1
6185644 Farmwald et al. Feb 2001 B1
6191997 Son et al. Feb 2001 B1
6192004 Aikawa Feb 2001 B1
6211703 Takekuma et al. Apr 2001 B1
6219384 Kliza et al. Apr 2001 B1
6226723 Gustavson et al. May 2001 B1
6226757 Ware et al. May 2001 B1
6232792 Starr May 2001 B1
6233157 Yoon May 2001 B1
6240039 Lee et al. May 2001 B1
6240495 Usui May 2001 B1
6253266 Ohanian Jun 2001 B1
6260097 Horowitz et al. Jul 2001 B1
6266285 Farmwald et al. Jul 2001 B1
6266730 Perino et al. Jul 2001 B1
6266737 Ware et al. Jul 2001 B1
6278300 Urakawa Aug 2001 B1
6279090 Manning Aug 2001 B1
6292877 Ryan Sep 2001 B1
6292903 Coteus et al. Sep 2001 B1
6304937 Farmwald et al. Oct 2001 B1
6310171 Naito et al. Oct 2001 B1
6314051 Farmwald et al. Nov 2001 B1
6321282 Horowitz et al. Nov 2001 B1
6336205 Kurokawa et al. Jan 2002 B1
6343352 Davis et al. Jan 2002 B1
6356260 Montalbo Mar 2002 B1
6359815 Sato et al. Mar 2002 B1
6388886 Tobita May 2002 B1
6388934 Tobita May 2002 B1
6400625 Arimoto Jun 2002 B2
6401167 Barth et al. Jun 2002 B1
6404258 Ooishi Jun 2002 B2
6442644 Gustavson et al. Aug 2002 B1
6445624 Janzen et al. Sep 2002 B1
6449159 Haba Sep 2002 B1
6449727 Toda Sep 2002 B1
6456544 Zumkehr Sep 2002 B1
6470405 Hampel et al. Oct 2002 B2
6477592 Chen et al. Nov 2002 B1
6493789 Ware et al. Dec 2002 B2
6496897 Ware et al. Dec 2002 B2
6502161 Perego et al. Dec 2002 B1
6504790 Wolford Jan 2003 B1
6510503 Gillingham et al. Jan 2003 B2
6516365 Horowitz et al. Feb 2003 B2
6526469 Drehmel et al. Feb 2003 B1
6539454 Mes Mar 2003 B2
6545875 Perino et al. Apr 2003 B1
6553472 Yang et al. Apr 2003 B2
6584037 Farmwald et al. Jun 2003 B2
6590781 Kollipara et al. Jul 2003 B2
6591353 Ware et al. Jul 2003 B1
6611905 Grundon et al. Aug 2003 B1
6618736 Menage Sep 2003 B1
6629222 Jeddeloh Sep 2003 B1
6629225 Zumkehr Sep 2003 B2
6640292 Barth et al. Oct 2003 B1
6643752 Donnelly et al. Nov 2003 B1
6643787 Zerbe et al. Nov 2003 B1
6646953 Stark Nov 2003 B1
6654897 Dreps et al. Nov 2003 B1
6657871 Perino et al. Dec 2003 B2
6675272 Ware et al. Jan 2004 B2
6680866 Kajimoto Jan 2004 B2
6681288 Ware et al. Jan 2004 B2
6684263 Horowitz et al. Jan 2004 B2
6697918 Rowlands Feb 2004 B2
6724666 Janzen et al. Apr 2004 B2
6748465 Howard et al. Jun 2004 B2
6760856 Borkenhagen et al. Jul 2004 B1
6760857 Lau et al. Jul 2004 B1
6765800 Haba et al. Jul 2004 B2
6788594 Ware et al. Sep 2004 B2
6804764 LaBerge et al. Oct 2004 B2
6807613 Keeth et al. Oct 2004 B1
6807614 Chung Oct 2004 B2
6813196 Park et al. Nov 2004 B2
6833984 Belgacem Dec 2004 B1
6839266 Ware et al. Jan 2005 B1
6839393 Sidiropoulos Jan 2005 B1
6853557 Haba et al. Feb 2005 B1
6868474 Barth et al. Mar 2005 B2
6873939 Zerbe et al. Mar 2005 B1
6889336 Schoenfeld et al. May 2005 B2
6898085 Haba et al. May 2005 B2
6912680 Keeth Jun 2005 B1
6920540 Hampel et al. Jul 2005 B2
6928571 Bonnella et al. Aug 2005 B1
6940782 Matsui Sep 2005 B2
6950956 Zerbe et al. Sep 2005 B2
6970988 Chung Nov 2005 B1
7031207 Nishioka Apr 2006 B2
7057948 Shimizu et al. Jun 2006 B2
7076745 Togo Jul 2006 B2
7095661 Osaka et al. Aug 2006 B2
7100066 Jeong Aug 2006 B2
7102905 Funaba et al. Sep 2006 B2
7120084 White et al. Oct 2006 B2
7126399 Lee Oct 2006 B1
7159092 Johnson et al. Jan 2007 B2
7171321 Best Jan 2007 B2
7177998 Ware et al. Feb 2007 B2
7197611 Barth et al. Mar 2007 B2
7200055 Ware et al. Apr 2007 B2
7209397 Ware et al. Apr 2007 B2
7210016 Ware et al. Apr 2007 B2
7224595 Dreps et al. May 2007 B2
7225292 Ware et al. May 2007 B2
7225311 Ware et al. May 2007 B2
7251162 Kawajiri et al. Jul 2007 B2
7287109 Barth et al. Oct 2007 B2
7287119 Barth et al. Oct 2007 B2
7313715 Yoo et al. Dec 2007 B2
7386696 Jakobs et al. Jun 2008 B2
7457174 Braun et al. Nov 2008 B2
7457189 Lee et al. Nov 2008 B2
7484064 Ware et al. Jan 2009 B2
7548601 Sidiropoulos Jun 2009 B2
7610524 Janzen Oct 2009 B2
8363493 Ware Jan 2013 B2
8391039 Ware et al. Mar 2013 B2
8462566 Ware et al. Jun 2013 B2
8537601 Ware et al. Sep 2013 B2
8717837 Ware et al. May 2014 B2
9437279 Ware Sep 2016 B2
10056130 Best Aug 2018 B2
10325645 Ware Jun 2019 B2
20010026487 Koga Oct 2001 A1
20010047450 Gillingham et al. Nov 2001 A1
20020021616 Keeth et al. Feb 2002 A1
20020174311 Ware et al. Nov 2002 A1
20030047757 Kumazaki et al. Mar 2003 A1
20030076702 Kyung et al. Apr 2003 A1
20030112677 Lehmann et al. Jun 2003 A1
20030117864 Hampel et al. Jun 2003 A1
20030200407 Osaka et al. Oct 2003 A1
20040003194 Bodas et al. Jan 2004 A1
20040054845 Ware et al. Mar 2004 A1
20040120197 Kondo et al. Jun 2004 A1
20040170072 Ware et al. Sep 2004 A1
20050169097 Ware et al. Aug 2005 A1
20050240744 Shaikh et al. Oct 2005 A1
20060007761 Ware et al. Jan 2006 A1
20060039174 Ware et al. Feb 2006 A1
20060056244 Ware Mar 2006 A1
20060069895 Ware et al. Mar 2006 A1
20060077731 Ware et al. Apr 2006 A1
20060129776 Ware et al. Jun 2006 A1
20070247935 Ware et al. Oct 2007 A1
20070255919 Tsem et al. Nov 2007 A1
20090063887 Ware et al. Mar 2009 A1
20090138646 Ware et al. May 2009 A1
20090251987 Macri Oct 2009 A1
20130028039 Wang Jan 2013 A1
Foreign Referenced Citations (26)
Number Date Country
0379772 Aug 1990 EP
0709786 May 1996 EP
0735492 Oct 1996 EP
0831402 Mar 1998 EP
0849685 Jun 1998 EP
0855653 Jul 1998 EP
0884732 Dec 1998 EP
08-227394 Sep 1996 JP
10-022458 Jan 1998 JP
11-007335 Jan 1999 JP
11-085345 Mar 1999 JP
11-167515 Jun 1999 JP
11-284126 Oct 1999 JP
11-328004 Nov 1999 JP
2000-035831 Feb 2000 JP
2000-174505 Jun 2000 JP
2000-243893 Sep 2000 JP
2000-284873 Oct 2000 JP
2000-348490 Dec 2000 JP
2001-027918 Jan 2001 JP
2001-044325 Feb 2001 JP
WO-1998-015897 Apr 1998 WO
WO-1999-041667 Aug 1999 WO
WO-1999-046687 Sep 1999 WO
WO-1999-050852 Oct 1999 WO
WO-2000-054164 Sep 2000 WO
Non-Patent Literature Citations (67)
Entry
U.S. Appl. No. 13/923,634, filed Jun. 21, 2013, Ware et al.
“Draft Standard for a High-Speed Memory Interface (SyncLink),” Draft 0.99 IEEE P1596.7-199X, pp. 1-56 (1996), Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society. 66 pages.
“JEDEC Standard—Double Data Rate (DDR) SDRAM Specification—JESD79”, JEDEC Solid State Technology Association, Jun. 2000, pp. 1-76. 76 Pages.
Commission Investigative Staffs' Response to Complaint's Motion for Leave to File a Reply to Commission Investigative Staffs' Response in Support of Respondents Motion for Summary Determination that U.S. Pat. No.'s 7,210,016 and 7,177,998 are invalid, dated Aug. 6, 2009, In the Matter of “Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same,” Investigation No. 337-TA-661. 16 pages.
Translation of Notice of Reasons for Rejection for Japanese Patent Application No. 2008-027486 dated Jan. 9, 2009. 9 pages.
CRISP, Richard, “Direct Rambus Technology: The New Main Memory Standard,” IEEE Micro, Nov./Dec. 1997, pp. 18-28. 11 pages.
EP Communication dated Jan. 5, 2011 for EP Application No. 10176311.8 re extended European Search Report. 9 pages.
EP Extended Search Report dated Apr. 15, 2010 re EP Application No. 10150033.8. 8 pages.
EP Extended Search Report dated Feb. 7, 2011 re EP Application No. 10175885.2. 7 pages.
EP Extended Search Report dated Jan. 5, 2011 re EP Application No. 10177771.2. 8 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 05797483.4, includes New Claims (clear copy) dated Jun. 5, 2012. 8 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 10175885.2, includes New Claims (clear copy) dated Jun. 8, 2012. 7 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 10176311.8, includes New Claims (clear copy) dated Jun. 13, 2012. 10 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 10177771.2, includes New Claims (clear copy) dated Jun. 8, 2012. 8 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 05797483.4. 8 pages.
EP Office Action dated Feb. 14, 2011 re EP Application No. 05797483.4. 6 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 10175885.2. 5 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 10176311.8. 9 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 10177771.2. 8 pages.
EP Response dated Apr. 18, 2011 regarding European Application No. 05797483.4, including remarks in response to Official Communication, new claims with highlighted amendment, and new description p. 41. 12 pages.
EP Response dated Aug. 26, 2011 to the Official Communication dated Mar. 14, 2011 and to the European Search Opinion dated Feb. 7, 2011 re EP Application No. 10175885.2-1229. 15 pages.
EP Response dated Feb. 15, 2013 to the Official Communication dated Sep. 20, 2012 in EP Application No. 05797483.4-1229. 15 pages.
EP Response dated Jul. 12, 2011 to the Official Communication dated Feb. 7, 2011 and to the European Search Opinion dated Jan. 5, 2011 for EP Application No. 10176311.8-1229. 32 pages.
EP Response dated Jul. 15, 2011 to the Official Communication dated Feb. 7, 2011 and to the European Search Opinion dated Jan. 5, 2011 re EP Application No. 10177771.2-1229. 23 pages.
EP Response dated Jun. 13, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 10176311.8-1229, Includes New Claims 1-16 (Clear and Highlighted copies). 16 pages.
EP Response dated Jun. 5, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 05797483.4-1229. 3 pages.
EP Response dated Jun. 8, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 10175885.2-1229, Includes New Claims 1-9 (Clear and Highlighted copies). 9 pages.
EP Response dated Jun. 8, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 10177771.2-1229, Includes New Claims 1-11 (Clear and Highlighted copies). 11 pages.
European Search Report and Written Opinion in EP Application No. 05022021.9, dated Jun. 1, 2006. 6 pages.
European Search Report and Written Opinion in European Patent Application 02009032.0-2212, dated Jul. 4, 2005. 9 pages.
Exhibit 26: Yang et al., “A Scalable 32Gb/s Parallel Data Transceiver with On-Chip Timing Calibration Circuits,” IEEE International Solid State Circuits Conference, pp. 258-259, 2000. 2 pages.
Gillingham et al., “SLDRAM: High Performance Open-Standard Memory,” IEEE Micro, Nov./Dec. 1997, pp. 29-39, vol. 17, No. 6, Institute of Electrical and Electronics Engineers, Inc., Los Alamitos, California. 11 pages.
Gillingham, Peter, “SLDRAM Architectural and Functional Overview,” SLDRAM Consortium, Aug. 29, 1997, pp. 1-14. 14 pages.
IBM Corp., “Application Note: Direct Rambus Memory System Overview,” Mar. 30, 1998, pp. 1-5. 6 pages.
IBM, “184 Pin DIMM Design Updates/Ramifications for Unbuffered and Registered DDR DIMMs,” JC-42.5, Dec. 1999, pp. 1-12. 13 pages.
IBM, Micron Technology and Reliance Computer Corporation, “DDR SDRAM Registered DIMM,” Design Specification, Revision 0.6, Nov. 1999. 62 pages.
IEEE Standard for Scalable Coherent Interface (SCI), “Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society,” IEEE Std. 1596-1992, Aug. 2, 1993. 270 pages.
International Preliminary Report on Patentability (Chapter 1) dated Apr. 12, 2007, re International Application No. PCT/US2005/032770. 6 pages.
International Preliminary Report on Patentability and Written Opinion in International Application No. PCT/US2005/032346, dated Mar. 29, 2007. 10 pages.
International Search Report and Written Opinion dated May 10, 2006 in International Application No. PCT/US2005/042722. 15 pages.
International Search Report and Written Opinion in International Application No. PCT/US2005/032346, Apr. 18, 2006. 11 pages.
JP Response dated Mar. 30, 2012 re JP Application No. 2009-162534. 7 pages. (Without Translation).
Kim, Y.R., “Memory Product Planning and Application,” Samsung Electronics, DDR, Today and Tomorrow, Platform Conference, Jul. 18-19, 2000. 26 pages.
Lluis Paris, et al., WP 24.3 A 800MB/S 72 Mb SLDRAM with Digitally-Calibrated DLL, 1999 IEEE International Solid-State Circuits Conference, 0-7803-5129-0/99, 10 pages.
Nakase et al., “Source-Synchronization and Timing Vernier Techniques for 1.2 GB/s SLDRAM Interface,” IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 494-501. 8 pages.
Notice of Opposition dated Apr. 8, 2008 re European Patent No. 1291778; Application No. 02009032.0; 23 pages.
Notice of Opposition dated Apr. 8, 2008, re European Patent No. 1291778 with EP Application No. 02009032.0. 24 pages.
Paris et al., “WP 24.3: A 800 MB/s 72 Mb SLDRAM with Digitally-Calibrated DLL,” ISSCC, 0-7803-5129-0/99, Slide Supplement, IEEE, 1999. 10 pages.
Poulton, John, “Signaling in High Performance Memory Systems,” IEEE Solid State Circuits Conference, slides 1-59, Feb. 1999. 30 pages.
Rambus Inc., “8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM—Preliminary Information,” Rambus Inc. Data Sheet, Mar. 1, 1996. 30 pages.
Rambus Inc., “Direct RAC Data Sheet,” Advanced Information, Last Modified Aug. 7, 1998, pp. 1-46. 46 pages.
Rambus Inc., “Direct Rambus Short Channel Layout Guide,” Version 0.8, Mar. 2000. 34 pages.
Rambus Inc., “Rambus RIMM Module (with 64/72Mb RDRAMs)” Data Sheet, Preliminary Information, Document DL0078, Version 0.90, Mar. 1999, pp. 1-11. 11 pages.
Rambus Inc., “Rambus SO-RIMM Module (with 128/144Mb RDRAMs),” Advance Information, Document DL0076, Version 0.7, Feb. 2000, p. 1-12. 12 pages.
Rambus, Inc., “Direct RDRAM 256/288-Mbit (1Mx16/18x16d),” Preliminary Information, Document DL0105, Version 1.1, Aug. 2000. 72 pages.
Rambus, Inc., “Rambus RIMM Connector,” Document DL0069, Version 1.01, Jul. 1999. 14 pages.
Samsung Electronics Inc., “KMM377S1620CT2 SDRAM Module Datasheet,” Rev. 1 (Nov. 1998), Preliminary, pp. 1-12. 12 pages.
Sato et al., “A 5-GByte/s Data-Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 653-660. 8 pages.
Seibert, Mike, “Competitive DDR Memory Sub-Systems,” Micron Technology, Inc., DRAM Memory Enabling, Platform Conference, Jul. 18-19, 2000. 67 pages.
SLDRAM Inc., “SLD4M18DR400 4 MEG X 18 SLDRAM: 400 Mb/s/pin SLDRAM 4 M x 18 SLDRAM Pipelined, Eight Bank, 2.5 V Operation,” Jul. 9, 1998. 69 pages.
SLDRAM Inc., 4M x 18 SLDRAM, Draft Advance, Jul. 9, 1998, pp. 1-69.
The Institute of Electrical and Electronics Engineers, “Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface Signaling Technology (RamLink),” Mar. 19, 1996, IEEE STD 1596.4-1996, XP002315223, pp. 12, 43-45. 5 pages.
U.S. Appl. No. 60/057,092 for “SLDRAM Architecture,” filed Aug. 27, 1997, 340 pages.
Wang et al., “A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique,” Apr. 2001, IEEE Journal of Solid-State Circuits, pp. 648-657, vol. 36, No. 4. 10 pages.
Wong et al., “Inserting Active Delay Elements to Achieve Wave Pipelining,” IEEE 1989, p. 270-273. 4 pages.
Yeung et al., “A 2.4 Gb/s/pin Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation,” IEEE Journal of Solid-State Circuits, vol. 35, No. 11, pp. 1619-1627, Nov. 2000. 10 pages.
Yoo, Changsik, “DRAM Design 3,” Samsung Electronics, High Speed DRAM Interface, Dec. 2001. 35 pages.
Related Publications (1)
Number Date Country
20220101908 A1 Mar 2022 US
Divisions (3)
Number Date Country
Parent 12757035 Apr 2010 US
Child 13228070 US
Parent 12246415 Oct 2008 US
Child 12757035 US
Parent 11746007 May 2007 US
Child 12246415 US
Continuations (11)
Number Date Country
Parent 16897157 Jun 2020 US
Child 17391521 US
Parent 16418316 May 2019 US
Child 16897157 US
Parent 15805009 Nov 2017 US
Child 16418316 US
Parent 15242425 Aug 2016 US
Child 15805009 US
Parent 14951190 Nov 2015 US
Child 15242425 US
Parent 14267446 May 2014 US
Child 14951190 US
Parent 13890801 May 2013 US
Child 14267446 US
Parent 13741255 Jan 2013 US
Child 13890801 US
Parent 13544967 Jul 2012 US
Child 13741255 US
Parent 13228070 Sep 2011 US
Child 13544967 US
Parent 10942225 Sep 2004 US
Child 11746007 US