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Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Industry
CPC
G06F13/00
This industry / category may be too specific. Please go to a parent level for more data
Parent Industries
G
PHYSICS
G06
Computing
G06F
ELECTRICAL DIGITAL DATA PROCESSING
Current Industry
G06F13/00
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Sub Industries
G06F13/10
Programme control for peripheral devices
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where the programme performs an interfacing function
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where the programme performs an input/output emulation function
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Terminal emulation
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using hardware independent of the central processor
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where hardware performs an I/O function other than control of data transfer
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where hardware is a sequential transfer control unit
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and has means for transferring I/O instructions and statuses between control unit and main processor
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for dedicated transfers to a network
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Handling requests for interconnection or transfer
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for access to memory bus
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based on arbitration
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with latency improvement
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using a concurrent pipeline structrure
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by maintaining request order
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by reordering requests
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through address comparison
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using refresh
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with request queuing
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with interleaved bank access
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in a multiprocessor architecture
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Access to multiple memories
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Access to shared memory
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Details of memory controller
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using buffers
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using bus width
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using multiple buses
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Synchronisation and timing concerns
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Configuration of memory controller to different memory types
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based on priority control
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for access to input/output bus
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using successive scanning
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with priority control
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using interrupt
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with priority control
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using burst mode transfer
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Cycle stealing DMA
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Halt processor DMA
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Multiplexed DMA
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with priority control
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using combination of interrupt and burst mode transfer
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with priority control
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for access to common bus or bus system
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with centralised access control
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using a time dependent access
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using independent requests or grants
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using a centralised polling arbiter
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with decentralised access control
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using a physical-position-dependent priority
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using a time-dependent priority
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using a self-select method with individual priority code comparator
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using a contention resolving method
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using a parallel poll method
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Information transfer
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using universal interface adapter
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for adaptation of a particular data processing system to different peripheral devices
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for adaptation of different data processing systems to different peripheral devices
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Bus structure
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Coupling between buses
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with data restructuring
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with data re-ordering
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with data-width conversion
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using switching circuits
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using bus bridges
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with arbitration
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and deadlock prevention
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with address mapping
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where the bus bridge performs an extender function
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where the bridge performs a synchronising function
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where the function is bus cycle extension
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where the synchronisation uses buffers
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Device-to-bus coupling
G06F13/4068
Electrical coupling
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Drivers or receivers
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Precharging or discharging
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Live connection to bus
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Bus impedance matching
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Mechanical coupling
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in incremental bus architectures
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Bus transfer protocol
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on a parallel bus
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being a system bus
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with asynchronous protocol
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with synchronous protocol
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being an input/output bus
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with asynchronous protocol
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with synchronous protocol
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being a memory bus
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with asynchronous protocol
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with synchronous protocol
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on a daisy chain bus
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using a handshaking protocol
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using a clocked protocol
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using an embedded synchronisation
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on a point to point bus
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using a handshaking protocol
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using a clocked protocol
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using an embedded synchronisation
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on a serial bus
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using a handshaking protocol
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using a clocked protocol
G06F13/4295
using an embedded synchronisation
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