Patent Grant
12120880
This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Memory Circuit (3D-Memory) devices and fabrication methods.
Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes such as lateral and vertical dimensions within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality.
However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low.
There are many techniques to construct 3D stacked integrated circuits or chips including:
In a land mark papers at VLSI 2007 and IEDM 2007, Toshiba presented techniques to construct 3D memories which they called-BiCS. Many of the memory vendors followed that work by variation and alternatives mostly for non-volatile memory applications, such as now being referred to as 3D-NAND. They provide an important manufacturing advantage of being able to utilize one, usually ‘critical’, lithography step for the patterning of multiple layers. The vast majority of these 3D Memory schemes use poly-silicon for the active memory cell channel which suffers from higher cell to cell performance variations and lower drive than a cell with a monocrystalline channel. In at least our U.S. Pat. Nos. 8,026,521, 8,114,757, 8,687,399, 8,379,458, and 8,902,663, these are incorporated herein by reference; we presented multiple 3D memory structures generally constructed by successive layer transfers using ion cut techniques. In this work we are presenting multiple methods and structures to construct 3D memory with monocrystalline channels constructed by alternative methods to ion cut and successive layer transfers. This structure provides the benefit of multiple layers being processed by one lithography step with many of the benefits of a monocrystalline channel, and provides overall lower construction costs.
In addition, the entire contents of U.S. Pat. Nos. 11,233,069, 11,114,464, 10,847,540, 10,418,369, 10,014,318, U.S. patent application publication 2020/0013800 and U.S. patent application Ser. No. 17/524,737, 62/307,568, 62/286,362, 62/276,953, 62/271,251, 62/266,610, and 62/246,054, the entire contents of the foregoing patents, publications, and applications are incorporated herein by reference.
The invention may be directed to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods.
In one aspect, a 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the first level includes at least one voltage regulator circuit.
In another aspect, a 3D device, the device including: a first level including logic circuits; and a second level including a plurality of memory cells, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the logic circuits include at least one power down control circuit.
In another aspect, a 3D device, the device including: a first level including logic circuits; and a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the logic circuits include a plurality of antifuse structures.
In another aspect, a 3D device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a third metal layer overlaying the second metal layer, a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by at least four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the memory control circuit includes at least one digital to analog converter circuit.
In another aspect, a 3D device, the device including: a first level including a single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer, a third metal layer overlaying the second metal layer, a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the at least four memory mini arrays includes at least four rows by at least four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the memory control circuit includes at least one cache memory circuit.
In another aspect, a 3D device, the device including: a first level including a single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a third metal layer overlaying the second metal layer, a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the at least four memory mini arrays includes at least four rows by at least four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the memory control circuit includes at least one logic counter circuit.
In another aspect, a 3D device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer, a third metal layer overlaying the second metal layer, a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the memory control circuit includes at least one Look Up Table circuit (“LUT”).
In another aspect, a 3D device, the device including: a first level including a single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a third metal layer overlaying the second metal layer, a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the at least four memory mini arrays includes at least four rows by at least four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the first level includes at least one in-out interface control circuit.
In another aspect, a 3D device, the device including: a first level including a single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a third metal layer overlaying the second metal layer, a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the at least four memory mini arrays includes at least four rows by at least four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the memory control circuit includes a memory refresh circuit.
A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a plurality of second transistors disposed atop the third metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, and where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors; and a connection path from the fourth metal to the third metal, where the connection path includes a via disposed through the memory array, and where the memory control circuit includes at least one power down control circuit.
A 3D semiconductor device, the device including: a first level including a single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the at least four memory mini arrays includes at least four rows by at least four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where at least one of the plurality of second transistors includes a structure deposited using Atomic Level Deposition (“ALD”), where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the first level includes at least one differential read circuit.
A 3D semiconductor device, the device including: a first level including a single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a plurality of second transistors disposed atop the third metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; a memory array including word-lines; and an upper level disposed atop the fourth metal layer, where the upper level includes a mono-crystalline silicon layer, where the memory array includes at least four memory mini arrays, where each of the at least four memory mini arrays includes at least four rows by at least four columns of memory cells, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors or at least one of the plurality of third transistors, and where the memory control circuit includes at least one error correcting circuit.
Various embodiments of the invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
An embodiment or embodiments of the invention are now described with reference to the drawing figures. Persons of ordinary skill in the art will appreciate that the description and figures illustrate rather than limit the invention and that in general the figures are not drawn to scale for clarity of presentation. Such skilled persons will also realize that many more embodiments are possible by applying the inventive principles contained herein and that such embodiments fall within the scope of the invention which is not to be limited except by the appended claims.
Some drawing figures may describe process flows for building devices. The process flows, which may be a sequence of steps for building a device, may have many structures, numerals and labels that may be common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step's figure may have been described in the previous steps'
Memory architectures include at least two important types—NAND and NOR. The NAND architecture provides higher densities as the transistors forming the memory cells are serially connected with only an external connection at the beginning and end of the cell string as is illustrated in at least U.S. Pat. No. 8,114,757, FIGS. 37A-37G. NOR architectures are less dense but provide faster access and could work sometimes when the NAND architecture cannot as individual NOR memory cells are directly accessible and in many cases both its source and drain are accessible, such as being illustrated in at least U.S. Pat. No. 8,114,757, FIGS. 30A-30M.
The memory cell could be constructed with conventional N type or P type transistors where the channel doping may be of opposite type with respect to the source drain doping or the memory cell could utilize a junction-less transistor construction where the gate could fully deplete the channel when in the off-state. For some architectures, the junction-less transistor is attractive as it may take less processing steps (or provide other device advantages such as low leakage off-state) to form the memory array without the need to form a change in doping along the transistor.
Some 3D Memory architectures are utilizing a horizontal memory transistor, for example, such as illustrated in at least U.S. Pat. No. 8,114,757, at least FIGS. 37A-37G and FIGS. 30A-30M. Others may use vertical memory transistors, for example, such as in the Toshiba BiCS architecture such as illustrated in at least U.S. Pat. No. 7,852,675.
Multiple methods to construct 3D memory structures using horizontal junction-less transistors for a NAND architecture, and for horizontal NAND and NOR architectures in general may be found in, for example, such as U.S. Pat. No. 8,114,757 in at least FIG. 33 and FIG. 37. The following would present multiple techniques to form a multilayer silicon over oxide start structure equivalent to, for example, such as at least FIGS. 33D and 37D (of U.S. Pat. No. 8,114,757), without the use of ion-cut layer transfer.
The starting structure could be similar to FIG. 41A of U.S. application Ser. No. 14/642,724, incorporated herein by reference, as illustrated in
Then, by utilizing anodizing processes, thick crystalline layer 120 may be converted to a multilayer of alternating low porosity over high porosity as illustrated in
The number of alternating layers included in multilayer structure 122 could be made as high as the number of layers needed for the 3D memory (for example, greater than 20, greater than 40, greater than 60, or greater than 100) or for the transferring of a subset of multilayer structures one on top of the other to form the desired final structure. The porosity modulation could be achieved, for example, by (1) alternating the anodizing current, or (2) changing the illumination of the silicon structure while in the anodizing process, or (3) by first alternating the doping as layer 120 is being grown through epitaxial process, or (4) etching & oxidizing multilayers of SiXGe1-X/Si. Layer 144 could be the portion of layer 120 which is left un-processed by the modulated-porosity process. Below are listed few embodiments of the above method of forming a c-Si/SiO2 multilayer from an alternated porosity multilayer;
For example, U.S. Pat. No. 7,772,096, incorporated herein by reference, teaches the formation of a multilayer structure according to (3) above, starting with alternate doping following these steps:
The above processing may result in first desired multilayer structure 122 or second desired multilayer structure 124 for the formation of 3D memories.
In yet another embodiment of method (3), U.S. patent application Ser. No. 12/436,249, incorporated herein by reference, teaches an alternative method for the formation of the multilayer structure 122 with alternating doping. In brief, the method starts by multiple depositions of amorphous silicon with alternating doping, then performing a solid phase recrystallization to convert the stack into a stack of p-type doped single crystal Si-containing layers using a high temperature recrystallization, with recrystallization temperatures from 550° C. to 700° C. After recrystallization, the single crystal Si-containing layers could be subjected to anodization and so forth as presented in ii-iv above. U.S. patent application Ser. No. 12/436,249 teaches a few alternatives for the formation of the alternating doping layer structure which could be employed herein for the 3D memory multilayer structure formation.
In an embodiment of method (2), the epitaxial layer 120 could include alternating n doped and n+ doped layers. The porous formation of the n doped layers may be assisted by light to form the holes for the anodizing process to effectively work as had been presented in S. Frohnhoff et. al., Thin Solid Films, in press (1994), U.S. patent application Ser. Nos. 10/674,648, 11/038,500, 12/436,249 and US patent 7, 772,096, all of these incorporated herein by reference. Following the anodizing step the structure could be oxidized and then annealed as presented in steps iii and iv above.
In an embodiment of method (1), A method to form alternating layers of coarse and fine porous layers is by alternating the anodizing current similar to the description in “Porous silicon multilayer structures: A photonic band gap analysis” by J. E. Lugo et al J. Appl. Phys. 91, 4966 (2002), U.S. Pat. No. 7,560,018, U.S. patent application Ser. No. 10/344,153, European patent EP0979994, and “Photonic band gaps analysis of Thue-Morse multilayers made of porous silicon” by L. Moretti et al, 26 Jun. 2006/Vol. 14, No. 13 OPTICS EXPRESS, all of these incorporated herein by reference. Following the anodizing step the structure could be oxidized and then annealed as presented in steps iii and iv above.
The anodizing step could be done as a single wafer process or by using a batch mode as illustrated in U.S. Pat. No. 8,906,218, incorporated herein by reference and other similar patents assigned to a company called Solexel.
In yet another embodiment combining methods (3) and (2), the multilayer structure 122 may be formed by first forming multilayer structure of alternating n type over p type. Such a method is illustrated in U.S. Pat. No. 8,470,689 and in “Silicon millefeuille”: From a silicon wafer to multiple thin crystalline films in a single step” by D. Hernandez et al., Applied Physics Letters 102, 172102 (2013); incorporated herein by reference. These methods leverage the fact that n type silicon would not become porous without light while p type silicon would only need current for the anodizing process to take place. For these methods the multilayer of n over p could be first etched to form the multilayer pattern such as is illustrated in FIG. 31E or FIG. 37E of U.S. Pat. No. 8,114,757 followed by an anodizing process to convert the p type silicon to porous while leaving the n type solid and un-etched. Then the step of oxidation iii. could be used to convert the porous layer to an isolation layer. The annealing step iv. could be made short or skipped as the n layers might be very lightly etched or not be etched at all.
In yet another embodiment of method (3), a multilayer structure could be achieved by successive epitaxial growths of n type silicon over p+ type silicon multiple times for which the n silicon could be etched at a much higher rate than the p+ silicon. In a paper titled: “Fabrication of conducting GeSi/Si micro and nanotubes and helical microcoils” by S V Golod, V Ya Prinz, V I Mashanov and A K Gutakovsky, Semicond. Sci. Technol. 16 (2001) 181-185, incorporated herein by reference, it presents that p+ silicon would be etched at a much lower rate than n silicon, quoting: “As a selective etchant, an ammonium hydroxide-water solution can be used. It was shown in [8] that the 3.7 wt. % NH4OH solution has a pp+ selectivity of approximately 8000:1 at 75° C. and boron concentration p+=1020 cm−3.”
Another alternative is to form multilayers of silicon over Si1-XGeX as illustrated in “New class of Si-based superlattices: Alternating layers of crystalline Si and porous amorphous S1-XGeX alloys” by R. W. Fathauer et al., Appl. Phys. Lett. 61 (19), 9 Nov. 1992, incorporated herein by reference. In such a multilayer structure there is high degree of selectivity in etching Si1-XGeX layers over Si layers. This may be followed by oxidation such as step iii. and anneal iv. could provide multilayers of silicon over oxide. In a paper titled: “Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)” by Se Hwan Park et al, IEICE Transactions on Electronics. 05/2012, incorporated herein by reference, it presents the use of multilayers of silicon over Si1-XGeX for forming a 3D NAND device. While many of the 3D memories presented are 3D RAM and 3D ReRAM, the multilayer structure presented herein are useful for 3D NAND type memory as was presented in this paper and in many of process flow presented in the incorporated here in patents such as in U.S. Pat. No. 8,581,349 as related to FIG. 37A-37G, incorporated herein by reference.
An alternative method to the modulated-porosity method for forming c-Si/SiO2 multilayers may be to utilize the Bosch process. In a paper titled “Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays” by Davide Sacchetto et al. at IEEE SDDR09, incorporated herein by reference, a technique used for deep hole etch has been applied to form structures of crystalline lines one on top of the other each with oxide all around. Similar techniques could be used to form the base structure for 3D memory.
Yet another alternative for forming c-Si/SiO2 multilayer structures is direct epitaxy of silicon, special oxide, and silicon again. The special oxide is a rare-earth oxide which if deposited properly would keep the crystal structure of the silicon to allow crystalline silicon on top of it as presented in U.S. patent application publication US 2014/0291752, incorporated herein by reference.
An interesting aspect of the multilayer structure that are epitaxial based rather than the layer transfer approach is that the whole structure in most cases would resemble one monolithic crystal, in which the crystal repeating element which could be a silicon atom or other molecules are very well aligned across layers. No molecular level alignment would happen in layer transfer process. So in an epitaxial process of multilayer formation the molecules forming the multilayer structure are all aligned forming lines that are parallel at better than 0.01 of degree while in layer transfer base multilayer structure between layers the molecules line would have in most case a misalignment greater than 0.1 degree. As well, in an epitaxial process of multilayer formation the molecules forming the multilayer structure from one layer to the next are aligned less than within half an atomic or molecule distance.
The epitaxy process of multilayers of an n+ type layer over a p type layer could be done at lower temperatures to reduce the dopant movement of the n+ layer, at the lower portion of the multilayer structure, into the p type layer as the multilayer structure is being formed. There are known epitaxial processes in the art which allow good quality layers to be formed while keeping the process temperature below 600° C. For example, such has been presented in papers by D. SHAHRJERDI, titled “Low-Temperature Epitaxy of Compressively Strained Silicon Directly on Silicon Substrates” published at Journal of ELECTRONIC MATERIALS, Vol. 41, No. 3, 2012; by S. Wirths titled “Low temperature RPCVD epitaxial growth of Si1_xGex using Si2H6 and Ge2H6” published at Solid-State Electronics 83 (2013) 2-9”; and by Pere Roca I Cabarrocas titled “Low temperature plasma deposition of silicon thin films: From amorphous to crystalline” published at Journal of Non-Crystalline Solids, Elsevier, 2012, 358 (17), pp. 2000-2003; and in U.S. Pat. Nos. 7,262,116, 8,778,811 and application US 2014/0045324, all of the forgoing incorporated herein by reference.
An advantage of using oxidized porous silicon for isolating the silicon layers for the 3D memory structure is the ability to easily and selectively etch portions of these oxidized porous layers to allow the gate formation to have a larger coverage of the transistor channel to have an increased control on the memory transistor, for example, such as with gate all around or a ‘mostly’ gate all around transistor structure. In a similar way in the other forms of multilayer structure the area on top and under the channel could be etched so in the follow-on processing step of oxide and gate formation it would form a larger coverage of the channel which could be a gate all around configuration for better channel control.
Base wafers or substrates, or acceptor wafers or substrates, or target wafers substrates herein may be substantially comprised of a crystalline material, for example, mono-crystalline silicon or germanium, or may be an engineered substrate/wafer such as, for example, an SOI (Silicon on Insulator) wafer or GeOI (Germanium on Insulator) substrate. Similarly, donor wafers herein may be substantially comprised of a crystalline material and may include, for example, mono-crystalline silicon or germanium, or may be an engineered substrate/wafer such as, for example, an SOI (Silicon on Insulator) wafer or GeOI (Germanium on Insulator) substrate, depending on design and process flow choices.
In general the described memory structure would be arranged as a process flow forming a type of a 3D memory structure. These flows could be considered as a Lego part which could be mixed in different ways forming other variations, thus forming many types of devices. Some of these variations will be presented but as with Lego there too many variations to describe all of them. It is appreciated that artisan in the art could use these elements of process and architecture to construct other variations utilizing the teaching provided herein.
Many of these memory structures are constructed starting with multilayer of mono-crystal layers as illustrated in
A volatile 3D memory using floating body charge is described in U.S. Pat. No. 8,114,757, incorporated herein by reference, as related to at least FIGS. 30A-30M and FIGS. 31A-31K. The following is an additional alternative for forming a 3D DRAM volatile memory.
3D Memory may be multi-layers of 2D memory in which memory cells are placed as a matrix with rows and columns. These memory cells are controlled by memory control lines such as bit-lines, source-lines, and word-lines, usually in a perpendicular arrangement, so that by selecting a specific bit-line and specific word-line one may select a specific memory cell to write to or read from. In a 3D memory matrix, having three dimensions, selecting a specific memory cell requires the selecting of the specific layer which could be done by additional memory control lines such as select-lines. As been presented herein, some of the select lines could be integrated in the semiconductor layer in which the memory devices are built into (for example,
Another alternative that would not require changes in the device structure presented is to use what could be called ‘self refresh’. In a common DRAM refresh, a refresh cycle means that each cell is being read and re-written individually. In ‘self refresh’ many or even all cells could be refreshed together by driving a specific current (may be a current range or minimum current) through them. The cell holding ‘zero’ will keep its zero state and the cell holding ‘one’ will get recharged to recover their lost of floating body charge due to leakage. This technique had been detailed in a paper by Takashi Ohsawa et. al. in paper titled: “Autonomous Refresh of Floating Body Cell (FBC)” published in IEDM 2008, and in follow up paper titled: “Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization” published by IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 10, OCTOBER 2009, and U.S. Pat. Nos. 8,194,487 and 8,446,794, all of the foregoing are incorporated herein by reference.
Another type of memory is resistive-memory (“ReRAM”) which is a non-volatile memory type. A 3D ReRAM has been described in U.S. Pat. No. 9,117,749, incorporated herein by reference. In general, ReRAM perform the memory function by having the resistivity change which could be achieved by driving current through the ReRAM variable resistivity medium and could be sense by measuring current or voltage through that medium. There are many types of materials that could be used for ReRAM and some of those are oxides with additional materials which could be driven into the oxide to change it resistivity. U.S. Pat. No. 8,390,326 incorporated herein by reference present the use of silicon oxide for such use. A subclass of the ReRAM are structure that allow only one time programing (“OTP”) of these mediums such as presented in U.S. Pat. No. 8,330,189 incorporated herein by reference.
A form of T-RAM cell has been described in a paper by Ahmad Z. Badwan et. al. titled “SOI Field-Effect Diode DRAM Cell: Design and Operation” published in IEEE Electron Device Letters, Vol. 34, No. 8 Aug. 2013, incorporated herein by reference. The T-RAM structured presented here and the method to process them could be adapted to build FED (Field-Effect Diode) structure and to form a 3D-FED RAM device.
A volatile 3D memory using floating body charge is described in U.S. Pat. No. 8,114,757, incorporated herein by reference, as related to at least FIGS. 30A-30M and FIGS. 31A-31K. The following is an additional alternative for forming a 3D DRAM volatile memory.
3D Memory may be multi-layers of 2D memory in which memory cells are placed as a matrix with rows and columns. These memory cells are controlled by memory control lines such as bit-lines, source-lines, and word-lines, usually in a perpendicular arrangement, so that by selecting a specific bit-line and specific word-line one may select a specific memory cell to write to or read from. In a 3D memory matrix, having three dimensions, selecting a specific memory cell requires the selecting of the specific layer which could be done by additional memory control lines such as select-lines. As been presented herein, some of the select lines could be integrated in the semiconductor layer in which the memory devices are built into (for example,
The illustrations in
In U.S. Pat. No. 8,902,663, incorporated herein by reference; a select transistor is presented at the upper layer of a 3D memory cell column as presented in respect to
This new type of 3D memories could be constructed to achieve significant advantage over the prior art by utilizing the 3D architecture as illustrated in at least
As was discussed in respect to
In most cases the volatile operation could interfere with the non-volatile operation of the memory cells. So it is common to avoid using them together, and to have the unused portion electrically reset to reduce interference with the used portion.
There are many use modes which such enhanced memory could be used including, splitting the memory bank for volatile and non-volatile portions, power down with saving the volatile information into the non-volatile portion, and reduce sleep power by moving the volatile information into the non volatile portion. For some of these use modes the 3D structures presented in here with control circuits on top and/or on the bottom—
Central controller 630 commanding and controlling these operations for sleep mode recovery mode etc.
In-Out interface controller to interface with data and with the device controller 601.
Sense Amplifiers 620 to sense the data of a memory cell according to the mode of operation and to convert side memory control circuits 601 to a digital bit which could be temporarily stored in the unit memory cash 634.
Signal generators 618 to generate the required voltages and current for the proper read write of the memory cells. Some of these circuitry, such as charge pumps, could be shared by all units and be placed in side memory control circuits 601.
Blocks 612, 614, 616, 617 for the various control lines such as bit-lines, word-lines, gate-lines, select lines etc. The layer decoders 616 might be removed from the unit 604 into the general per-layer circuits at side memory control circuits 601.
Additional advantage for such memory architecture is the potential ability to move in and out very large blocks of data as many blocks 602 could be accessed in parallel. If only a single per-layer stair case is used for maximum array efficiency than the parallel action would be limited to single layer at a time. For many applications this could be managed by proper system data structure and control.
Such 3D Memory could include redundancy circuitry to allow repair of control functions as well as replacement of faulty memory bits. The architecture of
The memory control redundancy could be applied to any of the 3D memories herein.
Another embodiment of monolithic 3D memory according to the present invention is demonstrated in
For example the composition of the S/D layers 702 could be N+ silicon while the channel layers 704 could be P type silicon and the selective etch process would utilize anodic etching as detailed in U.S. Pat. No. 8,470,689 and as was described herein.
An alternative is to use P++ silicon for the S/D layers 702 and N silicon for channel layers 704 and the later selective etch would utilize the NH4OH solution as taught by Golod et al.
Yet another alternative is to use N+ silicon for the (S/D) layers 702 and P type SiGe for channel layers 704 and the later selective etch would utilize the process taught by Se Hwan Park et al in a piper titled “Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)” published in TECHNICAL REPORT OF IEICE in 711 (APWF_PSH), a paper by FL W. Fathauer et al titled “New class of Si-based superlattices: Alternating layers of crystalline Si and porous amorphous Si, -, Ge, alloys” published by Appl. Phys. Lett. 61 (19), 9 Nov. 1992, a paper by Jang-GnYun titled “Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory” published at IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL2011 and U.S. Pat. No. 8,501,609 all incorporated herein by reference.
For simplicity we shall outline the flow for a vertical channel 3D memory structure including S/D layers 702 as N+ silicon and P type silicon for channel layers 704. A person skilled in the art would be able to modify the flow for other alternative embodiments.
On top of the multilayer of alternating 702/704 a hard mask material 706 is deposited.
In this 3D memory structure, and also in most other memory structures herein, the horizontal per layer line through the matrix could be the limiting factor of the power performance of the device with respect to how long it could be made. On the other hand the area required for the stair-case interconnect structure dictates longer lines to save in silicon real-estate and reduce cost per bit. A preferred design might place such stair-case on both sides of the line which could help reduce cell to cell variation in addition to improving power and delay. If the device is fractured into multiple blocks real estate efficiency can be improved by sharing each stair case between both the right and the left sides of each block.
An alternative technique for selective removal of the P type material regions between channels while not etching the channel regions and the N type S/D lines is to use an anodizing process which would etch the P regions between channels to convert them to porous regions. The anodizing wet etching is highly selective and would not affect the N type S/D lines, especially if the process is done in dark as previously discussed such as in U.S. Pat. No. 8,470,689. For further enhancement of this anodizing porous formation the S/D lines could be used to deliver the anodizing current throughout various regions of the structure. An additional enhancement could be added by using positive voltage on substantially all of gates 804 conductors. Such positive voltage on the gates will further deplete the channels blocking the anodizing etch for the channel region while the entire P region in between are etched and become porous. The selected voltages for efficient selective anodization will depend on engineering considerations, for example, the type of the body, and doping concentrations.
In another alternative the above process of anodizing could be extended to achieve further an all-layer anodization under the ridge structure to support a following step of transferring the complete 3D NOR structure to another wafer cutting the formed porous layer underneath. The all-layer cut porous formation could alternatively be formed after the step of the second formation of O/N/O layer as illustrated in
The ridge control may be constructed by first removing the channel material at the region designated for ridge control. Then the select gate transistors are formed on the S/D line as outlined above. The select gate transistors may be designed to function as junction less transistors or as gate all around nano-wires. In some cases it might be desired to thin the S/D lines in the region designated as junction less transistor or nano-wire to achieve better gate control. Such thinning would narrow these regions to about 20 nm thickness or about 15 nm or about 10 nm.
The architecture referred to by naming as 3D NOR and illustrated herein in reference to
Additional enhancement to such 3D NOR is to break the gate control to two independent side gates—left gates and right gates, as shown in
These two gate control lines can be placed on the top connection layer side by side as illustrated in
Additional enhancement to such 3D NOR is to implement MirrorBit® technology as was produced commercially by Spansion for NOR products.
These two enhancements could be combined to allow ‘4 bit per cell’ as is illustrated in
Another known enhancement is to control the amount of charge being stored in a cell to allow multi-level voltages per cell, hence coding more than 1 bit per cell. These different enhancement techniques could be combined to achieve even higher number of bits per cell. Accordingly if each corner is designed to hold 4 levels then the cell could store 16 bits. If more levels are managed at each corner than the storage capacity of a cell could be even higher.
The general approach to select and access a specific bit could be as follows:
Additional alternative is to add side gates to the other facet of the 3D NOR channels. So starting from the structure illustrated in
The move from a memory cell with two facet of gated control charged trap surfaces to a memory cell with four facets of gated control charged trap surfaces would allow a doubling of the memory cell storage capacity. Moreover, a smart control leveraging these multiple gate memory cells could enable a far larger increase in per cell storage capacity as will be described in the following.
This multilevel technique could apply to the following higher bit sites per facet scheme just as well.
To further illustrates the 4-Gate 3D NOR operation a table for the operating mode is provided. The memory channel has one facet facing and connecting to the top S/D line (S/Dtop) and one to the bottom S/D line (S/Dbottom), it has four gate controlled facet. For the facet the table is referring the gate controlling that facet would be called C-Gate, the supporting gate on its right side would be called R-Gate, and the one on its left L-Gate. The table suggests specific voltages but those could be consider relative values, based upon design and engineering considerations. The voltage to perform write into the charge traps is called 8v and accordingly the erase is −8V. Values such as 2v, 4v and 6v are high enough to direct the charge but not high enough to cause significant charge trapping.
Engineering the memory peripheral circuits for the memory matrix including the circuits to generate the required signals for the memory control lines and the sense circuits to sense the memory content is a well-practiced memory engineering task. The memory structure presented herein adds some less common variation as a word-line controlling a gate may function as a R-Gate or as C-Gate or as L-Gate depend on the specific channel currently in action. In the following we review the high level architecture for such a memory control circuit.
The discussion would be for one of the many alternative architecture options—of an 8 bit per facet as illustrated in
As an alternative the gate control lines of the cells adjacent to a channel which is being written to or read from could be put into negative voltage such as −4v to disable these adjacent channels. So for example if in reference to
The reference signal generator 2528 provides the required signals to operate the read write operations. All the voltages suggested herein are suggested voltages for some conceptual 3D-NOR. These signal levels could be adjusted for specific designs based on the choice of materials, process flow, layer thicknesses, and feature sizes.
Another known enhancement technique is to control the amount of charge being trapped in a cell to allow coding of more than 1 bit based on the amount of charge. These different enhancement techniques could be combined to achieve an even higher number of bits per cell. Current charge trap memories are known to achieve 3 bits or 8 levels per cell. A white paper titled “MirrorBit® Quad Technology: The First 4-bit-per-cell Flash Memory Spansion™ MirrorBit Quad Technology to Expand Flash Memory Innovation for Electronic Devices” was published by Spansion—www.spansion, Doc. 43704A (SEPTEMBER 2006), incorporated herein by reference. The paper shows the use of MirrorBit in which every bit site could be programmed to one of 4 levels representing 2 bits, providing in total 4 bits per cell. Adapting such to the HD-NOR could result with 54 bits per cell non-volatile memory structure. And the structure could be organized to have some of the memory used as fast access FB-RAM for which a self-refresh mode could be added. In addition, known techniques such as Probabilistic error correction in multi-bit-per-cell flash memory as described in U.S. Pat. No. 8,966,342, incorporated herein by reference, could be integrated for increased robustness of such memory operations.
This architecture could also support additional modes of operation. The structure could be designed to allow independent access to 8 blocks provided none of them share the Peripherals circuits. It could designed to support synchronized access of up to 8 units sharing the same row or sharing the same column and or the same layer, reducing access power and still provides multiple bits.
It could be designed to support on chip transfer from the non-volatile portion to the high speed FB-RAM portion or the other way. Such transfer could be done in parallel to or from 8 blocks reducing time and power for such transfer. Such capabilities could allow high speed access with a low power operating mode. So data is transferred to FB-DRAM designated block for fast access but could stored back into the NOR NV section for sleep or power down.
The corners Clt, Crt, Clb, Crb could be used for device top level control for the operating mode, to generate the special voltage source required for read and write, and for interface to external devices.
In general memory design it is common to use partitioning which utilizes powers of 2 numbers such as: 4, 8, 16, 32, 64, . . . . Such work well with decoding and addressing. Yet,
Alternatively 3 layers could be used to form the 18 memory sites of which 16 would be used. Or 11 layers to form 66 sites of which 64 could be used reducing further the unused memory sites, which could also be used as redundancy for repair of defective sites with proper look up table in the control circuits.
The three gates control of the charge trap layers of this 3D-NOR as illustrated in
This distributed form of storage could help reduce the sensitivity to local defect and increase the overall memory capacity.
For this distributed memory storage technique the Orthonormal basis signal processing techniques of linear algebra could be deployed. Quoting: Orthonormal Basis: A subset {v1, . . . , vk} of a vector space V, with the inner product ,
, is called orthonormal if
vi, vj=
=0 when i≠j. That is, the vectors are mutually perpendicular. Moreover, they are all required to have length one:
vi, vi
=1.
There many such basis and there in signal processing has been extensively studied in the art. A subset of these are called wavelets as been described in article by G. BEYLKIN titled: “ON THE REPRESENTATION OF OPERATORS IN BASES OF COMPACTLY SUPPORTED WAVELETS” published SIAM J. NUMER. ANAL. c 1992 Society for Industrial and Applied Mathematics Vol. 6, No. 6, pp. 1716-1740, December 1992 011, incorporated herein by reference.
With Orthonormal set of vectors every ‘bit site’ could be represented by one of these vectors. So for n bits we would have n vectors. Writing a bit would be like adding a vector to the charge trap surface by scanning along the channel and modulating the amount stored according to the vector. Reading would be the inverse which could be the effect of multiplying the stored values by the reading vector. Accordingly if the vector was stored the value of the reading would be ‘1’ and if it was not than it would be ‘0’. The vector itself could be multiplied by a scalar which would represent multilevel per vector.
Additional information on wavelets and related decomposition and reconstruction algorithms may be found in “Fundamentals of Wavelets Theory, Algorithms, and Applications,” Goswami, J., C., et al., 2nd Ed., JWiley & Sons, 2010, especially chapters 6 and 7, the entire book is incorporated herein by reference. Orthonormal wavelets such as, for example, of Shannon (sine radians sampling), Meyer (smoothing of Shannon), Battle-Lemarié, and Daubechics may be utilized depending on engineering choices and optimizations. Biorthogonal wavelets, for example, of Cohen, Daubechies, and Feaveau, may be useful depending on engineering choices and optimizations. Moreover, additional information on wavelets may be found in B. Vidakovic, et al., “Wavelets for Kids, A Tutorial Introduction,” 1994 Duke University, incorporated herein by reference.
An alternative peripheral circuits including block diagrams will now be presented for the 3D-NOR fabric such as is illustrated in
The L0-1 address would indicate the level of charge stored or read from the selected bit. Changing stored levels could be achieved by additional write voltage levels such as, for example, 10 volts, 11 volts, 12 volts, etc. (adjusted to the device technology employed) or by modulating the writing/reading time or combination of these. The Gate Signal Forming Unit 3402 could include the corresponding circuits to implement the bit levels.
The four centralized signals (GSr, GU, GSl, Gd) are forming a bus like signals for the word-lines available to be selected for the selected channel column gates. Unit 3450 could include the buffers and drive electronics. These are designed according to system considerations such as access time, power and so forth. The Row Address lines R0-k and their complementary signals could be delivered as another bus-like signals. For each channel a large fan-in NAND gate could be used with decoding like connection to the Row address so NAND 3430 is activated to “0” only once the Row address is addressing channel ‘n’ (respectively NAND 3429 is activated to “0” only once the Row address is addressing channel ‘n−1’). For each channel there is also a dedicated selector block—for ‘n−1’ selector block 3439, for ‘n’ selector block 3440, and for ‘n+1’ selector block 3441. Each selector block has three selectors, two are one-of-two selectors M2, and one is one-of-three selectors M3. These selectors could use a full transmission gate or other switching type circuits.
For the case when channel ‘n’ is addressed, NAND 3430 is activated and accordingly the selector M3 of 3440 would select GSl signal to drive gate line related to West gate such as WL1-Wn, the first M2 selector of 3440 would select Gu signal to drive gate line related to the North gate such as WL2-Nn, the second M2 selector of 3440 would select Gd signal to drive gate line related to South gate such as WL3-Sn, and selector M3 of 3441 would select GSr signal to drive gate line related to the West gate of the n+1 column channel which could be the East gate of the n channel column WL4-Wn+1. All non-activated selectors (M2, M3) will output “0”, or may be left floating in some configuration, which will prevent their respective channel to be affected or affect the memory operations. Accordingly providing the proper signal to perform the desired operation to the addressed bit within the addressed facet on the addressed channel.
In a similar architecture the peripherals circuit for driving the bit-lines—the S/D lines could be made. For simplicity the following peripherals circuits are to support the bit-lines—BL1, BL2, BL3, . . . —for the structure illustrated in
The L0-1 address would indicate the level of charge stored or read from the selected bit, this optional input for the case S/D lines may be used for the level modulation.
The two centralized signals (SDn, SDn+1) are forming bus-like signals for the bit-lines available to be selected for the selected column. Unit 3550 could include the buffers and drive electronics. These are designed according to system consideration such as access time, power and so forth. The layer Address lines Co. and their complementary signals could be delivered as another bus like signals. For each layer a large fan-in NAND gate could be used with decoding such as connection to the layer address so NAND 3530 is activated to “0” only once the layer address is addressing layer ‘n’ (respectively NAND 3529 is activated to “0” only once the layer address is addressing layer ‘n−1’). For each layer there is also a dedicated selector block—for ‘n−1’ selector block 3539, for ‘n’ selector block 3540, and for ‘n+1’ selector block 3541. Each selector block has one-of-three selector M3. These selectors could use a full transmission gate or other switching type circuits.
For the case when column ‘n’ is addressed NAND 3530 may be activated and accordingly the selector M3 of 3540 would select SDn signal to drive bit-line to S/Dn at 3520 related such as BL1, and selector M3 of 3541 would select SDn+1 signal to drive bit line related to S/Dn+1 such as BL2. All non-activated selectors (M3) will output “0”, or may be left floating in some configuration, which will prevent their respected channel to be affected or affect the memory operations. Accordingly providing the proper signal to perform the desired operation to the addressed bit within the addressed facet on the addressed channel.
In some configurations the M3 selector could be constructed to select between two active signals or leave the output floating which will render that line in-active.
The units Voltage Source Circuits 3404 and/or 3504 could be designed to provide the proper signals as was described herein for the word-line, bit-line operations of the 3D-NOR memory including such that were described in respect to
The O/N/O stacks within the 3D NOR fabric could be designed independently; for example, the facet(s) related to/under the first gates and the facet(s) related to/under the second gates could be different in many ways. It could include the same materials with different thickness or different materials. Some of such O/N/O stack materials have been presented in paper by Chun Zhao titled “Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm” published at Materials 2014, 7, 5117-5145; doi:10.3390/ma7075117, incorporated herein by reference. The O/N/O stack could include band gap engineering for better performance. Such band gape engineering has been described in papers such as by Dong Hua Li et al. titled “Effects of Equivalent Oxide Thickness on Bandgap-Engineered SONOS Flash Memory” published at the 2009 IEEE Nanotechnology Materials and Devices Conference Jun. 2-5, 2009, and by Hang-Ting Luc et al. titled “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability” published at IEDM 2005. And in patents such as U.S. Pat. Nos. 7,414,889, 7,512,016 and 7,839,696 all of the forgoing are incorporated herein by reference.
In the 3D NOR architecture such as is illustrated in at least
Radical oxidation could be used for the formation of a high quality oxide such as for the formation of the tunneling oxide. For example, by a TEL SPA (slot plane antenna) tool/machine, wherein oxygen radicals are generated and utilized to form thin thermal oxides (generally of single crystal silicon) at less than 400 degC.
Additional alternative is to integrate logic and programmable logic into the 3D-NOR fabric.
Alternative to construct a PHT on the bottom of the 3D NOR fabric could utilize lithography instead of etch selectivity between O/N/O-1 and the charge transfer oxide of O/N/O-2. One such alternative is illustrated in respect to
These PHTs could be programmed by the first gates using the top part of O/N/O-1, or by forming additional O/N/O-3 and new horizontal gate in replacement of the hard mask 3721.
The horizontal transistor source and drain are part of a vertical transistors of adjacent Ridges which are part of the 3D-NOR structure. Using these two Ridges first bit-lines (BL1) and the appropriate second gates (WLn, WLn+3) these new horizontal transistors could be programmed to three operating modes: Always off, top gate controlled (un-programmed), or always on.
This form of customizing the HD-NOR fabric could allow support for programmable logic as presented in the following.
Use of the NOR structure as illustrated in
The substrate of N channel transistors tightly packed in a 2D array in which every transistor could be configured as an active transistor or a connected path or a disconnected path provides a useful configurable terrain which could be used to form high density NV memory, high speed DRAM and or highly configurable logic terrain. Such a substrate overlaid by custom fabric could be used to form many attractive systems. For example, a NOR substrate of N channel transistors could be configured as domino logic that is known to be a very high speed design technique utilizing primarily N channel transistors. Such as in a paper by Allam, M. W et al titled “High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies”, published at Low Power Electronics and Design, 2000. ISLPED '00, incorporated herein by reference. An improvement is presented allowing higher speed and lower power domino logic.
Specific types of configurable logic could be formed in such 3D-NOR substrates. Within the field of programmable logic the most used fabric for which there currently is a wide range of design tools are the LUT based fabrics used for the most advanced FPGA and the PLA/PLD based fabrics used for some lower complexity smaller devices.
In the wired-or portion 4314 there are isolated central bars 4342 for which there are programmable connections 4324 to each side to the wired-or bar. The two groups are isolated with isolations 4321.
Another alternative is to use the HD-NOR substrate for some of the required memory peripherals circuits. The left side 4312 of 43B illustrates construction of a wide AND circuit that is common for select lines decoder. The AND of
In some applications, such as advanced process nodes, the N type LUT circuit illustrated in
The broken line 4410 indicates the transitions of signals from the customizing the HD-NOR fabric to an overlaying upper layer of CMOS fabric which could carrying the CMOS circuits 4412 and 4414.
The structure of
The use of two complementing N type circuits as described in
An alternative to building a programmable logic fabric on the 3D NOR backside is to build programmable logic fabric within the 3D NOR fabric. For this alternative some of the ridges or portion of them could be targeted for logic integration by using narrow enough S/D lines so in that a portion the S/D region surrounded by second gates are effectively junction-less transistors gated by their respective second gates.
The first gates of the 3D NOR fabric could be used to program each of the channels in the NPN vertical channel column, while the second gates could be used to program the horizontal S/D junctionless transistor (“JLT”) channels, as is illustrated in
These LUT-4s could be arranged along a ridge while their surrounding ridges may function as memories. Since the LUT-4 would need circuits for supporting functions such as half latch 4414, CMOS circuits 4412, signal reconstruction circuit 4202, restore buffer 4002, it could be desired to have more than 5 rows of memory ridge for each logic ridge.
The first gates and the second gates associated with logic function could be disconnected using litho and prices from the gates of the memory ridges, and by use of multiplexers could be made to have dual function. During the programming mode it may be connected to the memory gates and in logic mode be connected to the logic signals.
While junctionless transistors could need a very thin channel of less than 20 nm to have a low leakage comparable with comparable NPN transistor the use of them for programmable logic such as LUT-4 and especially when using two complementing LUT-4s with half latch 4414 reconstruction, could be effective even for larger channel widths, due to the differential function of the circuit and the use of junction less transistors in an N only serially connected structure as illustrated in
The table of
The ‘OR of ANDs’ implementation make a far less use of the junctionless transistor aspect of the S/D lines. It could be implemented even without use of this junctionless transistor by segmenting the ridges to groups of 8 channel columns with the area density penalty associated with such segmentation especially due to the potential stair-case access per layer structure.
Having the both programmable ‘AND of NANDs’ and its complementing ‘OR of ANDs’ allows structuring ridges as a PLA with a half latch reconstruction option providing a wider range of programmable fabric options.
The fabric could be even programmed to allocate regions to LUT type or PLA type according to the need of specific products or type of product.
In similar way the complementing function could be configured from two OR-AND LUT-4.
Using the structure of
An additional flexibility of the 3D NOR fabric is the ability to allocate more rows for the programmable logic cell, if those are available in the fabric. So if the 8 input function requires more than 8 terms then by programming more rows it could be assigned in. A full LUT-8 would require 128 rows.
Another use of the 3D-NOR fabric could be to route a signal through.
It might be preferred to route both the output and its corresponding complementary output to allow better signal recovery as the routing signal within the 3D NOR ridge fabric is associated with many ‘on’ transistors on the routing path and many ‘off’ transistor with their leakage hanging on the path. By using differential signal reconstruction, such as the half-latch 4414, the routed signal could be properly reconstructed.
An alternative structure of the 3D NOR fabric could leave some bridges between the ridges to support full three dimensional routing within the 3D NOR fabric. We can call this variation of the fabric 3D NOR-B. It starts with modifying the ridge 5504 forming a pattern by leaving periodic bridges 5506, of N+ silicon for example, as is illustrated by top view
The followings steps would be similar to those presented in respect to
The bridges would then be a programmable connection between adjacent ridge S/D lines. And accordingly allow routing signal between ridges.
An alternative for the use of the 3D NOR is to use 3D NAND fabric such as the one illustrated in
Let's review the system process flow. It starts as was discussed in respect to
The substrate 5650 could then be removed as illustrated in
This side wafer approach allow the decoupling of the 3D NOR fabrication process from the fabrication of the support circuits. It could allow using a relatively less dense process for generic 3D NOR and an advanced high density process for the support circuits. For example, if the rule used for 3D NOR uses a minimum size of F1 and accordingly the contact area for complementing LUT 4˜80-100 F12. The basic circuits to support such LUT 4 structure are five of the half latch (on for each input signal A, B, C, D and one as just signal re-buffer) and drive illustrated in
In some applications it might be desired to allocate specific gates in the 3D-NOR fabric for logic application. This could allow gates used to control active transistors of the LUT to be with higher speed capability by using thin oxide for those instead of O/N/O. As an example some of the gates connected in
In some applications it might be desired to add on the peripheral circuits on top of the word-lines fabric 5632 using similar concept of layer transfer and “smart-alignment”.
An optional partition of the 3D-NOR fabric, to a multiplicity of units, was previously presented in relation to
The formation of the 3D NOR logic fabric as an array of semi-independent units fits well with the ideas of continuous array and 3D configurable FPGAs as presented in U.S. Pat. Nos. 8,384,426 and 8,115,511 incorporated herein by reference, and related to
Alternatively, the structure of uncovered P region can be selectively removed before the second dummy oxide deposition and after the first dummy oxide removal. As a result, the second oxide could serve as a spacer to not only protect first O/N/O 5820 from accidental write due to a second gate but much more the second oxide could serve as a spacer in the formation of parasitic sidewall vertical NPN transistors gated by the second gate that will be subsequently formed.
The voltages suggested in
The voltage suggested in
A detailed illustration of how such a ‘ripple programming’ of a structure such as
And the ripple programming could be extended to complete forming access per layer S/D line as an alternative to the stair-case process.
Using a structure such as is illustrated in
After the optional etching of the regions designated to become JLT to the tight size with channel of less than about 20 nm has been achieved, a third O/N/O and third gates could be deposited on at least all the designated JLT regions 6432 (could be approximately similar in shape to dummy oxide N regions 6424) as illustrated in
Forming the necking for the JLT transistors is a relatively challenging process due to the small size the S/D lines need to be necked to allow the gate to control the JLT channel. The differential type of programmable logic structure presented herein allows the device to function in a wide range and wide variation of these JLTs. Yet a poor gate control of these JLT would increase the power wasting of the logic circuit. An optional approach could be to use less than 8 layers for the logic by allocating more ridges such as two or four with fewer layers to perform the comparable function.
The alternative structures presented herein are leveraging multilayer 3D stacks.
One such Z direction change technique is the thickness of the various layers in the stack. As the stack could be formed by epitaxial growth, changing the gases time or other process parameters could result in a stack with Z direction changes which could enable forming multilayer structures of about 50 nm per layer in thickness in the memory portion and forming multilayer structures of less than about 20 nm per layer for the N+ layers in the logic portion.
Another alternative is to put a blocking hard pattern in between the memory stack and the logic stack.
While processing fabrics for 3D NOR Memory while also forming 3D NOR Logic could reduce cost in other cases it might work better to process these fabrics mostly independently and then connect them together for a better more efficient (cost and/or performance) overall 3D system. There are many options for mix and match between step and fabric presented herein and the choice of a specific flavor could also be affected by the objective target of the end 3D system.
Additional alternative could be used to further enhance the fabric routing capabilities. In this option the second O/N/O and second gates, or a portion of them, could be replaced by Resistive Random Access Memory—“R-RAM” or One Time Programmable—“OTP” structure. In such an option, this programmable post could be programmed to form bridges between adjacent ridges and between layers of the same ridge offering a very rich connectivity fabric.
A flow could start by modifying the flow in respect to
The starting point could be the 3D NOR structure as illustrated in
An OTP technology has been presented U.S. Pat. Nos. 8,330,189 and 8,390,326 incorporated herein by reference. An RRAM compatible RRAM technology has been described in U.S. Pat. No. 8,581,349 such as in respect to FIG. 32A-J, FIG. 34A-L, FIG. 35A-F, its entirety incorporated herein by reference, a paper by D. Sekar titled “3D Memory with Shared Lithography Steps: The Memory Industry's Plan to “Cram More Components onto Integrated Circuits”, presented at IEEE S3S 2014, By Daeseok Lee et al, titled “BEOL compatible (300° C.) TiN/TiOx/Ta/TiN 3D nanoscale (˜10 nm) IMT selector” published at IEDM 2013, by Liang Zhao et al, titled “Ultrathin (˜2 nm) HfOx as the Fundamental Resistive Switching Element: Thickness Scaling Limit, Stack Engineering and 3D Integration” published at IEDM 2014; by Ke-Jing Lee, titled “Effects of Electrodes on the Switching Behavior of Strontium Titanate Nickelate Resistive Random Access Memory” published at Materials 2015, 8,7191-7198; and also in papers by Sung Hyun Jo et al. in a paper titled “Programmable Resistance Switching in Nanoscale Two-Terminal Devices” published by Nano Lett., Vol. 9, No. 1, 2009; by Adnan Mehonic et al titled “Resistive switching in silicon suboxide films” published by Journal of Applied Physics, Volume 111, Issue 7; and by Yuefei Wang et al. titled “Resistive switching mechanism in silicon highly rich SiOx (x<0.75) films based on silicon dangling bonds percolation model” published by Applied Physics Letters, Volume 102 Number 4; Volume 102 Number, and by Sungjun Kim et al. titled “Fully Si compatible SiN resistive switching memory with large self-rectification ratio” published at AIP ADVANCES 6, 015021 (2016), and titled Gradual bipolar resistive switching in Ni/Si3N4/n+—Si resistive-switching memory device for high-density integration and low-power applications published at Solid-State Electronics 114 (2015) 94-97; and by Shuang Gao et al. titled “Forming-free and self-rectifying resistive switching of the simple Pt/TaOx/n-Si structure for access device-free high-density memory application” published at Nanoscale, 2015, 7, 6031-6038; and by Umesh Chand, titled “Metal induced crystallized poly-Si-based conductive bridge resistive switching memory device with one transistor and one resistor architecture” published at APPLIED PHYSICS LETTERS 107, 203502 (2015); and by Adnan Mehonic titled “Resistive switching in silicon suboxide films” published by JOURNAL OF APPLIED PHYSICS 111, 074507 (2012); all of the foregoing are incorporated herein by reference.
It should be noted the ‘OTP RRAM’ technology described above herein may also be utilized as a multi-stage programmed technology, partially forming/programing to an intermediate resistance value and un-programming for emulation, and then a final full programmation to a low resistance value. With reference to U.S. Pat. Nos. 7,973,559 and 8,390,326, both incorporated herein by reference.
For proper operation a select device should be added to each pillar. These select devices, for example, could be an active transistor or a diode. The select device could use the vertical transistor or diode embedded within the ridges or may added in as polysilicon TFT devices. A simple flow could start by first etching the very top portion of these pillars.
In some alternatives, the structure could include both type of pillars, RRAM and OTP. The OTP could function well for routing which might not need to be altered, for example, such as providing ground “0” to the lower S/D bar of the LUT-4; while the RRAM could function well for connections that would be desired to be reprogrammed. Herein, the junctionless transistor portions arranged in the horizontal plane are selectively replaced by the RRAM and/or OTP. These pillars could also be used for signal input or output by adding additional select elements such as diodes or transistors to protect interference with the pillar programming operation. It is important to note that the RRAM and OTP represented herein are desired to be Ohmic rather than self-rectifying.
The pillar could now be connected to word-lines. It could be desired to connect them in odd/even similar to the first gates connection illustration of
OTP pillars are easier to construct, could offer easier programming and be good enough for most routing applications.
RRAM offer re-programmability and could also be used as embedded non-volatile memory. RRAM pillars could also be used to reduce the need for a JLT process. For such the S/D lines for the logic Ridges could be made with built-in disconnection gaps. RRAM pillars could be used to bridge the gaps with the help of the adjacent Ridge S/D lines for the programming phase.
Without JLT the routing fabric could be a bit less efficient as vertical gaps could be made in all ridges of the fabric in odd/even phases, or other patterns, and RRAM pillars could be used to route signals to adjacent ridges for routing in the S/D lines direction.
RRAM pillars could also be used to allow the ripple programming option for per layer bit-lines structure formation as an alternative to the troublesome stair-case process. For this a modified flow of the one presented in
In such a modified flow, first vertical transistors could be programmed to “On” by first S/D contact 6311 and the corresponding first gate. Than first RRAM pillar could be connected to second S/D line 6332. Now using the first RRAM pillar a second vertical transistor could be turned “On”, and then third S/D line 6333 could be connected to second RRAM pillar. And so forth for all S/D lines. Then all the turned “On” vertical transistors could be turned Off and the correspond RRAM pillars could provide per layer connection to the S/D lines.
Another alternative use of these programmable vertical pillars (RRAM/OTP) is to help overcome poor yield of JLT structures. As discussed for the S/D lines to embed JLT the channel need to be sized below 20 nm—‘necking’. In processing such thin ‘necks’ there is a possibility that some of these necks may be fully disconnected. Such disconnection could present a challenge to program the transistors connected to the permanently disconnected S/D line.
Having the 3D NOR fabric being very memory fabric like, a self-test could be used to write and test read all locations in the fabric to identify defects and such permanently disconnected S/D lines. Using the connected S/D lines the pillars and ‘ripple’ style programming, a flow could be performed to program those transistors and overcome their S/D lines disconnection. Such flow could be illustrated using
Once programmed the pillars could be disconnected from the unbroken S/D lines 1st SD 6831 and 2nd SD 6832 and normal programming could resume. There are other variations and alternative recovery flows that could be made possible using the RRAM/OTP pillars.
An additional alternative is to form the diode access device to the RRAM/OTP 6902 pillars electrode in two steps forming NP diodes for the odd pillars 6956 and PN diodes for the even pillars 6946 as is illustrated in
These signals may be then reconstructed by the half latch 7074, which may be disposed in the overlaying logic support circuits, and then fed to the gates of the next level LUT-X. Such could be implemented for each of the LUTs inputs. The dashed line is indicating the physical separation of the circuit portion within the 3D NOR fabric and the circuit portion within the logic layer/stack.
In another alternative the embedded JLT 6451 could be replaced by P doped poly silicon thus forming a lateral NPN transistor integrated into the S/D lines.
The flow could start first by filling oxide in-between S/D lines just as was shown for the RRAM/OTP pillar formation flow. Then, using non directional etch in defined window regions designated for lateral channel are etch in the S/D lines. Then P doped poly silicon may be deposited in a non-directional deposition techniques such as ALD could be used to fully fill the etched S/D regions. Then using directional etch the side poly is removed leaving the poly integrated with the S/D lines. Laser and other annealing techniques could be used to crystallize the poly silicon and integrate it with S/D N type silicon to complete formation of the lateral NPN transistors. Then third O/N/O and gate could be deposited and formed, substantially completing the structure.
The RRAM/OTP pillars 7302, 7304, could be used to form connection into the LUT-X logic cell to enable cell programming such as converting one LUT-4 into two LUT-2s, as is illustrated in
The top S/D lines 7411 would act as the gate for the programming of the 3rd O/N/O 7406 to program these select transistors.
Differential routing is an option that has some advantages but does consume twice the routing resources. In some applications mixing differential routing with conventional single ended routing could provide better overall optimization. Having mixed types of routing resources such as conventional metal routing over the control circuits 7530 and silicon through RRAM/OTP connection and through ONO programmable transistors in the 3D NOR fabric might advise mixing also the routing techniques. Accordingly standard single ended could be use for signals over metal while differential type could be used for the other type of routing resources.
An alternative for forming an NPN select device for the RRAM/OTP pillar is by depositing or transferring an NPN layer and then etch it thus leaving select device on top of each pillar.
Additional alternative is to replace the ‘necking’ process with a channel replacement process thereby instead of forming JLTs by ‘necking’, an NPN may be formed by replacing the ‘neck’ with P type poly silicon as is illustrated in the following
This kind of lateral NPN could be formed as an alternative to JLTs as were been presented herein.
For the read additional circuits could be added for the S/D line with integrating an analog to digital converter. Such structures could support multiple signal processing techniques to allow flexibility between storage density, access speed, and device yield. This charge trap 3D NOR memory could be used also for brain-like storage where charges are being added to memory locations in similar fashion to the human brain synapse. As a general note we described herein a memory structure and variations. There are many ways to form other variations of these structures that would be obvious to an artisan in the semiconductor memory domain to form by the presented elements described herein. These may include exchanging n type with p type and vice versa, increase density by sharing control lines, silicidation of some in-silicon control lines, improve speed and reduce variation by strengthening bit-lines and word-line with upper layer parallel running and periodically connected metal lines.
The sizing of the structure and accordingly of the memory channel could be designed in consideration of access time, operation time memory durability costs and many other considerations. The 3D structure provides interesting attributes as more memory could be added by having a larger number of layers. Processing a higher number of layers is easier when the dimensions of the patterns within the layer are relatively larger. In general the historic trend of the industry has been to make devices smaller and smaller to reduce cost per storage bit and increase memory integration. As size gets reduced beyond a certain level the bit storage will be limited both in how much charge and accordingly how many levels could be stored in one charge trap site Additionally, bit storage will be limited by how many sites could be used on one facet without cross interference between them, also called the second-bit effect (SBE), retention time, reliability, and control-lines resistance and capacity (RC) are all negatively impacted as well. In a 3D NOR structure the individual memory cell could be kept relatively large to achieve the desired attributes of bit capacity on a individual facet both in number of sites and how many levels are stored in each site. This will achieve the desired reliability retention and access time while increasing the number of layers to increase memory integration and reduce cost per memory cell. The dimension of—length, width, and height of the memory cell channel could be designed accordingly and those could be relatively similar resulting with a cube like channel or varied to so they are very different. The formation of the O/N/O structure could be modified to enable a charge trap structure that has on its own multiple layers to allow more levels for the multilevel bit storage techniques. Some of these approaches are detailed in papers by: Gu Haiming et al titled “Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array” published in Vol. 31, No. 10 Journal of Semiconductors October 2010; Ye Zhoul, et al titled “Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism published at SCIENTIFIC REPORTS|3:2319| DOI: 10.1038/srep02319; Kyoung-Rok Han et al titled “:Multi-bit/Cell SONOS Flash Memory with Recessed Channel Structure” published at NSTI-Nanotech 2008; by Guangli WANG titled “Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods” published at Front. Optoclectron. China 2011, 4(2): 146-149; by Yan-Xiang Luo et al titled “Coupling of carriers injection and charges distribution in Schottky barrier charge trapping memories using source-side electrons programming” published at Semicond. Sci. Technol. 29 (2014) 115006 (8 pp); by Chun-Hsing Shih, titled “Reading Operation and Cell Scalability of Nonvolatile Schottky barrier Multibit Charge-Trapping Memory Cells” at IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012, by Zhenjie Tang et al titled “Dependence of memory characteristics on the (ZrO2)x (SiO2)1−x elemental composition” at Semicond. Sci. Technol. 30 (2015)065010, by Jun Yong Bak Nonvolatile Charge-Trap Memory Transistors With Top-Gate Structure Using In—Ga—Zn—O Active Channel and ZnO Charge-Trap Layer” at IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 3, MARCH 2014, and U.S. Pat. No. 8,822,288 all incorporated herein by reference.
The differential amplifier circuit illustrated in
The 3D NOR fabric uses the O/N/O ‘mirror bit’ aspect to store many bits on each facet and accordingly a none conducting charge trap is valuable to increase memory storage. The use of 3D NOR fabric for logic and routing does not leverage this aspect and accordingly a floating gate such as polysilicon could be as useful. An artisan in the art could do the proper modifications to the process flows presented in here for alternatives utilizing the 3D NOR structure described herein utilizing alternative storage mediums such as floating gate, ReRAM, in which the O/N/O structure could be replaced by ReRAM structure, floating gate based structure and so forth.
The structure of this 3D NOR could be modified by changing the gate stack to construct a 3D-DRAM using the floating body technique.
The Floating body of the 3D-DRAM or of the 3D-NOR Universal memory could be refreshed using the self-refresh described herein.
A silicidation could be used in some portions of the S/D lines such as for regions designated to be potential contacts to the RRAM/OTP pillars as is illustrated in
For a JLT to have low off current it might be desired to limit the dopant of the S/D lines below 1E20 atoms/cm3, yet for the S/D lines to serve better as a routing fabric it would be better to have them doped to over 1E20 atoms/cm3. An optional solution could be to add doping by diffusion (gas, solid, implant, depending on integration engineering choices) or similar techniques while the regions for the JLT are protected using lithography and proper masking.
The 3D NOR fabric could be programmed to enable additional LUT type functions and other programmable functions. In the following sections, some of these other non LUT functions are presented.
The structure of
Many additional functions could be formed to enhance the overall usability of the 3D NOR fabric for programmable logic implementation.
Two function outputs could be wired together forming a wired-AND function (one of the functions is low and the result is low).
An output of one function could be used in a following function by connecting it instead of the ‘0’ input forming a ‘daisy chain’ OR connection (one of the function is ‘high’ and the output is ‘high’).
So if two functions are wired AND their inverting function could be ‘daisy chain’ OR to form a proper inverted signal.
An alternative approach to connect multiple functions is using Output Enable (“OE”) control.
A structure for LUT-4 could be degraded to LUT-3 with one input function as OE.
For some functions single ended logic could be used via a modified ‘domino logic’ reconstruction circuit.
Since the design of 3D NOR fabric allows for non-volatile (NV) programming of its channels it could support built-in NV memory.
There are 4 select lines—S1, S2, S3, S4. One of those could be selected by connecting it to “ground” while the other are kept at high resistivity/floating. A 2 to 4 circuit (
The RRAM/OTP pillars may be programmed to be connected as illustrated in
If the gates input are not pre-connected in pairs then the memory content of the structure could be doubled.
The structure could be programmed in pairs, a ridge and its complement, for double output reconstruction. If a single ended output reconstruction is used then the memory density could be doubled.
Another type of memory that could be implemented within the 3D NOR logic fabric is volatile memory utilizing the floating body effect of the P channel and the refresh techniques described before in respect to floating body memory under the terms ‘periodic refresh’, ‘self refresh’ or “Autonomous Refresh”. Some of this technique has been detailed in a paper by Takashi Ohsawa et. al. entitled: “Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization”.
The top circuit 8720 illustrates two sections. The left side is the direct access for reading the memory using the other side of the RRAM/OTP pillars to individually access the ‘bit-lines’ of each memory row—b1, b2, b3, b4, b5, b6. This could be done using the differential approach by having the adjacent ridge storing the complement data and using the half latch or differential amplifier circuit to compare the corresponding ‘bit-lines’ for the selected memory column by selecting one gate line acting as word-line—w1, w2, w3, w4, w5, w6, w7, w8.
The SL lines are the segments marked “0” and are shared between two memory cells. The other S/D segments are used for the BL lines. The right side of the structure is providing the write voltages for the structure Vpp (2.4V) or Vpp-(−1.5V). It utilizes three S/D segments marked as Vpp/Vpp- to distribute these writing voltages which then could be activated for the selected row by the gate control of one of p1, p2, p3, p4, p5, p6. The write control portion could support multiple memory structures if connected in series to the left side bit memory structure.
Both types of memory are dual port as they are accessible from the ‘top’—the logic fabric side and from the ‘bottom’, the programming side.
Alternatively another mode of “Autonomous Refresh” could be used as outlined in the referenced paper and is illustrated in
The top control circuit 8720 for the RAM portion is dedicated and accordingly
The utilization of the 3D-NOR fabric for logic is highly dependent on the efficiency of the overlying control circuit. If the process node used for the control logic is advanced enough then substantially all of the fabric ridges could be used for logic operations. If the control logic circuit density is further improved it might be desired to improve the overall logic density by having the two complementing logic units, one underneath the other, as is illustrated in
Another alternative to increase the 3D NOR logic density is to use the bottom side for logic as well. A layer transfer flow for forming a 3D programmable system leveraging the 3D NOR fabric was described in respect to
The programming peripherals circuits 9154 could be multiplexed with the bottom logic control circuits 9174 with access to the gates.
The gates could be allocated between right side of the ridge and left side and top control and bottom control circuits. Alternatively the fabrication of the 3D NOR fabric could include isolation of the gate between top and bottom using technique such as the one described in respect to
Another alternative enhancement for the 3D NOR logic fabric is adding Lateral RRAM for Y direction connectivity. The starting point is illustrated in
Now the necking step could be done followed by its O/N/O and gate formation.
The programming of the Lateral RRAM portion can be conducted by the resistance change across the resistive switching material. The resistive switching materials incorporated herein can be electrolyte materials such as conductive bridge material, or phase change materials where its crystallographic phase can be changed from amorphous-to-crystalline or crystalline-to-amorphous by Joule heating, or a thin oxide layer where its oxygen vacancies form charge traps or conductive filaments. The resistance across the resistive switching materials is substantially changed from before to after the programming. The resistive changing material is normally insulating, but it is made to be conductive through the conductive path, which is called programming. The programming can be carried out by applying a high voltage, depending on material and design considerations for example such as 5 V, between a pillar and an S/D segment crossing a node to be programming. If the multi-time programmability is available, the programmed state can be erased. For example, if the erase mechanism involves the movement of oxygen vacancies, a high negative voltage such as −5 V is applied between a pillar and an S/D segment crossing a node to be erased. Alternatively, if the erase mechanism involves Joule heating, a high positive voltage but less than the programming voltage such as 3 V is applied between a pillar and an S/D segment crossing a node to be erased. During the programming or erasing operations, the lateral junctionless transistors on the selected pair of S/D segments are all turned on by applying a pass voltage to the second gate lines regardless of the programmed statues of the JLTs.
Now these pillars 9224 could be connected forming a fourth gate to be used to start the lateral RRAM programming by feeding positive voltage through the P+ poly pillars to the lateral RRAMs. Then the lateral RRAM connection to the selected regions of the selected S/D lines could be done by selecting specific locations of the specific S/D segment to be connected to the relevant lateral RRAM. G
An alternative application of the technology is to use part of the 3D NOR logic fabric for operations resembling a brain Synapse. A paper by Lixue Xia titled “Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication” published at JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 31(1): 3-19 Jan. 2016, incorporated herein by reference, teach the use of a crossbar RRAM array for matrix-vector multiplication. Accordingly the RRAM pillars and the corresponding S/D segments could be used for such functions. Papers by Sangsu Park et al titled “Electronic system with memristive synapses for pattern recognition” published by Scientific Reports|5:10123|DOI: 10.1038/srep10123, by Yu Wang et al, titled “Energy Efficient RRAM Spiking Neural Network for Real Time Classification”, published at the 25th Symposium on VLSI, by Manan Suri, titled “Exploiting Intrinsic Variability of Filamentary Resistive Memory for Extreme Learning Machine Architectures” published by IEEE Transactions on Nanotechnology 15 Jun. 2015 and Sangsu Park, titled “Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device” published by Nanotechnology 24 (2013), all the forgoing incorporated herein by reference teach use of an RRAM cross-bar for brain type processing and accordingly could be implemented in the 3D NOR fabric RRAM pillars and the corresponding S/D segments.
Another alternative is to utilize the 3D NOR fabric floating-body memory structure for Synapse type circuit as is presented in paper such as one by Min-Woo Kwon et al titled “Integrate-and-Fire Neuron Circuit and Synaptic Device using Floating Body MOSFET with Spike Timing-Dependent Plasticity” published by JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL. 15, NO. 6, DECEMBER, 2015, incorporated herein by reference.
As a general note we described herein 3D memory structure and variations. There are many ways to form other variations of these structures that would be obvious to artisan in the semiconductor memory domain to form by the presented elements described herein. These may include exchanging n type with p type and vice versa, increase density by sharing control lines, silicidation of some in silicon control lines, providing stair case on both sides of memory blocks to improve speed and reduce variation including sharing staircase in between two blocks and other presented variations herein. Many of these options had been presented in some memory options in more details and it would be obvious to artisan in the semiconductor memory domain to apply to the other memory structures.
The structures and flow presented herein are utilizing NPN transistors. Other types of transistors with the corresponding modification of process and materials could be used as alternative such as junction-less transistors, or non-silicon transistors (for example SiGe, CNT, and so on). Those alternatives could be implemented leveraging the special benefits of the architecture disclosed herein.
It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. For example, drawings or illustrations may not show n or p wells for clarity in illustration. Moreover, transistor channels illustrated or discussed herein may include doped semiconductors, but may instead include undoped semiconductor material. Further, any transferred layer or donor substrate or wafer preparation illustrated or discussed herein may include one or more undoped regions or layers of semiconductor material. Further, transferred layer or layers may have regions of STI or other transistor elements within it or on it when transferred. Rather, the scope of the invention includes combinations and sub-combinations of the various features described hereinabove as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by appended claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3007090 | Rutz | Oct 1961 | A |
| 3819959 | Chang et al. | Jun 1974 | A |
| 4009483 | Clark | Feb 1977 | A |
| 4197555 | Uehara et al. | Apr 1980 | A |
| 4213139 | Rao et al. | Jul 1980 | A |
| 4400715 | Barbee et al. | Aug 1983 | A |
| 4487635 | Kugimiya et al. | Dec 1984 | A |
| 4510670 | Schwabe | Apr 1985 | A |
| 4522657 | Rohatgi et al. | Jun 1985 | A |
| 4612083 | Yasumoto et al. | Sep 1986 | A |
| 4643950 | Ogura et al. | Feb 1987 | A |
| 4704785 | Curran | Nov 1987 | A |
| 4711858 | Harder et al. | Dec 1987 | A |
| 4721885 | Brodie | Jan 1988 | A |
| 4732312 | Kennedy et al. | Mar 1988 | A |
| 4733288 | Sato | Mar 1988 | A |
| 4829018 | Wahlstrom | May 1989 | A |
| 4854986 | Raby | Aug 1989 | A |
| 4866304 | Yu | Sep 1989 | A |
| 4939568 | Kato et al. | Jul 1990 | A |
| 4956307 | Pollack et al. | Sep 1990 | A |
| 5012153 | Atkinson et al. | Apr 1991 | A |
| 5032007 | Silverstein et al. | Jul 1991 | A |
| 5047979 | Leung | Sep 1991 | A |
| 5087585 | Hayashi | Feb 1992 | A |
| 5093704 | Sato et al. | Mar 1992 | A |
| 5106775 | Kaga et al. | Apr 1992 | A |
| 5152857 | Ito et al. | Oct 1992 | A |
| 5162879 | Gill | Nov 1992 | A |
| 5189500 | Kusunoki | Feb 1993 | A |
| 5217916 | Anderson et al. | Jun 1993 | A |
| 5250460 | Yamagata et al. | Oct 1993 | A |
| 5258643 | Cohen | Nov 1993 | A |
| 5265047 | Leung et al. | Nov 1993 | A |
| 5266511 | Takao | Nov 1993 | A |
| 5277748 | Sakaguchi et al. | Jan 1994 | A |
| 5286670 | Kang et al. | Feb 1994 | A |
| 5294556 | Kawamura | Mar 1994 | A |
| 5308782 | Mazure et al. | May 1994 | A |
| 5312771 | Yonehara | May 1994 | A |
| 5317236 | Zavracky et al. | May 1994 | A |
| 5324980 | Kusunoki | Jun 1994 | A |
| 5355022 | Sugahara et al. | Oct 1994 | A |
| 5371037 | Yonehara | Dec 1994 | A |
| 5374564 | Bruel | Dec 1994 | A |
| 5374581 | Ichikawa et al. | Dec 1994 | A |
| 5424560 | Norman et al. | Jun 1995 | A |
| 5475280 | Jones et al. | Dec 1995 | A |
| 5478762 | Chao | Dec 1995 | A |
| 5485031 | Zhang et al. | Jan 1996 | A |
| 5498978 | Takahashi et al. | Mar 1996 | A |
| 5527423 | Neville et al. | Jun 1996 | A |
| 5535342 | Taylor | Jul 1996 | A |
| 5554870 | Fitch et al. | Sep 1996 | A |
| 5563084 | Ramm et al. | Oct 1996 | A |
| 5583349 | Norman et al. | Dec 1996 | A |
| 5583350 | Norman et al. | Dec 1996 | A |
| 5586291 | Lasker | Dec 1996 | A |
| 5594563 | Larson | Jan 1997 | A |
| 5604137 | Yamazaki et al. | Feb 1997 | A |
| 5617991 | Pramanick et al. | Apr 1997 | A |
| 5627106 | Hsu | May 1997 | A |
| 5656548 | Zavracky et al. | Aug 1997 | A |
| 5656553 | Leas et al. | Aug 1997 | A |
| 5659194 | Iwamatsu | Aug 1997 | A |
| 5670411 | Yonehara | Sep 1997 | A |
| 5681756 | Norman et al. | Oct 1997 | A |
| 5695557 | Yamagata et al. | Dec 1997 | A |
| 5701027 | Gordon et al. | Dec 1997 | A |
| 5707745 | Forrest et al. | Jan 1998 | A |
| 5714395 | Bruel | Feb 1998 | A |
| 5721160 | Forrest et al. | Feb 1998 | A |
| 5737748 | Shigeeda | Apr 1998 | A |
| 5739552 | Kimura et al. | Apr 1998 | A |
| 5744979 | Goetting | Apr 1998 | A |
| 5748161 | Lebby et al. | May 1998 | A |
| 5757026 | Forrest et al. | May 1998 | A |
| 5770483 | Kadosh | Jun 1998 | A |
| 5770881 | Pelella et al. | Jun 1998 | A |
| 5781031 | Bertin et al. | Jul 1998 | A |
| 5817574 | Gardner | Oct 1998 | A |
| 5829026 | Leung et al. | Oct 1998 | A |
| 5835396 | Zhang | Nov 1998 | A |
| 5854123 | Sato et al. | Dec 1998 | A |
| 5861929 | Spitzer | Jan 1999 | A |
| 5877034 | Ramm | Mar 1999 | A |
| 5877070 | Goesele et al. | Mar 1999 | A |
| 5882987 | Srikrishnan | Mar 1999 | A |
| 5883525 | Tavana et al. | Mar 1999 | A |
| 5889903 | Rao | Mar 1999 | A |
| 5893721 | Huang et al. | Apr 1999 | A |
| 5915167 | Leedy | Jun 1999 | A |
| 5920788 | Reinberg | Jul 1999 | A |
| 5937312 | Iyer et al. | Aug 1999 | A |
| 5943574 | Tehrani et al. | Aug 1999 | A |
| 5952680 | Strite | Sep 1999 | A |
| 5952681 | Chen | Sep 1999 | A |
| 5965875 | Merrill | Oct 1999 | A |
| 5977579 | Noble | Nov 1999 | A |
| 5977961 | Rindal | Nov 1999 | A |
| 5980633 | Yamagata et al. | Nov 1999 | A |
| 5985742 | Henley et al. | Nov 1999 | A |
| 5994746 | Reisinger | Nov 1999 | A |
| 5998808 | Matsushita | Dec 1999 | A |
| 6001693 | Yeouchung et al. | Dec 1999 | A |
| 6009496 | Tsai | Dec 1999 | A |
| 6020252 | Aspar et al. | Feb 2000 | A |
| 6020263 | Shih et al. | Feb 2000 | A |
| 6027958 | Vu et al. | Feb 2000 | A |
| 6030700 | Forrest et al. | Feb 2000 | A |
| 6052498 | Paniccia | Apr 2000 | A |
| 6054370 | Doyle | Apr 2000 | A |
| 6057212 | Chan et al. | May 2000 | A |
| 6071795 | Cheung et al. | Jun 2000 | A |
| 6075268 | Gardner et al. | Jun 2000 | A |
| 6103597 | Aspar et al. | Aug 2000 | A |
| 6111260 | Dawson et al. | Aug 2000 | A |
| 6125217 | Paniccia et al. | Sep 2000 | A |
| 6153495 | Kub et al. | Nov 2000 | A |
| 6191007 | Matsui et al. | Feb 2001 | B1 |
| 6200878 | Yamagata | Mar 2001 | B1 |
| 6204529 | Lung et al. | Mar 2001 | B1 |
| 6222203 | Ishibashi et al. | Apr 2001 | B1 |
| 6226197 | Nishimura | May 2001 | B1 |
| 6229161 | Nemati et al. | May 2001 | B1 |
| 6242324 | Kub et al. | Jun 2001 | B1 |
| 6242778 | Marmillion et al. | Jun 2001 | B1 |
| 6252465 | Katoh | Jun 2001 | B1 |
| 6259623 | Takahashi | Jul 2001 | B1 |
| 6261935 | See et al. | Jul 2001 | B1 |
| 6264805 | Forrest et al. | Jul 2001 | B1 |
| 6281102 | Cao et al. | Aug 2001 | B1 |
| 6294018 | Hamm et al. | Sep 2001 | B1 |
| 6306705 | Parekh et al. | Oct 2001 | B1 |
| 6321134 | Henley et al. | Nov 2001 | B1 |
| 6322903 | Siniaguine et al. | Nov 2001 | B1 |
| 6331468 | Aronowitz et al. | Dec 2001 | B1 |
| 6331790 | Or-Bach et al. | Dec 2001 | B1 |
| 6331943 | Naji et al. | Dec 2001 | B1 |
| 6353492 | McClelland et al. | Mar 2002 | B2 |
| 6355501 | Fung et al. | Mar 2002 | B1 |
| 6355976 | Faris | Mar 2002 | B1 |
| 6358631 | Forrest et al. | Mar 2002 | B1 |
| 6365270 | Forrest et al. | Apr 2002 | B2 |
| 6376337 | Wang et al. | Apr 2002 | B1 |
| 6377504 | Hilbert | Apr 2002 | B1 |
| 6380046 | Yamazaki | Apr 2002 | B1 |
| 6392253 | Saxena | May 2002 | B1 |
| 6404043 | Isaak | Jun 2002 | B1 |
| 6417108 | Akino et al. | Jul 2002 | B1 |
| 6420215 | Knall et al. | Jul 2002 | B1 |
| 6423614 | Doyle | Jul 2002 | B1 |
| 6429481 | Mo et al. | Aug 2002 | B1 |
| 6429484 | Yu | Aug 2002 | B1 |
| 6430734 | Zahar | Aug 2002 | B1 |
| 6448615 | Forbes | Sep 2002 | B1 |
| 6475869 | Yu | Nov 2002 | B1 |
| 6476493 | Or-Bach et al. | Nov 2002 | B2 |
| 6479821 | Hawryluk et al. | Nov 2002 | B1 |
| 6483707 | Freuler et al. | Nov 2002 | B1 |
| 6507115 | Hofstee | Jan 2003 | B2 |
| 6515334 | Yamazaki et al. | Feb 2003 | B2 |
| 6515511 | Sugibayashi et al. | Feb 2003 | B2 |
| 6526559 | Schiefele et al. | Feb 2003 | B2 |
| 6528391 | Henley et al. | Mar 2003 | B1 |
| 6534352 | Kim | Mar 2003 | B1 |
| 6534382 | Sakaguchi et al. | Mar 2003 | B1 |
| 6544837 | Divakauni et al. | Apr 2003 | B1 |
| 6545314 | Forbes et al. | Apr 2003 | B2 |
| 6555901 | Yoshihara et al. | Apr 2003 | B1 |
| 6563139 | Hen | May 2003 | B2 |
| 6580124 | Cleeves | Jun 2003 | B1 |
| 6580289 | Cox | Jun 2003 | B2 |
| 6600173 | Tiwari | Jul 2003 | B2 |
| 6617694 | Kodaira et al. | Sep 2003 | B2 |
| 6620659 | Emmma et al. | Sep 2003 | B2 |
| 6624046 | Zavracky et al. | Sep 2003 | B1 |
| 6627518 | Inoue et al. | Sep 2003 | B1 |
| 6627985 | Huppenthal et al. | Sep 2003 | B2 |
| 6630713 | Geusic | Oct 2003 | B2 |
| 6635552 | Gonzalez | Oct 2003 | B1 |
| 6635588 | Hawryluk et al. | Oct 2003 | B1 |
| 6638834 | Gonzalez | Oct 2003 | B2 |
| 6642744 | Or-Bach et al. | Nov 2003 | B2 |
| 6653209 | Yamagata | Nov 2003 | B1 |
| 6653712 | Knall et al. | Nov 2003 | B2 |
| 6661085 | Kellar et al. | Dec 2003 | B2 |
| 6677204 | Cleeves et al. | Jan 2004 | B2 |
| 6686253 | Or-Bach | Feb 2004 | B2 |
| 6689660 | Noble | Feb 2004 | B1 |
| 6701071 | Wada et al. | Mar 2004 | B2 |
| 6703328 | Tanaka et al. | Mar 2004 | B2 |
| 6720613 | Chang | Apr 2004 | B1 |
| 6756633 | Wang et al. | Jun 2004 | B2 |
| 6756811 | Or-Bach | Jun 2004 | B2 |
| 6759282 | Campbell et al. | Jul 2004 | B2 |
| 6762076 | Kim et al. | Jul 2004 | B2 |
| 6774010 | Chu et al. | Aug 2004 | B2 |
| 6805979 | Ogura et al. | Oct 2004 | B2 |
| 6806171 | Ulyashin et al. | Oct 2004 | B1 |
| 6809009 | Aspar et al. | Oct 2004 | B2 |
| 6815781 | Vyvoda et al. | Nov 2004 | B2 |
| 6819136 | Or-Bach | Nov 2004 | B2 |
| 6821826 | Chan et al. | Nov 2004 | B1 |
| 6841813 | Walker et al. | Jan 2005 | B2 |
| 6844243 | Gonzalez | Jan 2005 | B1 |
| 6864534 | Ipposhi et al. | Mar 2005 | B2 |
| 6875671 | Faris | Apr 2005 | B2 |
| 6882572 | Wang et al. | Apr 2005 | B2 |
| 6888375 | Feng et al. | May 2005 | B2 |
| 6917219 | New | Jul 2005 | B2 |
| 6927431 | Gonzalez | Aug 2005 | B2 |
| 6930511 | Or-Bach | Aug 2005 | B2 |
| 6943067 | Greenlaw | Sep 2005 | B2 |
| 6943407 | Ouyang et al. | Sep 2005 | B2 |
| 6949421 | Padmanabhan et al. | Sep 2005 | B1 |
| 6953956 | Or-Bach et al. | Oct 2005 | B2 |
| 6967149 | Meyer et al. | Nov 2005 | B2 |
| 6985012 | Or-Bach | Jan 2006 | B2 |
| 6989687 | Or-Bach | Jan 2006 | B2 |
| 6995430 | Langdo et al. | Feb 2006 | B2 |
| 6995456 | Nowak | Feb 2006 | B2 |
| 7015719 | Feng et al. | Mar 2006 | B1 |
| 7016569 | Mule et al. | Mar 2006 | B2 |
| 7018875 | Madurawe | Mar 2006 | B2 |
| 7019557 | Madurawe | Mar 2006 | B2 |
| 7043106 | West et al. | May 2006 | B2 |
| 7052941 | Lee | May 2006 | B2 |
| 7064579 | Madurawe | Jun 2006 | B2 |
| 7067396 | Aspar et al. | Jun 2006 | B2 |
| 7067909 | Reif et al. | Jun 2006 | B2 |
| 7068070 | Or-Bach | Jun 2006 | B2 |
| 7068072 | New et al. | Jun 2006 | B2 |
| 7078739 | Nemati et al. | Jul 2006 | B1 |
| 7091551 | Anderson et al. | Aug 2006 | B1 |
| 7094667 | Bower | Aug 2006 | B1 |
| 7098691 | Or-Bach et al. | Aug 2006 | B2 |
| 7105390 | Brask et al. | Sep 2006 | B2 |
| 7105871 | Or-Bach et al. | Sep 2006 | B2 |
| 7109092 | Tong | Sep 2006 | B2 |
| 7110629 | Bjorkman et al. | Sep 2006 | B2 |
| 7111149 | Eilert | Sep 2006 | B2 |
| 7112815 | Prall | Sep 2006 | B2 |
| 7115945 | Lee et al. | Oct 2006 | B2 |
| 7115966 | Ido et al. | Oct 2006 | B2 |
| 7141853 | Campbell et al. | Nov 2006 | B2 |
| 7148119 | Sakaguchi et al. | Dec 2006 | B1 |
| 7157787 | Kim et al. | Jan 2007 | B2 |
| 7157937 | Apostol et al. | Jan 2007 | B2 |
| 7166520 | Henley | Jan 2007 | B1 |
| 7170807 | Fazan et al. | Jan 2007 | B2 |
| 7173369 | Forrest et al. | Feb 2007 | B2 |
| 7180091 | Yamazaki et al. | Feb 2007 | B2 |
| 7180379 | Hopper et al. | Feb 2007 | B1 |
| 7183611 | Bhattacharyya | Feb 2007 | B2 |
| 7189489 | Kunimoto et al. | Mar 2007 | B2 |
| 7205204 | Ogawa et al. | Apr 2007 | B2 |
| 7209384 | Kim | Apr 2007 | B1 |
| 7217636 | Atanackovic | May 2007 | B1 |
| 7223612 | Sarma | May 2007 | B2 |
| 7242012 | Leedy | Jul 2007 | B2 |
| 7245002 | Akino et al. | Jul 2007 | B2 |
| 7256104 | Ito et al. | Aug 2007 | B2 |
| 7259091 | Schuehrer et al. | Aug 2007 | B2 |
| 7265421 | Madurawe | Sep 2007 | B2 |
| 7271420 | Cao | Sep 2007 | B2 |
| 7274207 | Sugawara et al. | Sep 2007 | B2 |
| 7282951 | Huppenthal et al. | Oct 2007 | B2 |
| 7284226 | Kondapalli | Oct 2007 | B1 |
| 7296201 | Abramovici | Nov 2007 | B2 |
| 7304355 | Zhang | Dec 2007 | B2 |
| 7312109 | Madurawe | Dec 2007 | B2 |
| 7312487 | Alam et al. | Dec 2007 | B2 |
| 7314788 | Shaw | Jan 2008 | B2 |
| 7335573 | Takayama et al. | Feb 2008 | B2 |
| 7337425 | Kirk | Feb 2008 | B2 |
| 7338884 | Shimoto et al. | Mar 2008 | B2 |
| 7339821 | Walker | Mar 2008 | B2 |
| 7342415 | Teig et al. | Mar 2008 | B2 |
| 7351644 | Henley | Apr 2008 | B2 |
| 7358601 | Plants et al. | Apr 2008 | B1 |
| 7362133 | Madurawe | Apr 2008 | B2 |
| 7369435 | Forbes | May 2008 | B2 |
| 7371660 | Henley et al. | May 2008 | B2 |
| 7378702 | Lee | May 2008 | B2 |
| 7381989 | Kim | Jun 2008 | B2 |
| 7385283 | Wu | Jun 2008 | B2 |
| 7393722 | Issaq et al. | Jul 2008 | B1 |
| 7402483 | Yu et al. | Jul 2008 | B2 |
| 7402897 | Leedy | Jul 2008 | B2 |
| 7419844 | Lee et al. | Sep 2008 | B2 |
| 7432185 | Kim | Oct 2008 | B2 |
| 7436027 | Ogawa et al. | Oct 2008 | B2 |
| 7439773 | Or-Bach et al. | Oct 2008 | B2 |
| 7446563 | Madurawe | Nov 2008 | B2 |
| 7459752 | Doris et al. | Dec 2008 | B2 |
| 7459763 | Issaq et al. | Dec 2008 | B1 |
| 7459772 | Speers | Dec 2008 | B2 |
| 7463062 | Or-Bach et al. | Dec 2008 | B2 |
| 7463502 | Stipe | Dec 2008 | B2 |
| 7470142 | Lee | Dec 2008 | B2 |
| 7470598 | Lee | Dec 2008 | B2 |
| 7476939 | Okhonin et al. | Jan 2009 | B2 |
| 7477540 | Okhonin et al. | Jan 2009 | B2 |
| 7485536 | Jin et al. | Feb 2009 | B2 |
| 7485968 | Enquist et al. | Feb 2009 | B2 |
| 7486563 | Waller et al. | Feb 2009 | B2 |
| 7488980 | Takafuji et al. | Feb 2009 | B2 |
| 7492632 | Carman | Feb 2009 | B2 |
| 7495473 | McCollum et al. | Feb 2009 | B2 |
| 7498675 | Farnworth et al. | Mar 2009 | B2 |
| 7499352 | Singh | Mar 2009 | B2 |
| 7499358 | Bauser | Mar 2009 | B2 |
| 7508034 | Takafuji et al. | Mar 2009 | B2 |
| 7514748 | Fazan et al. | Apr 2009 | B2 |
| 7521806 | Trezza | Apr 2009 | B2 |
| 7525186 | Kim et al. | Apr 2009 | B2 |
| 7535089 | Fitzgerald | May 2009 | B2 |
| 7541616 | Fazan et al. | Jun 2009 | B2 |
| 7547589 | Iriguchi | Jun 2009 | B2 |
| 7553745 | Lim | Jun 2009 | B2 |
| 7557367 | Rogers et al. | Jul 2009 | B2 |
| 7558141 | Katsumata et al. | Jul 2009 | B2 |
| 7563659 | Kwon et al. | Jul 2009 | B2 |
| 7566855 | Olsen et al. | Jul 2009 | B2 |
| 7566974 | Konevecki | Jul 2009 | B2 |
| 7586778 | Ho et al. | Sep 2009 | B2 |
| 7589375 | Jang et al. | Sep 2009 | B2 |
| 7608848 | Ho et al. | Oct 2009 | B2 |
| 7612411 | Walker | Nov 2009 | B2 |
| 7615462 | Kim et al. | Nov 2009 | B2 |
| 7622367 | Nuzzo et al. | Nov 2009 | B1 |
| 7629640 | She et al. | Dec 2009 | B2 |
| 7632738 | Lee | Dec 2009 | B2 |
| 7633162 | Lee | Dec 2009 | B2 |
| 7638836 | Walker | Dec 2009 | B2 |
| 7666723 | Frank et al. | Feb 2010 | B2 |
| 7670912 | Yeo | Mar 2010 | B2 |
| 7671371 | Lee | Mar 2010 | B2 |
| 7671460 | Lauxtermann et al. | Mar 2010 | B2 |
| 7674687 | Henley | Mar 2010 | B2 |
| 7687372 | Jain | Mar 2010 | B2 |
| 7687872 | Cazaux | Mar 2010 | B2 |
| 7688619 | Lung et al. | Mar 2010 | B2 |
| 7692202 | Bensch | Apr 2010 | B2 |
| 7692448 | Solomon | Apr 2010 | B2 |
| 7692944 | Bernstein et al. | Apr 2010 | B2 |
| 7697316 | Lai et al. | Apr 2010 | B2 |
| 7709932 | Nemoto et al. | May 2010 | B2 |
| 7718508 | Lee | May 2010 | B2 |
| 7719876 | Chevallier | May 2010 | B2 |
| 7723207 | Alam et al. | May 2010 | B2 |
| 7728326 | Yamazaki et al. | Jun 2010 | B2 |
| 7732301 | Pinnington et al. | Jun 2010 | B1 |
| 7741673 | Tak et al. | Jun 2010 | B2 |
| 7742331 | Watanabe | Jun 2010 | B2 |
| 7745250 | Han | Jun 2010 | B2 |
| 7749884 | Mathew et al. | Jul 2010 | B2 |
| 7750669 | Spangaro | Jul 2010 | B2 |
| 7755622 | Yvon | Jul 2010 | B2 |
| 7759043 | Tanabe et al. | Jul 2010 | B2 |
| 7768115 | Lee et al. | Aug 2010 | B2 |
| 7772039 | Kerber | Aug 2010 | B2 |
| 7772096 | DeSouza et al. | Aug 2010 | B2 |
| 7774735 | Sood | Aug 2010 | B1 |
| 7776715 | Wells et al. | Aug 2010 | B2 |
| 7777269 | Walker | Aug 2010 | B2 |
| 7777330 | Pelley et al. | Aug 2010 | B2 |
| 7786460 | Lung et al. | Aug 2010 | B2 |
| 7786535 | Abou-Khalil et al. | Aug 2010 | B2 |
| 7790524 | Abadeer et al. | Sep 2010 | B2 |
| 7795619 | Hara | Sep 2010 | B2 |
| 7799675 | Lee | Sep 2010 | B2 |
| 7800099 | Yamazaki et al. | Sep 2010 | B2 |
| 7800148 | Lee et al. | Sep 2010 | B2 |
| 7800163 | Izumi et al. | Sep 2010 | B2 |
| 7800199 | Oh et al. | Sep 2010 | B2 |
| 7816721 | Yamazaki | Oct 2010 | B2 |
| 7843718 | Koh et al. | Nov 2010 | B2 |
| 7846814 | Lee | Dec 2010 | B2 |
| 7851844 | Van der Zanden et al. | Dec 2010 | B2 |
| 7863095 | Sasaki et al. | Jan 2011 | B2 |
| 7864568 | Fujisaki et al. | Jan 2011 | B2 |
| 7867822 | Lee | Jan 2011 | B2 |
| 7888764 | Lee | Feb 2011 | B2 |
| 7910432 | Tanaka et al. | Mar 2011 | B2 |
| 7915164 | Konevecki et al. | Mar 2011 | B2 |
| 7919845 | Karp | Apr 2011 | B2 |
| 7965102 | Bauer et al. | Jun 2011 | B1 |
| 7968965 | Kim | Jun 2011 | B2 |
| 7969193 | Wu et al. | Jun 2011 | B1 |
| 7973314 | Yang | Jul 2011 | B2 |
| 7982250 | Yamazaki et al. | Jul 2011 | B2 |
| 7983065 | Samachisa | Jul 2011 | B2 |
| 8008732 | Kiyotoshi | Aug 2011 | B2 |
| 8013399 | Thomas et al. | Sep 2011 | B2 |
| 8014166 | Yazdani | Sep 2011 | B2 |
| 8014195 | Okhonin et al. | Sep 2011 | B2 |
| 8022493 | Bang | Sep 2011 | B2 |
| 8030780 | Kirby et al. | Oct 2011 | B2 |
| 8031544 | Kim et al. | Oct 2011 | B2 |
| 8032857 | McIlrath | Oct 2011 | B2 |
| 8044448 | Kamigaichi et al. | Oct 2011 | B2 |
| 8044464 | Yamazaki et al. | Oct 2011 | B2 |
| 8068364 | Maejima | Nov 2011 | B2 |
| 8106520 | Keeth et al. | Jan 2012 | B2 |
| 8107276 | Breitwisch et al. | Jan 2012 | B2 |
| 8129256 | Farooq et al. | Mar 2012 | B2 |
| 8129258 | Hosier et al. | Mar 2012 | B2 |
| 8130547 | Widjaja et al. | Mar 2012 | B2 |
| 8136071 | Solomon | Mar 2012 | B2 |
| 8138502 | Nakamura et al. | Mar 2012 | B2 |
| 8153520 | Chandrashekar | Apr 2012 | B1 |
| 8158515 | Farooq et al. | Apr 2012 | B2 |
| 8178919 | Fujiwara et al. | May 2012 | B2 |
| 8183630 | Batude et al. | May 2012 | B2 |
| 8184463 | Saen et al. | May 2012 | B2 |
| 8185685 | Selinger | May 2012 | B2 |
| 8203187 | Lung et al. | Jun 2012 | B2 |
| 8208279 | Lue | Jun 2012 | B2 |
| 8209649 | MoIlrath | Jun 2012 | B2 |
| 8228684 | Losavio et al. | Jul 2012 | B2 |
| 8266560 | McIlrath | Aug 2012 | B2 |
| 8264065 | Su et al. | Sep 2012 | B2 |
| 8288816 | Komori et al. | Oct 2012 | B2 |
| 8294199 | Yahashi et al. | Oct 2012 | B2 |
| 8324680 | Izumi et al. | Dec 2012 | B2 |
| 8338882 | Tanaka et al. | Dec 2012 | B2 |
| 8343851 | Kim et al. | Jan 2013 | B2 |
| 8354308 | Kang et al. | Jan 2013 | B2 |
| 8355273 | Liu | Jan 2013 | B2 |
| 8374033 | Kito et al. | Feb 2013 | B2 |
| 8426294 | Lung et al. | Apr 2013 | B2 |
| 8432719 | Lue | Apr 2013 | B2 |
| 8432751 | Hafez | Apr 2013 | B2 |
| 8455941 | Ishihara et al. | Jun 2013 | B2 |
| 8470689 | Desplobain et al. | Jun 2013 | B2 |
| 8497512 | Nakamura et al. | Jul 2013 | B2 |
| 8501564 | Suzawa | Aug 2013 | B2 |
| 8507972 | Oota et al. | Aug 2013 | B2 |
| 8508994 | Okhonin | Aug 2013 | B2 |
| 8513725 | Sakuma et al. | Aug 2013 | B2 |
| 8514623 | Widjaja et al. | Aug 2013 | B2 |
| 8516408 | Dell | Aug 2013 | B2 |
| 8566762 | Morimoto et al. | Aug 2013 | B2 |
| 8525342 | Chandrasekaran | Oct 2013 | B2 |
| 8546956 | Nguyen | Oct 2013 | B2 |
| 8603888 | Liu | Dec 2013 | B2 |
| 8611388 | Krasulick et al. | Dec 2013 | B2 |
| 8619490 | Yu | Dec 2013 | B2 |
| 8630326 | Krasulick et al. | Jan 2014 | B2 |
| 8643162 | Madurawe | Feb 2014 | B2 |
| 8650516 | MoIlrath | Feb 2014 | B2 |
| 8654584 | Kim et al. | Feb 2014 | B2 |
| 8679861 | Bose | Mar 2014 | B2 |
| 8736068 | Bartley et al. | May 2014 | B2 |
| 8773562 | Fan | Jul 2014 | B1 |
| 8775998 | Morimoto | Jul 2014 | B2 |
| 8796777 | Song et al. | Aug 2014 | B2 |
| 8824183 | Samachisa et al. | Sep 2014 | B2 |
| 8841777 | Farooq | Sep 2014 | B2 |
| 8853785 | Augendre | Oct 2014 | B2 |
| 8896054 | Sakuma et al. | Nov 2014 | B2 |
| 8928119 | Leedy | Jan 2015 | B2 |
| 8971114 | Kang | Mar 2015 | B2 |
| 9105689 | Fanelli | Aug 2015 | B1 |
| 9172008 | Hwang | Oct 2015 | B2 |
| 9227456 | Chien | Jan 2016 | B2 |
| 9230973 | Pachamuthu et al. | Jan 2016 | B2 |
| 9269608 | Fanelli | Feb 2016 | B2 |
| 9334582 | See | May 2016 | B2 |
| 9391090 | Manorotkul et al. | Jul 2016 | B2 |
| 9472568 | Shin et al. | Oct 2016 | B2 |
| 9564450 | Sakuma et al. | Feb 2017 | B2 |
| 9570683 | Jo | Feb 2017 | B1 |
| 9589982 | Cheng et al. | Mar 2017 | B1 |
| 9595530 | Zhou | Mar 2017 | B1 |
| 9627287 | Engelhardt et al. | Apr 2017 | B2 |
| 9673257 | Takaki | Jun 2017 | B1 |
| 9997530 | Yon et al. | Jun 2018 | B2 |
| 10199354 | Modi et al. | Feb 2019 | B2 |
| 10666264 | Brewer | May 2020 | B1 |
| 20010000005 | Forrest et al. | Mar 2001 | A1 |
| 20010014391 | Forrest et al. | Aug 2001 | A1 |
| 20010028059 | Emma et al. | Oct 2001 | A1 |
| 20020024140 | Nakajima et al. | Feb 2002 | A1 |
| 20020025604 | Tiwari | Feb 2002 | A1 |
| 20020074668 | Hofstee et al. | Jun 2002 | A1 |
| 20020081823 | Cheung et al. | Jun 2002 | A1 |
| 20020090758 | Henley et al. | Jul 2002 | A1 |
| 20020096681 | Yamazaki et al. | Jul 2002 | A1 |
| 20020113289 | Cordes et al. | Aug 2002 | A1 |
| 20020132465 | Leedy | Sep 2002 | A1 |
| 20020140091 | Callahan | Oct 2002 | A1 |
| 20020141233 | Hosotani et al. | Oct 2002 | A1 |
| 20020153243 | Forrest et al. | Oct 2002 | A1 |
| 20020153569 | Katayama | Oct 2002 | A1 |
| 20020175401 | Huang et al. | Nov 2002 | A1 |
| 20020180069 | Houston | Dec 2002 | A1 |
| 20020190232 | Chason | Dec 2002 | A1 |
| 20020199110 | Kean | Dec 2002 | A1 |
| 20030015713 | Yoo | Jan 2003 | A1 |
| 20030032262 | Dennison et al. | Feb 2003 | A1 |
| 20030059999 | Gonzalez | Mar 2003 | A1 |
| 20030060034 | Beyne et al. | Mar 2003 | A1 |
| 20030061555 | Kamei | Mar 2003 | A1 |
| 20030067043 | Zhang | Apr 2003 | A1 |
| 20030076706 | Andoh | Apr 2003 | A1 |
| 20030102079 | Kalvesten et al. | Jun 2003 | A1 |
| 20030107117 | Antonell et al. | Jun 2003 | A1 |
| 20030113963 | Wurzer | Jun 2003 | A1 |
| 20030119279 | Enquist | Jun 2003 | A1 |
| 20030139011 | Cleeves et al. | Jul 2003 | A1 |
| 20030153163 | Letertre | Aug 2003 | A1 |
| 20030157748 | Kim et al. | Aug 2003 | A1 |
| 20030160888 | Yoshikawa | Aug 2003 | A1 |
| 20030173631 | Murakami | Sep 2003 | A1 |
| 20030206036 | Or-Bach | Nov 2003 | A1 |
| 20030213967 | Forrest et al. | Nov 2003 | A1 |
| 20030224582 | Shimoda et al. | Dec 2003 | A1 |
| 20030224596 | Marxsen et al. | Dec 2003 | A1 |
| 20040007376 | Urdahl et al. | Jan 2004 | A1 |
| 20040014299 | Moriceau et al. | Jan 2004 | A1 |
| 20040033676 | Coronel et al. | Feb 2004 | A1 |
| 20040036126 | Chau et al. | Feb 2004 | A1 |
| 20040047539 | Okubora et al. | Mar 2004 | A1 |
| 20040061176 | Takafuji et al. | Apr 2004 | A1 |
| 20040113207 | Hsu et al. | Jun 2004 | A1 |
| 20040143797 | Nguyen | Jul 2004 | A1 |
| 20040150068 | Leedy | Aug 2004 | A1 |
| 20040150070 | Okada | Aug 2004 | A1 |
| 20040152272 | Fladre et al. | Aug 2004 | A1 |
| 20040155301 | Zhang | Aug 2004 | A1 |
| 20040156172 | Lin et al. | Aug 2004 | A1 |
| 20040156233 | Bhattacharyya | Aug 2004 | A1 |
| 20040164425 | Urakawa | Aug 2004 | A1 |
| 20040166649 | Bressot et al. | Aug 2004 | A1 |
| 20040174732 | Morimoto | Sep 2004 | A1 |
| 20040175902 | Rayssac et al. | Sep 2004 | A1 |
| 20040178819 | New | Sep 2004 | A1 |
| 20040195572 | Kato et al. | Oct 2004 | A1 |
| 20040219765 | Reif et al. | Nov 2004 | A1 |
| 20040229444 | Couillard | Nov 2004 | A1 |
| 20040259312 | Schlosser et al. | Dec 2004 | A1 |
| 20040262635 | Lee | Dec 2004 | A1 |
| 20040262772 | Ramanathan et al. | Dec 2004 | A1 |
| 20050003592 | Jones | Jan 2005 | A1 |
| 20050010725 | Eilert | Jan 2005 | A1 |
| 20050023656 | Leedy | Feb 2005 | A1 |
| 20050045919 | Kaeriyama et al. | Mar 2005 | A1 |
| 20050067620 | Chan et al. | Mar 2005 | A1 |
| 20050067625 | Hata | Mar 2005 | A1 |
| 20050073060 | Datta et al. | Apr 2005 | A1 |
| 20050082526 | Bedell et al. | Apr 2005 | A1 |
| 20050098822 | Mathew | May 2005 | A1 |
| 20050110041 | Boutros et al. | May 2005 | A1 |
| 20050121676 | Fried et al. | Jun 2005 | A1 |
| 20050121789 | Madurawe | Jun 2005 | A1 |
| 20050130351 | Leedy | Jun 2005 | A1 |
| 20050130429 | Rayssac et al. | Jun 2005 | A1 |
| 20050148137 | Brask et al. | Jul 2005 | A1 |
| 20050176174 | Leedy | Aug 2005 | A1 |
| 20050218521 | Lee | Oct 2005 | A1 |
| 20050225237 | Winters | Oct 2005 | A1 |
| 20050266659 | Ghyselen et al. | Dec 2005 | A1 |
| 20050273749 | Kirk | Dec 2005 | A1 |
| 20050280061 | Lee | Dec 2005 | A1 |
| 20050280090 | Anderson et al. | Dec 2005 | A1 |
| 20050280154 | Lee | Dec 2005 | A1 |
| 20050280155 | Lee | Dec 2005 | A1 |
| 20050280156 | Lee | Dec 2005 | A1 |
| 20050282019 | Fukushima et al. | Dec 2005 | A1 |
| 20060014331 | Tang et al. | Jan 2006 | A1 |
| 20060024923 | Sarma et al. | Feb 2006 | A1 |
| 20060033110 | Alam et al. | Feb 2006 | A1 |
| 20060033124 | Or-Bach et al. | Feb 2006 | A1 |
| 20060043367 | Chang et al. | Feb 2006 | A1 |
| 20060049449 | Iino | Mar 2006 | A1 |
| 20060065953 | Kim et al. | Mar 2006 | A1 |
| 20060067122 | Verhoeven | Mar 2006 | A1 |
| 20060071322 | Kitamura | Apr 2006 | A1 |
| 20060071332 | Speers | Apr 2006 | A1 |
| 20060083280 | Tauzin et al. | Apr 2006 | A1 |
| 20060108613 | Song | May 2006 | A1 |
| 20060108627 | Choi et al. | May 2006 | A1 |
| 20060113522 | Lee et al. | Jun 2006 | A1 |
| 20060118935 | Kamiyama et al. | Jun 2006 | A1 |
| 20060121690 | Pogge et al. | Jun 2006 | A1 |
| 20060150137 | Madurawe | Jul 2006 | A1 |
| 20060158511 | Harrold | Jul 2006 | A1 |
| 20060170046 | Hara | Aug 2006 | A1 |
| 20060179417 | Madurawe | Aug 2006 | A1 |
| 20060181202 | Liao et al. | Aug 2006 | A1 |
| 20060189095 | Ghyselen et al. | Aug 2006 | A1 |
| 20060194401 | Hu et al. | Aug 2006 | A1 |
| 20060195729 | Huppenthal et al. | Aug 2006 | A1 |
| 20060207087 | Jafri et al. | Sep 2006 | A1 |
| 20060224814 | Kim et al. | Oct 2006 | A1 |
| 20060237777 | Choi | Oct 2006 | A1 |
| 20060249859 | Eiles et al. | Nov 2006 | A1 |
| 20060275962 | Lee | Dec 2006 | A1 |
| 20070004150 | Huang | Jan 2007 | A1 |
| 20070008013 | Fijany et al. | Jan 2007 | A1 |
| 20070014508 | Chen et al. | Jan 2007 | A1 |
| 20070035329 | Madurawe | Feb 2007 | A1 |
| 20070063259 | Derderian et al. | Mar 2007 | A1 |
| 20070072391 | Pocas et al. | Mar 2007 | A1 |
| 20070076509 | Zhang | Apr 2007 | A1 |
| 20070077694 | Lee | Apr 2007 | A1 |
| 20070077743 | Rao et al. | Apr 2007 | A1 |
| 20070090416 | Doyle et al. | Apr 2007 | A1 |
| 20070102737 | Kashiwabara et al. | May 2007 | A1 |
| 20070103191 | Sugawara et al. | May 2007 | A1 |
| 20070108523 | Ogawa et al. | May 2007 | A1 |
| 20070109831 | RaghuRam | May 2007 | A1 |
| 20070111386 | Kim et al. | May 2007 | A1 |
| 20070111406 | Joshi et al. | May 2007 | A1 |
| 20070132049 | Stipe | Jun 2007 | A1 |
| 20070132369 | Forrest et al. | Jun 2007 | A1 |
| 20070135013 | Faris | Jun 2007 | A1 |
| 20070141781 | Park | Jun 2007 | A1 |
| 20070158659 | Bensce | Jul 2007 | A1 |
| 20070158831 | Cha et al. | Jul 2007 | A1 |
| 20070176214 | Kwon et al. | Aug 2007 | A1 |
| 20070187775 | Okhonin et al. | Aug 2007 | A1 |
| 20070190746 | Ito et al. | Aug 2007 | A1 |
| 20070194453 | Chakraborty et al. | Aug 2007 | A1 |
| 20070206408 | Schwerin | Sep 2007 | A1 |
| 20070210336 | Madurawe | Sep 2007 | A1 |
| 20070211535 | Kim | Sep 2007 | A1 |
| 20070215903 | Sakamoto et al. | Sep 2007 | A1 |
| 20070218622 | Lee et al. | Sep 2007 | A1 |
| 20070228383 | Bernstein et al. | Oct 2007 | A1 |
| 20070252201 | Kito et al. | Nov 2007 | A1 |
| 20070252203 | Zhu et al. | Nov 2007 | A1 |
| 20070262457 | Lin | Nov 2007 | A1 |
| 20070275520 | Suzuki | Nov 2007 | A1 |
| 20070281439 | Bedell et al. | Dec 2007 | A1 |
| 20070283298 | Bernstein et al. | Dec 2007 | A1 |
| 20070287224 | Alam et al. | Dec 2007 | A1 |
| 20070296073 | Wu | Dec 2007 | A1 |
| 20070297232 | Iwata | Dec 2007 | A1 |
| 20080001204 | Lee | Jan 2008 | A1 |
| 20080003818 | Seidel et al. | Jan 2008 | A1 |
| 20080030228 | Amarilio | Feb 2008 | A1 |
| 20080032463 | Lee | Feb 2008 | A1 |
| 20080038902 | Lee | Feb 2008 | A1 |
| 20080048239 | Huo | Feb 2008 | A1 |
| 20080048327 | Lee | Feb 2008 | A1 |
| 20080054359 | Yang et al. | Mar 2008 | A1 |
| 20080067573 | Jang et al. | Mar 2008 | A1 |
| 20080070340 | Borrelli et al. | Mar 2008 | A1 |
| 20080072182 | He et al. | Mar 2008 | A1 |
| 20080099780 | Tran | May 2008 | A1 |
| 20080099819 | Kito et al. | May 2008 | A1 |
| 20080108171 | Rogers et al. | May 2008 | A1 |
| 20080123418 | Widjaja | May 2008 | A1 |
| 20080124845 | Yu et al. | May 2008 | A1 |
| 20080128745 | Mastro et al. | Jun 2008 | A1 |
| 20080128780 | Nishihara | Jun 2008 | A1 |
| 20080135949 | Lo et al. | Jun 2008 | A1 |
| 20080136455 | Diamant et al. | Jun 2008 | A1 |
| 20080142937 | Chen et al. | Jun 2008 | A1 |
| 20080142959 | DeMulder et al. | Jun 2008 | A1 |
| 20080143379 | Norman | Jun 2008 | A1 |
| 20080150579 | Madurawe | Jun 2008 | A1 |
| 20080160431 | Scott et al. | Jul 2008 | A1 |
| 20080160726 | Lim et al. | Jul 2008 | A1 |
| 20080165521 | Bernstein et al. | Jul 2008 | A1 |
| 20080175032 | Tanaka et al. | Jul 2008 | A1 |
| 20080179678 | Dyer et al. | Jul 2008 | A1 |
| 20080180132 | Ishikawa | Jul 2008 | A1 |
| 20080185648 | Jeong | Aug 2008 | A1 |
| 20080191247 | Yin et al. | Aug 2008 | A1 |
| 20080191312 | Oh et al. | Aug 2008 | A1 |
| 20080194068 | Temmler et al. | Aug 2008 | A1 |
| 20080203452 | Moon et al. | Aug 2008 | A1 |
| 20080213982 | Park et al. | Sep 2008 | A1 |
| 20080220558 | Zehavi et al. | Sep 2008 | A1 |
| 20080220565 | Hsu et al. | Sep 2008 | A1 |
| 20080224260 | Schmit et al. | Sep 2008 | A1 |
| 20080237591 | Leedy | Oct 2008 | A1 |
| 20080239818 | Mokhlesi | Oct 2008 | A1 |
| 20080242028 | Mokhlesi | Oct 2008 | A1 |
| 20080248618 | Ahn et al. | Oct 2008 | A1 |
| 20080251862 | Fonash et al. | Oct 2008 | A1 |
| 20080254561 | Yoo | Oct 2008 | A2 |
| 20080254572 | Leedy | Oct 2008 | A1 |
| 20080254623 | Chan | Oct 2008 | A1 |
| 20080261378 | Yao et al. | Oct 2008 | A1 |
| 20080266960 | Kuo | Oct 2008 | A1 |
| 20080272492 | Tsang | Nov 2008 | A1 |
| 20080277778 | Furman et al. | Nov 2008 | A1 |
| 20080283873 | Yang | Nov 2008 | A1 |
| 20080283875 | Mukasa et al. | Nov 2008 | A1 |
| 20080284611 | Leedy | Nov 2008 | A1 |
| 20080296681 | Georgakos et al. | Dec 2008 | A1 |
| 20080315253 | Yuan | Dec 2008 | A1 |
| 20080315351 | Kakehata | Dec 2008 | A1 |
| 20090001469 | Yoshida et al. | Jan 2009 | A1 |
| 20090001504 | Takei et al. | Jan 2009 | A1 |
| 20090016716 | Ishida | Jan 2009 | A1 |
| 20090026541 | Chung | Jan 2009 | A1 |
| 20090026618 | Kim | Jan 2009 | A1 |
| 20090032899 | Irie | Feb 2009 | A1 |
| 20090032951 | Andry et al. | Feb 2009 | A1 |
| 20090039918 | Madurawe | Feb 2009 | A1 |
| 20090052827 | Durfee et al. | Feb 2009 | A1 |
| 20090055789 | McIlrath | Feb 2009 | A1 |
| 20090057879 | Garrou et al. | Mar 2009 | A1 |
| 20090061572 | Hareland et al. | Mar 2009 | A1 |
| 20090064058 | McIlrath | Mar 2009 | A1 |
| 20090065827 | Hwang | Mar 2009 | A1 |
| 20090066365 | Solomon | Mar 2009 | A1 |
| 20090066366 | Solomon | Mar 2009 | A1 |
| 20090070721 | Solomon | Mar 2009 | A1 |
| 20090070727 | Solomon | Mar 2009 | A1 |
| 20090078970 | Yamazaki | Mar 2009 | A1 |
| 20090079000 | Yamazaki et al. | Mar 2009 | A1 |
| 20090080258 | Walker | Mar 2009 | A1 |
| 20090081848 | Erokhin | Mar 2009 | A1 |
| 20090087759 | Matsumoto et al. | Apr 2009 | A1 |
| 20090096009 | Dong et al. | Apr 2009 | A1 |
| 20090096024 | Shingu et al. | Apr 2009 | A1 |
| 20090108318 | Yoon et al. | Apr 2009 | A1 |
| 20090115042 | Koyanagi | May 2009 | A1 |
| 20090128189 | Madurawe et al. | May 2009 | A1 |
| 20090134397 | Yokoi et al. | May 2009 | A1 |
| 20090144669 | Bose et al. | Jun 2009 | A1 |
| 20090144678 | Bose et al. | Jun 2009 | A1 |
| 20090146172 | Pumyea | Jun 2009 | A1 |
| 20090159870 | Lin et al. | Jun 2009 | A1 |
| 20090160482 | Karp et al. | Jun 2009 | A1 |
| 20090161401 | Bigler et al. | Jun 2009 | A1 |
| 20090162993 | Yui et al. | Jun 2009 | A1 |
| 20090166627 | Han | Jul 2009 | A1 |
| 20090174018 | Dungan | Jul 2009 | A1 |
| 20090179268 | Abou-Khalil et al. | Jul 2009 | A1 |
| 20090185407 | Park | Jul 2009 | A1 |
| 20090194152 | Liu et al. | Aug 2009 | A1 |
| 20090194768 | Leedy | Aug 2009 | A1 |
| 20090194829 | Chung | Aug 2009 | A1 |
| 20090194836 | Kim | Aug 2009 | A1 |
| 20090204933 | Rezgui | Aug 2009 | A1 |
| 20090212317 | Kolodin et al. | Aug 2009 | A1 |
| 20090218627 | Zhu | Sep 2009 | A1 |
| 20090221110 | Lee et al. | Sep 2009 | A1 |
| 20090224330 | Hong | Sep 2009 | A1 |
| 20090224364 | Oh et al. | Sep 2009 | A1 |
| 20090230462 | Tanaka et al. | Sep 2009 | A1 |
| 20090234331 | Langereis et al. | Sep 2009 | A1 |
| 20090236749 | Otemba et al. | Sep 2009 | A1 |
| 20090242893 | Tomiyasu | Oct 2009 | A1 |
| 20090242935 | Fitzgerald | Oct 2009 | A1 |
| 20090250686 | Sato et al. | Oct 2009 | A1 |
| 20090262572 | Krusin-Elbaum | Oct 2009 | A1 |
| 20090262583 | Lue | Oct 2009 | A1 |
| 20090263942 | Ohnuma et al. | Oct 2009 | A1 |
| 20090267233 | Lee | Oct 2009 | A1 |
| 20090268983 | Stone et al. | Oct 2009 | A1 |
| 20090272989 | Shum et al. | Nov 2009 | A1 |
| 20090290434 | Kurjanowicz | Nov 2009 | A1 |
| 20090294822 | Batude et al. | Dec 2009 | A1 |
| 20090294836 | Kiyotoshi | Dec 2009 | A1 |
| 20090294861 | Thomas et al. | Dec 2009 | A1 |
| 20090294990 | Ishino et al. | Dec 2009 | A1 |
| 20090302294 | Kim | Dec 2009 | A1 |
| 20090302387 | Joshi et al. | Dec 2009 | A1 |
| 20090302394 | Fujita | Dec 2009 | A1 |
| 20090309152 | Knoefler et al. | Dec 2009 | A1 |
| 20090315095 | Kim | Dec 2009 | A1 |
| 20090317950 | Okihara | Dec 2009 | A1 |
| 20090321830 | Maly | Dec 2009 | A1 |
| 20090321853 | Cheng | Dec 2009 | A1 |
| 20090321948 | Wang et al. | Dec 2009 | A1 |
| 20090325343 | Lee | Dec 2009 | A1 |
| 20100001282 | Mieno | Jan 2010 | A1 |
| 20100013049 | Tanaka | Jan 2010 | A1 |
| 20100025766 | Nuttinck et al. | Feb 2010 | A1 |
| 20100025825 | DeGraw et al. | Feb 2010 | A1 |
| 20100031217 | Sinha et al. | Feb 2010 | A1 |
| 20100032635 | Schwerin | Feb 2010 | A1 |
| 20100038699 | Katsumata et al. | Feb 2010 | A1 |
| 20100038743 | Lee | Feb 2010 | A1 |
| 20100045849 | Yamasaki | Feb 2010 | A1 |
| 20100052134 | Werner et al. | Mar 2010 | A1 |
| 20100058580 | Yazdani | Mar 2010 | A1 |
| 20100059796 | Scheuerlein | Mar 2010 | A1 |
| 20100059864 | Mahler et al. | Mar 2010 | A1 |
| 20100078770 | Purushothaman et al. | Apr 2010 | A1 |
| 20100081232 | Furman et al. | Apr 2010 | A1 |
| 20100089627 | Huang et al. | Apr 2010 | A1 |
| 20100090188 | Fatasuyama | Apr 2010 | A1 |
| 20100112753 | Lee | May 2010 | A1 |
| 20100112810 | Lee et al. | May 2010 | A1 |
| 20100117048 | Lung et al. | May 2010 | A1 |
| 20100123202 | Hofmann | May 2010 | A1 |
| 20100123480 | Kitada et al. | May 2010 | A1 |
| 20100133695 | Lee | Jun 2010 | A1 |
| 20100133704 | Marimuthu et al. | Jun 2010 | A1 |
| 20100137143 | Rothberg et al. | Jun 2010 | A1 |
| 20100139836 | Horikoshi | Jun 2010 | A1 |
| 20100140790 | Setiadi et al. | Jun 2010 | A1 |
| 20100155932 | Gambino | Jun 2010 | A1 |
| 20100157117 | Wang | Jun 2010 | A1 |
| 20100159650 | Song | Jun 2010 | A1 |
| 20100181600 | Law | Jul 2010 | A1 |
| 20100190334 | Lee | Jul 2010 | A1 |
| 20100193884 | Park et al. | Aug 2010 | A1 |
| 20100193964 | Farooq et al. | Aug 2010 | A1 |
| 20100219392 | Awaya | Sep 2010 | A1 |
| 20100221867 | Bedell et al. | Sep 2010 | A1 |
| 20100224876 | Zhu | Sep 2010 | A1 |
| 20100224915 | Kawashima et al. | Sep 2010 | A1 |
| 20100225002 | Law et al. | Sep 2010 | A1 |
| 20100232200 | Shepard | Sep 2010 | A1 |
| 20100252934 | Law | Oct 2010 | A1 |
| 20100264551 | Farooq | Oct 2010 | A1 |
| 20100276662 | Colinge | Nov 2010 | A1 |
| 20100289144 | Farooq | Nov 2010 | A1 |
| 20100297844 | Yelehanka | Nov 2010 | A1 |
| 20100307572 | Bedell et al. | Dec 2010 | A1 |
| 20100308211 | Cho et al. | Dec 2010 | A1 |
| 20100308863 | Gliese et al. | Dec 2010 | A1 |
| 20100320514 | Tredwell | Dec 2010 | A1 |
| 20100320526 | Kidoh et al. | Dec 2010 | A1 |
| 20100330728 | McCarten | Dec 2010 | A1 |
| 20100330752 | Jeong | Dec 2010 | A1 |
| 20110001172 | Lee | Jan 2011 | A1 |
| 20110003438 | Lee | Jan 2011 | A1 |
| 20110024724 | Frolov et al. | Feb 2011 | A1 |
| 20110026263 | Xu | Feb 2011 | A1 |
| 20110027967 | Beyne | Feb 2011 | A1 |
| 20110037052 | Schmidt et al. | Feb 2011 | A1 |
| 20110042696 | Smith et al. | Feb 2011 | A1 |
| 20110049336 | Matsunuma | Mar 2011 | A1 |
| 20110050125 | Medendorp et al. | Mar 2011 | A1 |
| 20110053332 | Lee | Mar 2011 | A1 |
| 20110101537 | Barth et al. | May 2011 | A1 |
| 20110102014 | Madurawe | May 2011 | A1 |
| 20110111560 | Purushothaman | May 2011 | A1 |
| 20110115023 | Cheng | May 2011 | A1 |
| 20110128777 | Yamazaki | Jun 2011 | A1 |
| 20110134683 | Yamazaki | Jun 2011 | A1 |
| 20110143506 | Lee | Jun 2011 | A1 |
| 20110147791 | Norman et al. | Jun 2011 | A1 |
| 20110147849 | Augendre et al. | Jun 2011 | A1 |
| 20110159635 | Doan et al. | Jun 2011 | A1 |
| 20110170331 | Oh | Jul 2011 | A1 |
| 20110204917 | O'Neill | Aug 2011 | A1 |
| 20110221022 | Toda | Sep 2011 | A1 |
| 20110222356 | Banna | Sep 2011 | A1 |
| 20110227158 | Zhu | Sep 2011 | A1 |
| 20110241082 | Bernstein et al. | Oct 2011 | A1 |
| 20110284946 | Kiyotoshi | Nov 2011 | A1 |
| 20110284992 | Zhu | Nov 2011 | A1 |
| 20110286283 | Lung et al. | Nov 2011 | A1 |
| 20110304765 | Yogo et al. | Dec 2011 | A1 |
| 20110309432 | Ishihara et al. | Dec 2011 | A1 |
| 20110314437 | McIlrath | Dec 2011 | A1 |
| 20120001184 | Ha et al. | Jan 2012 | A1 |
| 20120003815 | Lee | Jan 2012 | A1 |
| 20120013013 | Sadaka et al. | Jan 2012 | A1 |
| 20120025388 | Law et al. | Feb 2012 | A1 |
| 20120032250 | Son et al. | Feb 2012 | A1 |
| 20120034759 | Sakaguchi et al. | Feb 2012 | A1 |
| 20120063090 | Hsiao et al. | Mar 2012 | A1 |
| 20120074466 | Setiadi et al. | Mar 2012 | A1 |
| 20120086100 | Andry | Apr 2012 | A1 |
| 20120126197 | Chung | May 2012 | A1 |
| 20120146193 | Stuber et al. | Jun 2012 | A1 |
| 20120161310 | Brindle et al. | Jun 2012 | A1 |
| 20120169319 | Dennard | Jul 2012 | A1 |
| 20120178211 | Hebert | Jul 2012 | A1 |
| 20120181654 | Lue | Jul 2012 | A1 |
| 20120182801 | Lue | Jul 2012 | A1 |
| 20120187444 | Oh | Jul 2012 | A1 |
| 20120193785 | Lin | Aug 2012 | A1 |
| 20120241919 | Mitani | Sep 2012 | A1 |
| 20120286822 | Madurawe | Nov 2012 | A1 |
| 20120304142 | Morimoto | Nov 2012 | A1 |
| 20120317528 | McIlrath | Dec 2012 | A1 |
| 20120319728 | Madurawe | Dec 2012 | A1 |
| 20130026663 | Radu et al. | Jan 2013 | A1 |
| 20130037802 | England | Feb 2013 | A1 |
| 20130049796 | Pang | Feb 2013 | A1 |
| 20130070506 | Kajigaya | Mar 2013 | A1 |
| 20130082235 | Gu et al. | Apr 2013 | A1 |
| 20130097574 | Balabanov et al. | Apr 2013 | A1 |
| 20130100743 | Lue | Apr 2013 | A1 |
| 20130128666 | Avila | May 2013 | A1 |
| 20130187720 | Ishii | Jul 2013 | A1 |
| 20130193550 | Sklenard et al. | Aug 2013 | A1 |
| 20130196500 | Batude et al. | Aug 2013 | A1 |
| 20130203248 | Ernst et al. | Aug 2013 | A1 |
| 20130207243 | Fuergut et al. | Aug 2013 | A1 |
| 20130263393 | Mazumder | Oct 2013 | A1 |
| 20130337601 | Kapur | Dec 2013 | A1 |
| 20140015136 | Gan et al. | Jan 2014 | A1 |
| 20140030871 | Arriagada et al. | Jan 2014 | A1 |
| 20140035616 | Oda et al. | Feb 2014 | A1 |
| 20140048867 | Toh | Feb 2014 | A1 |
| 20140099761 | Kim et al. | Apr 2014 | A1 |
| 20140103959 | Andreev | Apr 2014 | A1 |
| 20140117413 | Madurawe | May 2014 | A1 |
| 20140120695 | Ohtsuki | May 2014 | A1 |
| 20140131885 | Samadi et al. | May 2014 | A1 |
| 20140137061 | McIlrath | May 2014 | A1 |
| 20140145347 | Samadi et al. | May 2014 | A1 |
| 20140146630 | Xie et al. | May 2014 | A1 |
| 20140149958 | Samadi et al. | May 2014 | A1 |
| 20140151774 | Rhie | Jun 2014 | A1 |
| 20140191357 | Lee | Jul 2014 | A1 |
| 20140225218 | Du | Aug 2014 | A1 |
| 20140225235 | Du | Aug 2014 | A1 |
| 20140252306 | Du | Sep 2014 | A1 |
| 20140253196 | Du et al. | Sep 2014 | A1 |
| 20140264228 | Toh | Sep 2014 | A1 |
| 20140357054 | Son et al. | Dec 2014 | A1 |
| 20150021785 | Lin | Jan 2015 | A1 |
| 20150034898 | Wang | Feb 2015 | A1 |
| 20150243887 | Saitoh | Aug 2015 | A1 |
| 20150255418 | Gowda | Sep 2015 | A1 |
| 20150279829 | Kuo | Oct 2015 | A1 |
| 20150340369 | Lue | Nov 2015 | A1 |
| 20160049201 | Lue | Feb 2016 | A1 |
| 20160086970 | Peng | Mar 2016 | A1 |
| 20160104780 | Mauder | Apr 2016 | A1 |
| 20160133603 | Ahn | May 2016 | A1 |
| 20160141299 | Hong | May 2016 | A1 |
| 20160141334 | Takaki | May 2016 | A1 |
| 20160307952 | Huang | Oct 2016 | A1 |
| 20160343687 | Vadhavkar | Nov 2016 | A1 |
| 20170069601 | Park | Mar 2017 | A1 |
| 20170092371 | Harari | Mar 2017 | A1 |
| 20170098596 | Lin | Apr 2017 | A1 |
| 20170148517 | Harari | May 2017 | A1 |
| 20170179146 | Park | Jun 2017 | A1 |
| 20170221900 | Widjaja | Aug 2017 | A1 |
| 20170278858 | Walker et al. | Sep 2017 | A1 |
| 20180090219 | Harari | Mar 2018 | A1 |
| 20180090368 | Eun-Jeong et al. | Mar 2018 | A1 |
| 20180108416 | Harari | Apr 2018 | A1 |
| 20180294284 | Tarakji | Oct 2018 | A1 |
| 20190006009 | Harari | Jan 2019 | A1 |
| 20190043836 | Fastow et al. | Feb 2019 | A1 |
| 20190067327 | Herner | Feb 2019 | A1 |
| 20190157296 | Harari et al. | May 2019 | A1 |
| 20200020408 | Norman et al. | Jan 2020 | A1 |
| 20200020718 | Harari et al. | Jan 2020 | A1 |
| 20200051990 | Harari et al. | Feb 2020 | A1 |
| 20200105773 | Morris et al. | Apr 2020 | A1 |
| 20200203328 | Park | Jun 2020 | A1 |
| 20200227123 | Salahuddin et al. | Jul 2020 | A1 |
| 20200243486 | Quader et al. | Jul 2020 | A1 |
| 20200328176 | Liu | Oct 2020 | A1 |
| Number | Date | Country |
|---|---|---|
| 1267594 | Dec 2002 | EP |
| PCTUS2008063483 | May 2008 | WO |
| Entry |
|---|
| Colinge, J. P., et al., “Nanowire transistors without Junctions”, Nature Nanotechnology, Feb. 21, 2010, pp. 1-5. |
| Kim, J.Y., et al., “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 11-12, Jun. 10-12, 2003. |
| Kim, J.Y., et al., “The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond,” 2005 IEEE VLSI-TSA International Symposium, pp. 33-34, Apr. 25-27, 2005. |
| Abramovici, Breuer and Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990, pp. 432-447. |
| Yonehara, T., et al., “ELTRAN: SOI-Epi Wafer by Epitaxial Layer transfer from porous Silicon”, the 198th Electrochemical Society Meeting, abstract No. 438 (2000). |
| Yonehara, T., et al., “Eltran®, Novel SOI Wafer Technology,” JSAP International, Jul. 2001, pp. 10-16, No. 4. |
| Suk, S. D., et al., “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” in Proc. IEDM Tech. Dig., 2005, pp. 717-720. |
| Bangsaruntip, S., et al., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 297-300, Dec. 7-9, 2009. |
| Burr, G. W., et al., “Overview of candidate device technologies for storage-class memory,” IBM Journal of Research and Development , vol. 52, No. 4.5, pp. 449-464, Jul. 2008. |
| Bez, R., et al., “Introduction to Flash memory,” Proceedings IEEE, 91(4), 489-502 (2003). |
| Auth, C., et al., “45nm High-k+Metal Gate Strain-Enchanced Transistors,” Symposium on VLSI Technology Digest of Technical Papers, 2008, pp. 128-129. |
| Jan, C. H., et al., “A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications,” IEEE International Electronic Devices Meeting (IEDM), Dec. 7-9, 2009, pp. 1-4. |
| Mistry, K., “A 45nm Logic Technology With High-K+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-Free Packaging,” Electron Devices Meeting, 2007, IEDM 2007, IEEE International, Dec. 10-12, 2007, p. 247. |
| Ragnarsson, L., et al., “Ultralow-EOT (5 Å) Gate-First and Gate-Last High Performance CMOS Achieved by Gate-Electrode Optimization,” IEDM Tech. Dig., pp. 663-666, 2009. |
| Sen, P & Kim, C.J., “A Fast Liquid-Metal Droplet Microswitch Using EWOD-Driven Contact-Line Sliding”, Journal of Microelectromechanical Systems, vol. 18, No. 1, Feb. 2009, pp. 174-185. |
| Iwai, H., et.al., “NiSi Salicide Technology for Scaled CMOS,” Microelectronic Engineering, 60 (2002), pp. 157-169. |
| Froment, B., et.al., “Nickel vs. Cobalt Silicide integration for sub-50nm CMOS”, IMEC ESS Circuits, 2003. pp. 215-219. |
| James, D., “65 and 45-nm Devices—an Overview”, Semicon West, Jul. 2008, paper No. ctr_024377. |
| Davis, J.A., et.al., “Interconnect Limits on Gigascale Integration(GSI) in the 21st Century”, Proc. IEEE, vol. 89, No. 3, pp. 305-324, Mar. 2001. |
| Shino, T., et al., “Floating Body RAM Technology and its Scalability to 32nm Node and Beyond,” Electron Devices Meeting, 2006, IEDM '06, International, pp. 1-4, Dec. 11-13, 2006. |
| Hamamoto, T., et al., “Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond”, Solid-State Electronics, vol. 53, Issue 7, Papers Selected from the 38th European Solid-State Device Research Conference—ESSDERC'08, Jul. 2009, pp. 676-683. |
| Okhonin, S., et al., “New Generation of Z-RAM”, Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp. 925-928, Dec. 10-12, 2007. |
| Henttinen, K. et al., “Mechanically Induced Si Layer Transfer in Hydrogen-Implanted Si Wafers,” Applied Physics Letters, Apr. 24, 2000, p. 2370-2372, vol. 76, No. 17. |
| Lee, C.-W., et al., “Junctionless multigate field-effect transistor,” Applied Physics Letters, vol. 94, pp. 053511-1 to 053511-2, 2009. |
| Park, S. G., et al., “Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate,” International Electron Devices Meeting, IEDM 2004, pp. 515-518, Dec. 13-15, 2004. |
| Kim, J.Y., et al., “S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond,” 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005 pp. 34-35, Jun. 14-16, 2005. |
| Oh, H.J., et al., “High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond,” Solid-State Device Research Conference, ESSDERC 2005. Proceedings of 35th European , pp. 177-180, Sep. 12-16, 2005. |
| Chung, S.-W., et al., “Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology,” 2006 Symposium on VLSI Technology Digest of Technical Papers, pp. 32-33. |
| Lee, M. J., et al., “A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor,” IEEE Transactions on Electron Devices, vol. 54, No. 12, pp. 3325-3335, Dec. 2007. |
| Henttinen, K. et al., “Cold ion-cutting of hydrogen implanted Si,” J. Nucl. Instr. and Meth. in Phys. Res. B, 2002, pp. 761-766, vol. 190. |
| Brumfiel, G., “Solar cells sliced and diced”, May 19, 2010, Nature News. |
| Dragoi, et al., “Plasma-activated wafer bonding: the new low-temperature tool for MEMS fabrication”, Proc. SPIE, vol. 6589, 65890T (2007). |
| Vengurlekar, A., et al., “Mechanism of Dopant Activation Enhancement in Shallow Junctions by Hydrogen”, Proceedings of the Materials Research Society, vol. 864, Spring 2005, E9.28.1-6. |
| Yamada, M. et al., “Phosphor Free High-Luminous-Efficiency White Light-Emitting Diodes Composed of InGaN Multi-Quantum Well,” Japanese Journal of Applied Physics, 2002, pp. L246-L248, vol. 41. |
| Guo, X. et al., “Cascade single-chip phosphor-free white light emitting diodes,” Applied Physics Letters, 2008, pp. 013507-1-013507-3, vol. 92. |
| Takafuji, Y. et al., “Integration of Single Crystal Si TFTs and Circuits on a Large Glass Substrate,” IEEE International Electron Devices Meeting (IEDM), Dec. 7-9, 2009, pp. 1-4. |
| Wierer, J.J. et al., “High-power AlGaInN flip-chip light-emitting diodes,” Applied Physics Letters, May 28, 2001, pp. 3379-3381, vol. 78, No. 22. |
| El-Gamal, A., “Trends in CMOS Image Sensor Technology and Design,” International Electron Devices Meeting Digest of Technical Papers, Dec. 2002. |
| Ahn, S.W., “Fabrication of a 50 nm half-pitch wire grid polarizer using nanoimprint lithography,” Nanotechnology, 2005, pp. 1874-1877, vol. 16, No. 9. |
| Johnson, R.C., “Switching LEDs on and off to enlighten wireless communications,” EE Times, Jun. 2010, last accessed Oct. 11, 2010, <http://www.embeddedinternetdesign.com/design/225402094>. |
| Ohsawa, et al., “Autonomous Refresh of Floating Body Cell (FBC)”, International Electron Device Meeting, 2008, pp. 801-804. |
| Chen, P., et al., “Effects of Hydrogen Implantation Damage on the Performance of InP/InGaAs/InP p-i-n Photodiodes, Transferred on Silicon,” Applied Physics Letters, vol. 94, No. 1, Jan. 2009, pp. 012101-1 to 012101-3. |
| Lee, D., et al., “Single-Crystalline Silicon Micromirrors Actuated by Self-Aligned Vertical Electrostatic Combdrives with Piston-Motion and Rotation Capability,” Sensors and Actuators A114, 2004, pp. 423-428. |
| Shi, X., et al., “Characterization of Low-Temperature Processed Single-Crystalline Silicon Thin-Film Transistor on Glass,” IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 574-576. |
| Chen, W., et al., “InP Layer Transfer with Masked Implantation,” Electrochemical and Solid-State Letters, Issue 12, No. 4, Apr. 2009, H149-150. |
| Feng, J., et al., “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate,” IEEE Electron Device Letters, vol. 27, No. 11, Nov. 2006, pp. 911-913. |
| Zhang, S., et al., “Stacked CMOS Technology on SOI Substrate,” IEEE Electron Device Letters, vol. 25, No. 9, Sep. 2004, pp. 661-663. |
| Brebner, G., “Tooling up for Reconfigurable System Design,” IEE Colloquium on Reconfigurable Systems, 1999, Ref. No. 1999/061, pp. 2/1-2/4. |
| Bae, Y.-D., “A Single-Chip Programmable Platform Based on a Multithreaded Processor and Configurable Logic (Clusters,” 2002 IEEE International Solid-State Circuits Conference, Feb. 3-7, 2002, Digest of Technical Papers, ISSCC, vol. 1, pp. 336-337. |
| Lu, N.C.C., et al., “A Buried-Trench DRAM Cell Using a Self-aligned Epitaxy Over Trench Technology,” Electron Devices Meeting, IEDM '88 Technical Digest, International, 1988, pp. 588-591. |
| Valsamakis, E.A., “Generator for a Custom Statistical Bipolar Transistor Model,” IEEE Journal of Solid-State Circuits, Apr. 1985, pp. 586-589, vol. SC-20, No. 2. |
| Srivastava, P. et al., “Silicon Substrate Removal of GaN DHFETs for enhanced (>1100V) Breakdown Voltage,” Aug. 2010, IEEE Electron Device Letters, vol. 31, No. 8, pp. 851-852. |
| Gosele, U., et al., “Semiconductor Wafer Bonding,” Annual Review of Materials Science, Aug. 1998, pp. 215-241, vol. 28. |
| Spangler, L.J. et al., “A Technology for High Performance Single-Crystal Silicon-on-Insulator Transistors,” IEEE Electron Device Letters, Apr. 1987, pp. 137-139, vol. 8, No. 4. |
| Larrieu, G., et al., “Low Temperature Implementation of Dopant-Segregated Band-edger Metallic S/D junctions in Thin-Body SOI p-MOSFETs”, Proceedings IEDM, 2007, pp. 147-150. |
| Qui, Z., et al., “A Comparative Study of Two Different Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height Lowering”, IEEE Transactions on Electron Devices, vol. 55, No. 1, Jan. 2008, pp. 396-403. |
| Khater, M.H., et al., “High-k/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length”, IEEE Electron Device Letters, vol. 31, No. 4, Apr. 2010, pp. 275-277. |
| Abramovici, M., “In-system silicon validation and debug”, (2008) IEEE Design and Test of Computers, 25 (3), pp. 216-223. |
| Saxena, P., et al., “Repeater Scaling and Its Impact on CAD”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 4, Apr. 2004. |
| Abrmovici, M., et al., A reconfigurable design-for-debug infrastructure for SoCs, (2006) Proceedings—Design Automation Conference, pp. 7-12. |
| Anis, E., et al., “Low cost debug architecture using lossy compression for silicon debug”, (2007) Proceedings of the IEEE/ACM Design, pp. 225-230. |
| Anis, E., et al., “On using lossless compression of debug data in embedded logic analysis”, (2007) Proceedings of the IEEE International Test Conference, paper 18.3, pp. 1-10. |
| Boule, M., et al., “Adding debug enhancements to assertion checkers for hardware emulation and silicon debug”, (2006) Proceedings of the IEEE International Conference on Computer Design, pp. 294-299. |
| Boule, M., et al., “Assertion checkers in verification, silicon debug and in-field diagnosis”, (2007) Proceedings—Eighth International Symposium on Quality Electronic Design, ISQED 2007, pp. 613-618. |
| Burtscher, M., et al., “The VPC trace-compression algorithms”, (2005) IEEE Transactions on Computers, 54 (11), Nov. 2005, pp. 1329-1344. |
| Frieden, B., “Trace port on powerPC 405 cores”, (2007) Electronic Product Design, 28 (6), pp. 12-14. |
| Hopkins, A.B.T., et al., “Debug support for complex systems on-chip: A review”, (2006) IEEE Proceedings: Computers and Digital Techniques, 153 (4), Jul. 2006, pp. 197-207. |
| Hsu, Y.-C., et al., “Visibility enhancement for silicon debug”, (2006) Proceedings—Design Automation Conference, Jul. 24-28, 2006, San Francisco, pp. 13-18. |
| Josephson, D., et al., “The crazy mixed up world of silicon debug”, (2004) Proceedings of the Custom Integrated Circuits Conference, paper 30-1, pp. 665-670. |
| Josephson, D.D., “The manic depression of microprocessor debug”, (2002) IEEE International Test Conference (TC), paper 23.4, pp. 657-663. |
| Ko, H.F., et al., “Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug”, (2009) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28 (2), pp. 285-297. |
| Ko, H.F., et al., “Distributed embedded logic analysis for post-silicon validation of SOCs”, (2008) Proceedings of the IEEE International Test Conference, paper 16.3, pp. 755-763. |
| Ko, H.F., et al., “Functional scan chain design at RTL for skewed-load delay fault testing”, (2004) Proceedings of the Asian Test Symposium, pp. 454-459. |
| Ko, H.F., et al., “Resource-efficient programmable trigger units for post-silicon validation”, (2009) Proceedings of the 14th IEEE European Test Symposium, ETS 2009, pp. 17-22. |
| Liu, X., et al., “On reusing test access mechanisms for debug data transfer in SoC post-silicon validation”, (2008) Proceedings of the Asian Test Symposium, pp. 303-308. |
| Liu, X., et al., “Trace signal selection for visibility enhancement in post-silicon validation”, (2009) Proceedings DATE, pp. 1338-1343. |
| McLaughlin, R., et al., “Automated debug of speed path failures using functional tests”, (2009) Proceedings of the IEEE VLSI Test Symposium, pp. 91-96. |
| Morris, K., “On-Chip Debugging—Built-in Logic Analyzers on your FPGA”, (2004) Journal of FPGA and Structured ASIC, 2 (3). |
| Nicolici, N., et al., “Design-for-debug for post-silicon validation: Can high-level descriptions help?”, (2009) Proceedings—IEEE International High-Level Design Validation and Test Workshop, HLDVT, pp. 172-175. |
| Park, S.-B., et al., “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization”, (2008) Design Automation Conference (DAC08), Jun. 8-13, 2008, Anaheim, CA, USA, pp. 373-378. |
| Park, S.-B., et al., “Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)”, (2009) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28 (10), pp. 1545-1558. |
| Moore, B., et al., “High Throughput Non-contact SiP Testing”, (2007) Proceedings—International Test Conference, paper 12.3. |
| Riley, M.W., et al., “Cell broadband engine debugging for unknown events”, (2007) IEEE Design and Test of Computers, 24 (5), pp. 486-493. |
| Vermeulen, B., “Functional debug techniques for embedded systems”, (2008) IEEE Design and Test of Computers, 25 (3), pp. 208-215. |
| Vermeulen, B., et al., “Automatic Generation of Breakpoint Hardware for Silicon Debug”, Proceeding of the 41st Design Automation Conference, Jun. 7-11, 2004, p. 514-517. |
| Vermeulen, B., et al., “Design for debug: Catching design errors in digital chips”, (2002) IEEE Design and Test of Computers, 19 (3), pp. 37-45. |
| Vermeulen, B., et al., “Core-based scan architecture for silicon debug”, (2002) IEEE International Test Conference (TC), pp. 638-647. |
| Vanrootselaar, G. J., et al., “Silicon debug: scan chains alone are not enough”, (1999) IEEE International Test Conference (TC), pp. 892-902. |
| Kim, G.-S., et al., “A 25-mV-sensitivity 2-GB/s optimum-logic-threshold capacitive-coupling receiver for wireless wafer probing systems”, (2009) IEEE Transactions on Circuits and Systems II: Express Briefs, 56 (9), pp. 709-713. |
| Sellathamby, C.V., et al., “Non-contact wafer probe using wireless probe cards”, (2005) Proceedings—International Test Conference, 2005, pp. 447-452. |
| Jung, S. M., et al., “Soft Error Immune 0.46pm2 SRAM Cell with MIM Node Capacitor by 65nm CMOS Technology for Ultra High Speed SRAM”, IEDM 2003, pp. 289-292. |
| Brillouet, M., “Emerging Technologies on Silicon”, IEDM 2004, pp. 17-24. |
| Meindl, J. D., “Beyond Moore's Law: The Interconnect Era”, IEEE Computing in Science & Engineering, Jan./Feb. 2003, pp. 20-24. |
| Lin, X., et al., “Local Clustering 3-D Stacked CMOS Technology for Interconnect Loading Reduction”, IEEE Transactions on electron Devices, vol. 53, No. 6, Jun. 2006, pp. 1405-1410. |
| He, T., et al., “Controllable Molecular Modulation of Conductivity in Silicon-Based Devices”, J. Am. Chem. Soc. 2009, 131, 10023-10030. |
| Henley, F., “Engineered Substrates Using the Nanocleave Process”, SemiconWest, TechXPOT Conference—Challenges in Device Scaling, Jul. 19, 2006, San Francisco. |
| Diamant, G., et al., “Integrated Circuits based on Nanoscale Vacuum Phototubes”, Applied Physics Letters 92, 262903-1 to 262903-3 (2008). |
| Landesberger, C., et al., “Carrier techniques for thin wafer processing”, CS MANTECH Conference, May 14-17, 2007 Austin, Texas, pp. 33-36. |
| Shen, W., et al., “Mercury Droplet Micro switch for Re-configurable Circuit Interconnect”, The 12th International Conference on Solid State Sensors, Actuators and Microsystems. Boston, Jun. 8-12, 2003, pp. 464-467. |
| Bangsaruntip, S., et al., “Gate-all-around Silicon Nanowire 25-Stage CMOS Ring Oscillators with Diameter Down to 3 nm”, 2010 Symposium on VLSI Technology Digest of papers, pp. 21-22. |
| Borland, J.O., “Low Temperature Activation of Ion Implanted Dopants: A Review”, International Workshop on Junction technology 2002, S7-3, Japan Society of Applied Physics, pp. 85-88. |
| Vengurlekar, A., et al., “Hydrogen Plasma Enhancement of Boron Activation in Shallow Junctions”, Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 4052-4054. |
| El-Maleh, A. H., et al., “Transistor-Level Defect Tolerant Digital System Design at the Nanoscale”, Research Proposal Submitted to Internal Track Research Grant Programs, 2007. Internal Track Research Grant Programs. |
| Austin, T., et al., “Reliable Systems on Unreliable Fabrics”, IEEE Design & Test of Computers, Jul./Aug. 2008, vol. 25, issue 4, pp. 322-332. |
| Borkar, S., “Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation”, IEEE Micro, IEEE Computer Society, Nov.-Dec. 2005, pp. 10-16. |
| Zhu, S., et al., “N-Type Schottky Barrier Source/Drain MOSFET Using Ytterbium Silicide”, IEEE Electron Device Letters, vol. 25, No. 8, Aug. 2004, pp. 565-567. |
| Zhang, Z., et al., “Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources,” IEEE Electron Device Letters, vol. 31, No. 7, Jul. 2010, pp. 731-733. |
| Lee, R. T.P., et al., “Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated Source/Drain N-channel MuGFETs”, 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 108-109. |
| Awano, M., et al., “Advanced DSS MOSFET Technology for Ultrahigh Performance Applications”, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 24-25. |
| Choi, S.-J., et al., “Performance Breakthrough in NOR Flash Memory with Dopant-Segregated Schottky-Barrier (DSSB) SONOS Devices”, 2009 Symposium of VLSI Technology Digest, pp. 222-223. |
| Zhang, M., et al., “Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs”, Proceeding of ESSDERC, Grenoble, France, 2005, pp. 457-460. |
| Larrieu, G., et al., “Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI”, IEEE Electron Device Letters, vol. 30, No. 12, Dec. 2009, pp. 1266-1268. |
| Ko, C.H., et al., “NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications”, 2006 Symposium on VLSI Technology Digest of Technical Papers. |
| Kinoshita, A., et al., “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 168-169. |
| Kinoshita, A., et al., “High-performance 50-nm-Gate-Length Schottky-Source/Drain MOSFETs with Dopant-Segregation Junctions”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159. |
| Kaneko, A., et al., “High-Performance FinFET with Dopant-Segregated Schottky Source/Drain”, IEDM 2006. |
| Kinoshita, A., et al., “Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors”, IEDM 2006. |
| Kinoshita, A., et al., “Comprehensive Study on Injection Velocity Enhancement in Dopant-Segregated Schottky MOSFETs”, IEDM 2006. |
| Choi, S.-J., et al., “High Speed Flash Memory and 1T-DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS Device for Multi-functional SoC Applications”, 2008 IEDM, pp. 223-226. |
| Chin, Y.K., et al., “Excimer Laser-Annealed Dopant Segregated Schottky (ELA-DSS) Si Nanowire Gate-All-Around (GAA) pFET with Near Zero Effective Schottky Barrier Height (SBH)”, IEDM 2009, pp. 935-938. |
| Agoura Technologies white paper, “Wire Grid Polarizers: a New High Contrast Polarizer Technology for Liquid Crystal Displays”, 2008, pp. 1-12. |
| Unipixel Displays, Inc. white paper, “Time Multi-plexed Optical Shutter (TMOS) Displays”, Jun. 2007, pp. 1-49. |
| Azevedo, I. L., et al., “The Transition to Solid-State Lighting”, Proc. IEEE, vol. 97, No. 3, Mar. 2009, pp. 481-510. |
| Crawford, M.H., “LEDs for Solid-State Lighting: Performance Challenges and Recent Advances”, IEEE Journal of Selected Topics in Quantum Electronics, vol. 15, No. 4, Jul./Aug. 2009, pp. 1028-1040. |
| Tong, Q.-Y., et al., “A “smarter-cut” approach to low temperature silicon layer transfer”, Applied Physics Letters, vol. 72, No. 1, Jan. 5, 1998, pp. 49-51. |
| Tong, Q.-Y., et al., “Low Temperature Si Layer Splitting”, Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp. 126-127. |
| Nguyen, P., et al., “Systematic study of the splitting kinetic of H/He co-implanted substrate”, SOI Conference, 2003, pp. 132-134. |
| Ma, X., et al., “A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding”, Semiconductor Science and Technology, vol. 21, 2006, pp. 959-963. |
| Yu, C.Y., et al., “Low-temperature fabrication and characterization of Ge-on-insulator structures”, Applied Physics Letters, vol. 89, 101913-1 to 101913-2 (2006). |
| Li, Y. A., et al., “Surface Roughness of Hydrogen Ion Cut Low Temperature Bonded Thin Film Layers”, Japan Journal of Applied Physics, vol. 39 (2000), Part 1, No. 1, pp. 275-276. |
| Hoechbauer, T., et al., “Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers”, Nuclear Instruments and Methods in Physics Research B, vol. 216 (2004), pp. 257-263. |
| Aspar, B., et al., “Transfer of structured and patterned thin silicon films using the Smart-Cut process”, Electronics Letters, Oct. 10, 1996, vol. 32, No. 21, pp. 1985-1986. |
| Agarwal, A., et al., “Efficient production of silicon-on-insulator films by co-implantation of He+ with H+” Applied Physics Letters, vol. 72, No. 9, Mar. 1998, pp. 1086-1088. |
| Cook III, G. O., et al., “Overview of transient liquid phase and partial transient liquid phase bonding,” Journal of Material Science, vol. 46, 2011, pp. 5305-5323. |
| Moustris, G. P., et al., “Evolution of autonomous and semi-autonomous robotic surgical systems: a review of the literature,” International Journal of Medical Robotics and Computer Assisted Surgery, Wiley Online Library, 2011, DOI: 10.10002/rcs.408. |
| Subbarao, M., et al., “Depth from Defocus: A Spatial Domain Approach,” International Journal of Computer Vision, vol. 13, No. 3, pp. 271-294 (1994). |
| Subbarao, M., et al., “Focused Image Recovery from Two Defocused Images Recorded with Different Camera Settings,” IEEE Transactions on Image Processing, vol. 4, No. 12, Dec. 1995, pp. 1613-1628. |
| Guseynov, N. A., et al., “Ultrasonic Treatment Restores the Photoelectric Parameters of Silicon Solar Cells Degraded under the Action of 60Cobalt Gamma Radiation,” Technical Physics Letters, vol. 33, No. 1, pp. 18-21 (2007). |
| Gawlik, G., et al., “GaAs on Si: towards a low-temperature “smart-cut” technology”, Vacuum, vol. 70, pp. 103-107 (2003). |
| Weldon, M. K., et al., “Mechanism of Silicon Exfoliation Induced by Hydrogen/Helium Co-implantation,” Applied Physics Letters, vol. 73, No. 25, pp. 3721-3723 (1998). |
| Miller, D.A.B., “Optical interconnects to electronic chips,” Applied Optics, vol. 49, No. 25, Sep. 1, 2010, pp. F59-F70. |
| En, W. G., et al., “The Genesis Process: A New SOI wafer fabrication method”, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 163-164. |
| Uchikoga, S., et al., “Low temperature poly-Si TFT-LCD by excimer laser anneal,” Thin Solid Films, vol. 383 (2001), pp. 19-24. |
| He, M., et al., “Large Polycrystalline Silicon Grains Prepared by Excimer Laser Crystallization of Sputtered Amorphous Silicon Film with Process Temperature at 100 C,” Japanese Journal of Applied Physics, vol. 46, No. 3B, 2007, pp. 1245-1249. |
| Kim, S.D., et al., “Advanced source/drain engineering for box-shaped ultra shallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS,” IEEE Trans. Electron Devices, vol. 49, No. 10, pp. 1748-1754, Oct. 2002. |
| Ahn, J., et al., “High-quality MOSFET's with ultrathin LPCVD gate SiO2,” IEEE Electron Device Lett., vol. 13, No. 4, pp. 186-188, Apr. 1992. |
| Yang, M., et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientation,” Proceedings IEDM 2003. |
| Yin, H., et al., “Scalable 3-D finlike poly-Si TFT and its nonvolatile memory application,” IEEE Trans. Electron Devices, vol. 55, No. 2, pp. 578-584, Feb. 2008. |
| Kawaguchi, N., et al., “Pulsed Green-Laser Annealing for Single-Crystalline Silicon Film Transferred onto Silicon wafer and Non-alkaline Glass by Hydrogen-Induced Exfoliation,” Japanese Journal of Applied Physics, vol. 46, No. 1, 2007, pp. 21-23. |
| Faynot, O. et al., “Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond,” Electron Devices Meeting (IEDM), 2010 IEEE International, vol., No., pp. 3.2.1, 3.2.4, Dec. 6-8, 2010. |
| Khakifirooz, A., “ETSOI Technology for 20nm and Beyond”, SOI Consortium Workshop: Fully Depleted SOI, Apr. 28, 2011, Hsinchu Taiwan. |
| Kim, I.-K., et al.,“Advanced Integration Technology for a Highly Scalable SOI DRAM with SOC (Silicon-On-Capacitors)”, IEDM 1996, pp. 96-605-608, 22.5.4. |
| Lee, B.H., et al., “A Novel CMP Method for cost-effective Bonded SOI Wafer Fabrication,” Proceedings 1995 IEEE International SOI Conference, Oct. 1995, pp. 60-61. |
| Choi, Sung-Jin, et al., “Performance Breakthrough in NOR Flash Memory with Dopant-Segregated Schottky-Barrier (DSSB) SONOS Devices,” paper 11B-3, 2009 Symposium on VLSI Technology, Digest of Technical Papers, pp. 222-223. |
| Chang, Wei, et al., “Drain-induced Schottky barrier source-side hot carriers and its application to program local bits of nanowire charge-trapping memories,” Japanese Journal of Applied Physics 53, 094001 (2014) pp. 094001-1 to 094001-5. |
| Uchida, K., et al., “Enhancement of hot-electron generation rate in Schottky source metal-oxide-semiconductor filed-effect transistors,” Appl. Phys. Lett., 76, 3992 (2000). 10.1063/1.126845. |
| Okuyama, K., et al., “Characterization of Newly Developed 3-D Parallel Triple Gate MOS Transistor,” 4th COE Workshop Sep. 16, 2005. Hiroshima University. |
| Okuyama, K., et al., “Control of Subthreshold Characteristics of Narrow-Channel Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Transistor with Additional Side Gate Electrodes”, Jap. J. of Appl. Phys., vol. 46, No. 4B, 2007, pp. 1-4. |
| Okuyama, K., et al., “Proposal of 3-Dimensional Independent Triple-Gate MOS Transistor with Dynamic Current Control,” IEDM 2007. IEEE 1-4244-0585-8/07/2007. |
| Hokazono, A., et al., “Steep Channel & Halo Profiles utilizing Boron-Diffusion-Barrier Layers (Si:C) for 32 nm Node and Beyond,” VLSI Technology, 2008 IEEE Symposium on, vol., No., pp. 112-113, IEEE 978-1-4244-1805-3/08/2008. |
| Astrova, E.V., et al., “Anisotropic Shaping of Macroporous Silicon,” ISSN 1063-7826, Semiconductors, 2015, vol. 49, No. 4, pp. 551-558. |
| Huang, Z., et al., “Extended Arrays of Vertically Aligned Sub-10 nm Diameter [100] Si Nanowires by Metal Assisted Chemical Etching”, NanoLetters 2008, vol. 8, No. 9, pp. 3046-3051. |
| Schmidt, T., et. al., “Fabrication of Ultra-high aspect ratio silicon nanopores by electrochemical etching”, App. Phys. Lett., 105, 123111 (2014) 10.1063/1.4896524. |
| Lin, J., et al., “Investigation of the Formation of Undercut during the Fabrication of Silicon Microchannels by Electrochemical Etching,” Proc. 3rd IEEE Intl. Conf. on Nano/Micro Engineered and Molecular Systems, Jan. 6-9, 2008. Sanya, China. |
| Tsai, Wen-Jer, “A Novel Trapping-Nitride-Storage Non-Volatile Memory Cell Using a Gated-Diode Structure With an Ultra-Thin Dielectric Dopant Diffusion Barrier”, IEEE Trans. Elect. Dev., vol. 55, No. 8, pp. 2202-2211, Aug. 2008. |
| Topol, A.W., et al., “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM Tech. Digest, Dec. 5, 2005, pp. 363-366. |
| Demeester, P. et al., “Epitaxial lift-off and its applications,” Semicond. Sci. Technol., 1993, pp. 1124-1135, vol. 8. |
| Yoon, J., et al., “GaAs Photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies”, Nature, vol. 465, May 20, 2010, pp. 329-334. |
| Bakir and Meindl, “Integrated Interconnect Technologies for 3D Nanoelectronic Systems”, Artech House, 2009, Chapter 13, pp. 389-419. |
| Tanaka, H., et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” VLSI Technology, 2007 IEEE Symposium on , vol., No., pp. 14-15, Jun. 12-14, 2007. |
| Lue, H.-T., et al., “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010, pp. 131-132. |
| Kim, W., et al., “Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage”, Symposium on VLSI Technology Digest of Technical Papers, 2009, pp. 188-189. |
| Dicioccio, L., et al., “Direct bonding for wafer level 3D integration”, ICICDT 2010, pp. 110-113. |
| Kim, W., et al., “Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage,” Symposium on VLSI Technology, 2009, pp. 188-189. |
| Walker, A. J., “Sub-50nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash”, IEEE Trans. Elect. Dev., vol. 56, No. 11, pp. 2703-2710, Nov. 2009. |
| Hubert, A., et al., “A Stacked SONOS Technology, Up to 4 Levels and 6nm Crystalline Nanowires, with Gate-All-Around or Independent Gates (ΦFlash), Suitable for Full 3D Integration”, International Electron Devices Meeting, 2009, pp. 637-640. |
| Celler, G.K. et al., “Frontiers of silicon-on-insulator,” J. App. Phys., May 1, 2003, pp. 4955-4978, vol. 93, No. 9. |
| Rajendran, B., et al., “Electrical Integrity of MOS Devices in Laser Annealed 3D IC Structures”, proceedings VLSI Multi Level Interconnect Conference 2004, pp. 73-74. |
| Rajendran, B., “Sequential 3D IC Fabrication: Challenges and Prospects”, Proceedings of VLSI Multi Level Interconnect Conference 2006, pp. 57-64. |
| Jung, S.-M., et al., “The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 (stacked single-crystal Si) cell, 0.16um2, and SSTFT (stacked single-crystal thin film transistor) for ultra high density SRAM,” VLSI Technology, 2004. Digest of Technical Papers, pp. 228-229, Jun. 15-17, 2004. |
| Hui, K. N., et al., “Design of vertically-stacked polychromatic light-emitting diodes,” Optics Express, Jun. 8, 2009, pp. 9873-9878, vol. 17, No. 12. |
| Chuai, D. X., et al., “A Trichromatic Phosphor-Free White Light-Emitting Diode by Using Adhesive Bonding Scheme,” Proc. SPIE, 2009, vol. 7635. |
| Suntharalingam, V. et al., “Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology,” Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, Aug. 29, 2005, pp. 356-357, vol. 1. |
| Coudrain, P. et al., “Setting up 3D Sequential Integration for Back-Illuminated CMOS Image Sensors with Highly Miniaturized Pixels with Low Temperature Fully-Depleted SOI Transistors,” IEDM, 2008, pp. 1-4. |
| Flamand, G. et al., “Towards Highly Efficient 4-Terminal Mechanical Photovoltaic Stacks,” III-Vs Review, Sep.-Oct. 2006, pp. 24-27, vol. 19, Issue 7. |
| Zahler, J.M. et al., “Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells,” Photovoltaic Specialists Conference, Conference Record of the Twenty-Ninth IEEE, May 19-24, 2002, pp. 1039-1042. |
| Sekar, D. C., et al., “A 3D-IC Technology with Integrated Microchannel Cooling”, Proc. Intl. Interconnect Technology Conference, 2008, pp. 13-15. |
| Brunschweiler, T., et al., “Forced Convective Interlayer Cooling in Vertically Integrated Packages,” Proc. Intersoc. Conference on Thermal Management (ITHERM), 2008, pp. 1114-1125. |
| Yu, H., et al., “Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 14, No. 3, Article 41, May 2009, pp. 41.1-41.31. |
| Motoyoshi, M., “3D-IC Integration,” 3rd Stanford and Tohoku University Joint Open Workshop, Dec. 4, 2009, pp. 1-52. |
| Wong, S., et al., “Monolithic 3D Integrated Circuits,” VLSI Technology, Systems and Applications, 2007, International Symposium on VLSI-TSA 2007, pp. 1-4. |
| Batude, P., et al., “Advances in 3D Cmos Sequential Integration,” 2009 IEEE International Electron Devices Meeting (Baltimore, Maryland), Dec. 7-9, 2009, pp. 345-348. |
| Tan, C.S., et al., “Wafer Level 3-D ICs Process Technology,” ISBN-10: 0387765328, Springer, 1st Ed., Sep. 19, 2008, pp. v-xii, 34, 58, and 59. |
| Yoon, S.W. et al., “Fabrication and Packaging of Microbump Interconnections for 3D TSV,” IEEE International Conference on 3D System Integration (3DIC), Sep. 28-30, 2009, pp. 1-5. |
| Franzon, P.D. et al., “Design and CAD for 3D Integrated Circuits,” 45th ACM/IEEE Design, Automation Conference (DAC), Jun. 8-13, 2008, pp. 668-673. |
| Lajevardi, P., “Design of a 3-Dimension FPGA,” Thesis paper, University of British Columbia, Submitted to Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Jul. 2005, pp. 1-71. |
| Dong, C. et al., “Reconfigurable Circuit Design with Nanomaterials,” Design, Automation & Test in Europe Conference & Exhibition, Apr. 20-24, 2009, pp. 442-447. |
| Razavi, S.A., et al., “A Tileable Switch Module Architecture for Homogeneous 3D FPGAs,” IEEE International Conference on 3D System Integration (3DIC), Sep. 28-30, 2009, 4 pages. |
| Bakir M., et al., “3D Device-Stacking Technology for Memory,” Chptr. 13.4, pp. 407-410, in “Integrated Interconnect Technologies for 3D Nano Electronic Systems”, 2009, Artech House. |
| Weis, M. et al., “Stacked 3-Dimensional 6T SRAM Cell with Independent Double Gate Transistors,” IC Design and Technology, May 18-20, 2009. |
| Doucette, P., “Integrating Photonics: Hitachi, Oki Put LEDs on Silicon,” Solid State Technology, Jan. 2007, p. 22, vol. 50, No. 1. |
| Luo, Z.S. et al., “Enhancement of (In, Ga)N Light-emitting Diode Performance by Laser Liftoff and Transfer from Sapphire to Silicon,” Photonics Technology Letters, Oct. 2002, pp. 1400-1402, vol. 14, No. 10. |
| Zahler, J.M. et al., “Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells,” NCPV and Solar Program Review Meeting, 2003, pp. 723-726. |
| Kada, M., “Updated results of R&D on functionally innovative 3D-integrated circuit (dream chip) technology in FY2009”, (2010) International Microsystems Packaging Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference, Proceedings. |
| Kada, M., “Development of functionally innovative 3D-integrated circuit (dream chip) technology / high-density 3D-integration technology for multifunctional devices”, (2009) IEEE International Conference on 3D System Integration, 3DIC 2009. |
| Marchal, P., et al., “3-D technology assessment: Path-finding the technology/design sweet-spot”, (2009) Proceedings of the IEEE, 97 (1), pp. 96-107. |
| Xie, Y., et al., “Design space exploration for 3D architectures”, (2006) ACM Journal on Emerging Technologies in Computing Systems, 2 (2), Apr. 2006, pp. 65-103. |
| Souri, S., et al., “Multiple Si layers ICs: motivation, performance analysis, and design Implications”, (2000) Proceedings—Design Automation Conference, pp. 213-220. |
| Vinet, M., et.al., “3D monolithic integration: Technological challenges and electrical results”, Microelectronic Engineering Apr. 2011 vol. 88, Issue 4, pp. 331-335. |
| Bobba, S. et al., “CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits”, Asia pacific DAC 2011, paper 4A-4. |
| Choudhury, D., “3D Integration Technologies for Emerging Microsystems”, IEEE Proceedings of the IMS 2010, pp. 1-4. |
| Lee, Y.-J., et. al, “3D 65nm CMOS with 320° C. Microwave Dopant Activation”, IEDM 2010, pp. 1-4. |
| Crnogorac, F., et al., “Semiconductor crystal islands for three-dimensional integration”, J. Vac. Sci. Technol. B 28(6), Nov./Dec. 2010, pp. C6P53-C6P58. |
| Park, J.-H., et al., “N-Channel Germanium MOSFET Fabricated Below 360° C. by Cobalt-Induced Dopant Activation for Monolithic Three-Dimensional—ICs”, IEEE Electron Device Letters, vol. 32, No. 3, Mar. 2011, pp. 234-236. |
| Jung, S.-M., et al., “Highly Area Efficient and Cost Effective Double Stacked S3( Stacked Single-crystal Si ) Peripheral CMOS SSTFT and SRAM Cell Technology for 512M bit density SRAM”, IEDM 2003, pp. 265-268. |
| Joyner, J.W., “Opportunities and Limitations of Three-dimensional Integration for Interconnect Design”, PhD Thesis, Georgia Institute of Technology, Jul. 2003. |
| Choi, S.-J., “A Novel TFT with a Laterally Engineered Bandgap for of 3D Logic and Flash Memory”, 2010 Symposium of VLSI Technology Digest, pp. 111-112. |
| Radu, I., et al., “Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking”, IEEE 3D Systems Integration Conference (3DIC), Nov. 16-18, 2010. |
| Gaudin, G., et al., “Low temperature direct wafer to wafer bonding for 3D integration”, 3D Systems Integration Conference (3DIC), IEEE, 2010, Munich, Nov. 16-18, 2010, pp. 1-4. |
| Jung, S.-M., et al., ““Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node””, IEDM 2006, Dec. 11-13, 2006. |
| Souri, S. J., “Interconnect Performance in 3-Dimensional Integrated Circuits”, PhD Thesis, Stanford, Jul. 2003. |
| Uemoto, Y., et al., “A High-Performance Stacked-CMOS SRAM Cell by Solid Phase Growth Technique”, Symposium on VLSI Technology, 2010, pp. 21-22. |
| Jung, S.-M., et al., “Highly Cost Effective and High Performance 65nm S3( Stacked Single-crystal Si ) SRAM Technology with 25F2, 0.16um2 cell and doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications”, 2005 Symposium on VLSI Technology Digest of Technical papers, pp. 220-221. |
| Steen, S.E., et al., “Overlay as the key to drive wafer scale 3D integration”, Microelectronic Engineering 84 (2007) 1412-1415. |
| Maeda, N., et al., “Development of Sub 10-μm Ultra-Thinning Technology using Device Wafers for 3D Manufacturing of Terabit Memory”, 2010 Symposium on VLSI Technology Digest of Technical Papers, pp. 105-106. |
| Chan, M., et al., “3-Dimensional Integration for Interconnect Reduction in for Nano-CMOS Technologies”, IEEE Tencon, Nov. 23, 2006, Hong Kong. |
| Dong, X., et al., “Chapter 10: System-Level 3D IC Cost Analysis and Design Exploration”, in Xie, Y., et al., “Three-Dimensional Integrated Circuit Design”, book in series “Integrated Circuits and Systems” ed. A. Andrakasan, Springer 2010. |
| Naito, T., et al., “World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS”, 2010 Symposium on VLSI Technology Digest of Technical Papers, pp. 219-220. |
| Bernard, E., et al., “Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with Metal / High-K Gate stack”, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 16-17. |
| Cong, J., et al., “Quantitative Studies of Impact of 3D IC Design on Repeater Usage”, Proceedings of International VLSI/ULSI Multilevel Interconnection Conference, pp. 344-348, 2008. |
| Gutmann, R.J., et al., “Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals”, Journal of Semiconductor Technology and Science, vol. 4, No. 3, Sep. 2004, pp. 196-203. |
| Crnogorac, F., et al., “Nano-graphoepitaxy of semiconductors for 3D integration”, Microelectronic Engineering 84 (2007) 891-894. |
| Koyanagi, M, “Different Approaches to 3D Chips”, 3D IC Review, Stanford University, May 2005. |
| Koyanagi, M, “Three-Dimensional Integration Technology and Integrated Systems”, ASPDAC 2009 presentation. |
| Koyanagi, M., et al., “Three-Dimensional Integration Technology and Integrated Systems”, ASPDAC 2009, paper 4D-1, pp. 409-415. |
| Hayashi, Y., et al., “A New Three Dimensional IC Fabrication Technology Stacking Thin Film Dual-CMOS Layers”, IEDM 1991, paper 25.6.1, pp. 657-660. |
| Clavelier, L., et al., “Engineered Substrates for Future More Moore and More Than Moore Integrated Devices”, IEDM 2010, paper 2.6.1, pp. 42-45. |
| Kim, K., “From The Future Si Technology Perspective: Challenges and Opportunities”, IEDM 2010, pp. 1.1.1-1.1.9. |
| Ababei, C., et al., “Exploring Potential Benefits of 3D FPGA Integration”, in book by Becker, J.et al. Eds., “Field Programmable Logic 2004”, LNCS 3203, pp. 874-880, 2004, Springer-Verlag Berlin Heidelberg. |
| Ramaswami, S., “3D TSV IC Processing”, 3DIC Technology Forum Semicon Taiwan 2010, Sep. 9, 2010. |
| Davis, W.R., et al., “Demystifying 3D Ics: Pros and Cons of Going Vertical”, IEEE Design and Test of Computers, Nov.-Dec. 2005, pp. 498-510. |
| Lin, M., et al., “Performance Benefits of Monolithically Stacked 3DFPGA”, FPGA06, Feb. 22-24, 2006, Monterey, California, pp. 113-122. |
| Dong, C., et al., “Performance and Power Evaluation of a 3D CMOS/Nanomaterial Reconfigurable Architecture”, ICCAD 2007, pp. 758-764. |
| Gojman, B., et al., “3D Nanowire-Based Programmable Logic”, International Conference on Nano-Networks (Nanonets 2006), Sep. 14-16, 2006. |
| Dong, C., et al., “3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits”, IEEE Transactions on Circuits and Systems, vol. 54, No. 11, Nov. 2007, pp. 2489-2501. |
| Golshani, N., et al., “Monolithic 3D Integration of SRAM and Image Sensor Using Two Layers of Single Grain Silicon”, 2010 IEEE International 3D Systems Integration Conference (3DIC), Nov. 16-18, 2010, pp. 1-4. |
| Rajendran, B., et al., “Thermal Simulation of laser Annealing for 3D Integration”, Proceedings VMIC 2003. |
| Woo, H.-J., et al., “Hydrogen Ion Implantation Mechanism in GaAs-on-insulator Wafer Formation by Ion-cut Process”, Journal of Semiconductor Technology and Science, vol. 6, No. 2, Jun. 2006, pp. 95-100. |
| Sadaka, M., et al., “Building Blocks for wafer level 3D integration”, www.electroiq.com, Aug. 18, 2010, last accessed Aug. 18, 2010. |
| Madan, N., et al., “Leveraging 3D Technology for Improved Reliability,” Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), IEEE Computer Society. |
| Hayashi, Y., et al., “Fabrication of Three Dimensional IC Using “Cumulatively Bonded IC” (CUBIC) Technology”, 1990 Symposium on VLSI Technology, pp. 95-96. |
| Akasaka, Y., “Three Dimensional IC Trends,” Proceedings of the IEEE, vol. 24, No. 12, Dec. 1986. |
| Guarini, K. W., et al., “Electrical Integrity of State-of-the-Art 0.13um SOI Device and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” IEDM 2002, paper 16.6, pp. 943-945. |
| Kunio, T., et al., “Three Dimensional Ics, Having Four Stacked Active Device Layers,” IEDM 1989, paper 34.6, pp. 837-840. |
| Gaillardon, P-E., et al., “Can We Go Towards True 3-D Architectures?,” DAC 2011, paper 58, pp. 282-283. |
| Yun, J-G., et al., “Single-Crystalline Si Stacked Array (STAR) NAND Flash Memory,” IEEE Transactions on Electron Devices, vol. 58, No. 4, Apr. 2011, pp. 1006-1014. |
| Kim, Y., et al., “Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline Stacked Array,” IEEE Transactions on Electron Devices, vol. 59, No. 1, Jan. 2012, pp. 35-45. |
| Goplen, B., et al., “Thermal Via Placement in 3DICs,” Proceedings of the International Symposium on Physical Design, Apr. 3-6, 2005, San Francisco. |
| Bobba, S., et al., “Performance Analysis of 3-D Monolithic Integrated Circuits,” 2010 IEEE International 3D Systems Integration Conference (3DIC), Nov. 2010, Munich, pp. 1-4. |
| Batude, P., et al., “Demonstration of low temperature 3D sequential FDSOI integration down to 50nm gate length,” 2011 Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159. |
| Batude, P., et al., “Advances, Challenges and Opportunties in 3D CMOS Sequential Integration,” 2011 IEEE International Electron Devices Meeting, paper 7.3, Dec. 2011, pp. 151-154. |
| Yun, C. H., et al., “Transfer of patterned ion-cut silicon layers”, Applied Physics Letters, vol. 73, No. 19, Nov. 1998, pp. 2772-2774. |
| Ishihara, R., et al., “Monolithic 3D-ICs with single grain Si thin film transistors,” Solid-State Electronics 71 (2012) pp. 80-87. |
| Lee, S. Y., et al., “Architecture of 3D Memory Cell Array on 3D IC,” IEEE International Memory Workshop, May 20, 2012, Monterey, CA. |
| Lee, S. Y., et al., “3D IC Architecture for High Density Memories,” IEEE International Memory Workshop, p. 1-6, May 2010. |
| Rajendran, B., et al., “CMOS transistor processing compatible with monolithic 3-D Integration,” Proceedings VMIC 2005. |
| Huet, K., “Ultra Low Thermal Budget Laser Thermal Annealing for 3D Semiconductor and Photovoltaic Applications,” NCCAVS 2012 Junction Technology Group, Semicon West, San Francisco, Jul. 12, 2012. |
| Derakhshandeh, J., et al., “A Study of the CMP Effect on the Quality of Thin Silicon Films Crystallized by Using the u-Czochralski Process,” Journal of the Korean Physical Society, vol. 54, No. 1, 2009, pp. 432-436. |
| Kim, J., et al., “A Stacked Memory Device on Logic 3D Technology for Ultra-high-density Data Storage,” Nanotechnology, vol. 22, 254006 (2011). |
| Lee, K. W., et al., “Three-dimensional shared memory fabricated using wafer stacking technology,” IEDM Tech. Dig., 2000, pp. 165-168. |
| Chen, H. Y., et al., “HfOx Based Vertical Resistive Random Access Memory for Cost Effective 3D Cross-Point Architecture without Cell Selector,” Proceedings IEDM 2012, pp. 497-499. |
| Huet, K., et al., “Ultra Low Thermal Budget Anneals for 3D Memories: Access Device Formation,” Ion Implantation Technology 2012, AIP Conf Proceedings 1496, 135-138 (2012). |
| Batude, P., et al., “3D Monolithic Integration,” ISCAS 2011 pp. 2233-2236. |
| Batude, P., et al., “3D Sequential Integration: A Key Enabling Technology for Heterogeneous C-Integration of New Function With CMOS,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 2, No. 4, Dec. 2012, pp. 714-722. |
| Vinet, M., et.al., “Germanium on Insulator and new 3D architectures opportunities for integration”, International Journal of Nanotechnology, vol. 7, No. 4, (Aug. 2010) pp. 304-319. |
| Bernstein, K., et al., “Interconnects in the Third Dimension: Design Challenges for 3DICs,” Design Automation Conference, 2007, DAC'07, 44th ACM/IEEE, vol., No., pp. 562-567, Jun. 4-8, 2007. |
| Kuroda, T., “ThruChip Interface for Heterogeneous Chip Stacking,” ElectroChemicalSociety Transactions, 50 (14) 63-68 (2012). |
| Miura, N., et al., “A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface,” IEEE Micro Cool Chips XVI, Yokohama, Apr. 17-19, 2013, pp. 1-3(2013). |
| Kuroda, T., “Wireless Proximity Communications for 3D System Integration,” Future Directions in IC and Package Design Workshop, Oct. 29, 2007. |
| Qiang, J-Q, “3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems,” Proceedings of the IEEE, 97.1 (2009) pp. 18-30. |
| Lee, B.H., et al., “A Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMs,” Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 114-115. |
| Wu, B., et al., “Extreme ultraviolet lithography and three dimensional circuits,” Applied Physics Reviews, 1, 011104 (2014). |
| Delhougne, R., et al., “First Demonstration of Monocrystalline Silicon Macaroni Channel for 3-D NAND Memory Devices” IEEE VLSI Tech Digest, 2018, pp. 203-204. |
| Kim, J., et al.; “A stacked memory device on logic 3D technology for ultra-high-density data storage”; Nanotechnology 22 (2011) 254006 (7pp). |
| Hsieh, P-Y, et al., “Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators”, IEDM paper 3.1, pp. IEDM19-46 to IEDM19-49. |
| Then, Han Wui, et al., “3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications”, IEDM 2019, paper 17.3, pp. IEDM19-402 to IEDM19-405. |
| Rachmady, W., et al., “300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications”, IEDM 2019, paper 29.7, pp. IEDM19-697 to IEDM19-700. |
| Number | Date | Country | |
|---|---|---|---|
| 62307568 | Mar 2016 | US | |
| 62286362 | Jan 2016 | US | |
| 62276953 | Jan 2016 | US | |
| 62271251 | Dec 2015 | US | |
| 62266610 | Dec 2015 | US | |
| 62246054 | Oct 2015 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15333138 | Oct 2016 | US |
| Child | 15990611 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17665560 | Feb 2022 | US |
| Child | 18527356 | US | |
| Parent | 17524737 | Nov 2021 | US |
| Child | 17665560 | US | |
| Parent | 17396711 | Aug 2021 | US |
| Child | 17524737 | US | |
| Parent | 17063397 | Oct 2020 | US |
| Child | 17396711 | US | |
| Parent | 16526763 | Jul 2019 | US |
| Child | 17063397 | US | |
| Parent | 15990611 | May 2018 | US |
| Child | 16526763 | US |
