Patent Application
20240428848
Examples of the present disclosure generally relate to memory cells for an integrated circuitry (IC) device.
Memory cells for integrated circuitry devices (ICs) have many requirements and limitations that are different from those for other types of memory cells, such as those for static random access memory (SRAM). Some IC devices utilize an embedded SRAM called a configuration random access memory (CRAM), For example the IC device may be a field programmable gate array (FPGA). For example, while the storage nodes of conventional SRAM memory only interact with the word or address line and the data lines of the memory cell array, the storage nodes of CRAM memory cells are used to directly connect to neighboring circuitry in order to configure the logic of the FPGA. CRAM consists of SRAM and is used to configure all of the user logic in an FPGA.
In one or more examples, a memory device includes a first bit cell comprising a first inverter, the first inverter comprising a p-type transistor coupled to an n-type transistor, and header circuitry coupled to the first inverter and comprising a first header transistor and a second header transistor, the first header transistor having a gate configured to receive a bias voltage, the second header transistor having a gate configured to receive a reference voltage.
In one or more examples, a memory device includes first header circuitry comprising a first header transistor and a second header transistor, the first header transistor having a gate configured to receive a bias voltage, the second header transistor having a gate configured to receive a reference voltage, second header circuitry comprising a third header transistor and a fourth header transistor, the third header transistor having a gate configured to receive the bias voltage, the fourth header transistor having a gate configured to receive the reference voltage, a first bit cell and a second bit cell coupled to the first header circuitry; and a third bit cell and a fourth bit cell coupled to the second header circuitry.
In one or more examples, a memory device includes a first bit cell comprising a first inverter cross-coupled to a second inverter by a first storage node and a first inverse storage node; and a first header circuitry comprising a first header transistor and a second header transistor; the first header transistor having a gate configured to receive a bias voltage, the second header transistor having a gate configured to receive a reference voltage, the first header circuitry coupled to the first inverter and the second inverter.
Typically integrated circuitry devices (ICs) use an embedded static random access memory (SRAM) called a configuration random access memory (CRAM). CRAM memory cells are directly connected to and control a corresponding IC, such as a field programmable gate array (FPGA). Each bit cell of a CRAM memory cell requires: a compact layout for area scaling, direct access connections to internal storage nodes of FPGA logic, a large write margin, and low bitline and cell leakage in order to meet the requirements of advanced technology beyond the 7 nm field-effect transistor (FinFET) technology node (i.e., the 7 nm node). However, once passing the 7 nm node, conventional 6-T CRAM memory cell performance degrades. The node-to-node technology transistor performance gain slows down. Additionally, during the write operation the read and write operations are fighting. Therefore, to maintain a larger write margin, in conventional 6-T memory cells, weaker pull-up (p-type) transistors are used. However as a memory cell is scaled down to meet the constraints required by advanced technology beyond the 7 nm node, although the dimensions of the memory cell are scaled, the bitline and cell leakage are not. For example, every CRAM memory cell has a reverification built-in which causes current leakage. During a write operation if too much leakage is present, the bitline current will converge to ground so it cannot be read.
Furthermore, the requirements of advanced technology beyond the 7 nm node and the highly restricted layout of memory cell rules disallow the narrowest and weakest pull-up (p-type) transistors to be used. Therefore, the pass-gate (n-type) transistors need to be much wider to maintain a high alpha ratio between the pull-up and pass-gate transistors, and write margin. Wider and/or stronger pass-gate transistors would maintain the alpha ratio between the pull-up transistors and the pass-gate transistors. However, a wider/stronger pass-gate transistor is penalized by high bitline and high cell leakage along with the increased area because, as mentioned above, the leakages do not scale. Lastly, CRAM Vccmin (minimum Vcc operation voltage) yield loss is more susceptible to soft failures caused by slightly degraded n-type transistors resulting from higher device variation, larger process complexity & soft defect modes in advanced technology beyond the 7 nm node.
Embodiments herein, relate to an 8-T CRAM memory device that includes CRAM bit cells that are coupled to a header circuitry that is coupled to biasing circuitry. The biasing circuitry is controlled to weaken the pull-up transistors without having to widen the pass-gate transistors. Furthermore, the header circuitry is implemented as an additional row of p-type transistors between rows of the pull-up transistors and are shared between bit cells to reduce adding to the overall area of conventional 6-T CRAM cells. Additionally, the bias circuitry can be used to recover soft failures caused due to a degraded n-type transistor.
The configuration memory associated with the programmable resources 107 are programmed by way of the routing network 105. The routing network 105 enables routing memory bits operating as enable signals to corresponding circuit blocks. In one example, a plurality of configurable logic blocks (CLBs) 108, are coupled to receive global signals from the control circuitry 110. The control circuitry 110 could be used to provide global signals to each CLB 108. In contrast, the routing network 105 enables separately routing a local enable signal to individual CLBs 108. In one example, the local enable signal allows the CLBs 108 that receive the signal to be reconfigured during a partial reconfiguration.
In other examples, the programmable resources 107 includes other circuitry such as digital processing (DSP) circuitry, blocks of random access memory (BRAM), I/O circuitry, data transceivers, interface elements, system monitoring circuitry, Ethernet Media Access Controller (MAC) circuitry, or the like.
The gating logic circuitry 206 is coupled to receive the global signals, a configuration write enable signal (CFG write enable), and the local enable signal mc_gsc. It should be noted that the local enable signal mc_gsc could be a memory bit stored in the configuration memory. The gating logic circuitry 206 also receives a global enable (en_glob) signal.
The first bit cell 308 includes a word line (or address line) 301, a first inverter 303 comprising transistors 314 and 316, and a second inverter 305 comprising transistors 318 and 320. Each inverter is formed by a p-type transistor coupled to an n-type transistor. For example, the first inverter is formed by transistors 314 and 316. The second inverter is formed by transistors 318 and 320. The first inverter 303 is formed by coupling the drain of transistor 314 to the drain of transistor 316. The source of transistor 314 is coupled to an output of the header circuitry 302. The source of transistor 316 is coupled to a reference voltage (i.e., ground). Therefore, transistor 314 operates as a pull-up transistor and transistor 316 operates as a pass-gate transistor. The second inverter 305 is formed by coupling the drain of transistor 318 to the drain of transistor 320. The source of transistor 318 is coupled to an output of the header circuitry 302. The source of transistor 320 is coupled to a reference voltage (i.e., ground). Therefore, transistor 318 operates as a pull-up transistor and transistor 320 operates as a pass-gate transistor. The header circuitry 302 will be discussed in more detail below.
As described above, in one example, the CRAM device 204 is embedded in an IC, such as an FPGA. Therefore, the CRAM device 204 is directly connected to storage nodes of the FPGA. The storage nodes are used to cross-couple the first inverter 303 and the second inverter 305 in order to store data contained in the CRAM device 204. A first storage node q0 is coupled to the gates of transistors 318 and 320 while a first inverse storage node qb0 is coupled to the gates of transistors 314 and 316. It should be noted that the first storage node q is an example of a storage node, and the first inverse storage node qb is an example of an inverse storage node. The first storage node q0 is also coupled to the drains of transistors 314 and 316 while the first inverse storage node qb0 is coupled to the drains of transistors 318 and 320.
The word line 301 is used to couple transistors 312 and 322 of the first bit cell 308. In one example, transistors 312 and 322 are n-type transistors. The word line 301 connects the gates of transistors 312 and 322. Transistors 312 and 322 are used to control access to the first storage node q0 and the first inverse storage node qb0, respectively, by the data or bitline nodes. The CRAM device 204 is directly connected to data nodes of neighboring circuitry of an FPGA because it is embedded in the FPGA. The data nodes are used to both read and write data to respective data nodes. A first data node do is coupled to the drain of transistor 312. First storage node q0 is coupled to the source of transistor 312. A first inverse data node db0 is coupled to the source of transistor 322. First inverse storage node qb0 is coupled to the drain of transistor 322. It should be noted that first data node do is an example of a data node, and that first inverse data node db0 is an example of an inverse data node. In summary, transistors 314, 318 are p-type transistors while transistors 312, 316, 320, and 322 are n-type transistors.
The second bit cell 310 includes a word line (or address line) 335, a third inverter 313 comprising transistors 326 and 328, and a fourth inverter 315 comprising transistors 330 and 332. Each inverter is formed by a p-type transistor coupled to an n-type transistor. For example, the third inverter 313 is formed by transistors 326 and 328. The fourth inverter 315 is formed by transistors 330 and 332. The third inverter 313 is formed by coupling the drain of transistor 326 to the drain of transistor 328. The source of transistor 326 is coupled to an output of the header circuitry 302. The source of transistor 328 is coupled to a reference voltage (i.e., ground). Therefore, transistor 326 operates as a pull-up transistor and transistor 328 operates as a pull-down transistor. The fourth inverter 315 is formed by coupling the drain of transistor 330 to the drain of transistor 332. The source of transistor 330 is coupled to an output of the header circuitry 302. The source of transistor 332 is coupled to a reference voltage (i.e., ground). Therefore, transistor 330 operates as a pull-up transistor and transistor 332 operates as a pull-down transistor. The header circuitry 302 will be discussed in more detail below
For the same reasons described above, the CRAM device 204 is directly connected a second storage node q0 and a second inverse storage node qb1. The second storage node q1 and the second inverse storage node qb1 are used to cross-couple the third inverter 313 and the fourth inverter 315 in order to store data contained in the CRAM device 204. Stated differently, the second storage node q1 is coupled to the gates of transistors 330 and 332 while the second inverse storage node qb1 is coupled to the gates of transistors 326 and 328. The second storage node q1 is also coupled to the drains of transistors 326 and 328 while the second inverse storage node qb1 is coupled to the drains of transistors 330 and 332.
The word line 335 is used to couple transistors 324 and 334 of the second bit cell 310. In one example, transistors 324 and 334 are n-type transistors. Word line 335 connects the gates of transistors 324 and 334. Transistors 324 and 334 are used to control access to nodes q and qb, respectively, by data or bitline nodes. In one example, because the CRAM device 204 is embedded in an FPGA neighboring bit cells share a common data node and a common inverse data node. A second data node d1 is coupled to the drain of transistor 324. The second storage node q1 is coupled to the source of transistor 324. The second inverse data node db1 is coupled to the source of transistor 334. The second inverse storage node qb1 is coupled to the drain of transistor 334.
To mitigate the issues that arise with the shift to advanced technology beyond the 7 nm node, the first bit cell 308 and the second bit cell 310 are coupled to the header circuitry 302. The header circuitry 302 includes a first header transistor 304 and a second header transistor 306. In one example, the first header transistor 304 and the second header transistor 306 are both p-type transistors. The source of the first header transistor 304 is coupled to a voltage source Vgg. The drain of the first header transistor 304 is coupled to the source of the second header transistor 306. The gate of the first header transistor 304 is coupled to bias circuitry. The drain of the second header transistor 306 is coupled to the sources of transistors 314, 318, 326, and 330. The gate of the second header transistor 306 is coupled to reference voltage (e.g., ground). Therefore, in the illustrated example, the CRAM device 204 is an 8-T memory cell.
As described above, the CRAM device 204 requires a high write margin. However, due to the design constraints of advanced technology beyond the 7 nm node, it is not possible to use weaker pull-up transistors and/or use wider/stronger pass-gate transistors. Therefore, the biasing circuitry outputs a bias voltage that is used to control to control the voltage supplied to the gate of the first header transistor 304, while the second header transistor 306 is always on because it is coupled to the reference voltage. Advantageously this increases the alpha ratio between the pull-up transistor and the pass gate-transistor, thus allowing for a wider write operation margin, and reduces both bit line and cell leakage. Furthermore, the reduction in bit line and cell leakage allows the CRAM device 204 to support products that require higher operating temperatures, which cause higher bit line and cell leakage. For example, the CRAM device 204 is able support an automobile that operate in the 125° C. spec.
The third bit cell 408 includes a word line (or address line) 401, a fifth inverter 403 comprising transistors 414 and 416, and a sixth inverter 405 comprising transistors 418 and 420. The fifth inverter 403 is formed by coupling the drain of transistor 414 to the drain of transistor 416. The source of transistor 414 is coupled to an output of the header circuitry 402. The source of transistor 416 is coupled to a reference voltage (i.e., ground). Therefore, transistor 414 operates as a pull-up transistor and transistor 416 operates as a pass-gate transistor. The sixth inverter 405 is formed by coupling the drain of transistor 418 to the drain of transistor 420. The source of transistor 418 is coupled to an output of the header circuitry 402. The source of transistor 420 is coupled to a reference voltage (i.e., ground). Therefore, transistor 418 operates as a pull-up transistor and transistor 420 operates as a pass-gate transistor.
Storage nodes are used to cross-couple the fifth inverter 403 and the sixth inverter 405 in order to store data contained in the CRAM device 400. The second storage node q1 is coupled to the gates of transistors 418 and 420 while the second inverse storage node qb1 is coupled to the gates of transistors 414 and 416. The second storage node q1 is also coupled to the drains of transistors 414 and 416 while the second inverse storage node qb1 is coupled to the drains of transistors 418 and 420.
The word line 401 is used to couple transistors 412 and 422 of the third bit cell 408. In one example, transistors 412 and 422 are n-type transistors. Word line 401 connects the gates of transistors 412 and 422. Transistors 412 and 422 are used to control access to the second storage node q1 and the second inverse storage node qb1. Second data node d1 is coupled to the drain of transistor 412. The second storage node q1 is coupled to the source of transistor 412. Second inverse data node db1 is coupled to the source of transistor 422. The second inverse storage node qb1 is coupled to the drain of transistor 422. Stated differently, adjacent (neighboring) bit cells can share common data and storage nodes
The fourth bit cell 410 includes a word line 435, a seventh inverter 413 comprising transistors 426 and 428, and an eighth inverter 415 comprising transistors 430 and 432. The seventh inverter 413 is formed by coupling the drain of transistor 426 to the drain of transistor 428. The source of transistor 426 is coupled to an output of the header circuitry 402. The source of transistor 428 is coupled to a reference voltage (i.e., ground). Therefore, transistor 426 operates as a pull-up transistor and transistor 428 operates as a pass-gate transistor. The eighth inverter 415 is formed by coupling the drain of transistor 430 to the drain of transistor 432. The source of transistor 430 is coupled to an output of the header circuitry 402. The source of transistor 432 is coupled to a reference voltage (i.e., ground). Therefore, transistor 430 operates as a pull-up transistor and transistor 432 operates as a pass-gate transistor.
Storage nodes are used to cross-couple the seventh inverter 413 and the eighth inverter 415. Stated differently, a third storage node q2 is coupled to the gates of transistors 430 and 432 while a third inverse storage node qb2 is coupled to the gates of transistors 426 and 428. The third storage node q2 is also coupled to the drains of transistors 426 and 428 while the third inverse storage node qb2 is coupled to the drains of transistors 430 and 432.
The word line 435 is used to couple transistors 424 and 434 of the fourth bit cell 410. In one example, transistors 424 and 434 are n-type transistors. Word line 435 connects the gates of transistors 424 and 434. Transistors 424 and 434 are used to control access to nodes q and qb. A third data node d2 is coupled to the drain of transistor 424. The third storage node q2 is coupled to the source of transistor 424. The third inverse data node db2 is coupled to the source of transistor 434. The third inverse storage node qb2 is coupled to the drain of transistor 434.
The header circuitry 402 includes a third header transistor 404 and a fourth header transistor 406. In one example, the third header transistor 404 and the fourth header transistor 406 are both p-type transistors. The source of the third header transistor 404 is coupled to the voltage source Vgg. The drain of the third header transistor 404 is coupled to the source of the fourth header transistor 406. The gate of the third header transistor 404 is coupled to the bias circuitry. The drain of the fourth header transistor 406 is coupled to the sources of transistors 314, 318, 326, and 330. The gate of the fourth header transistor 406 is coupled to reference voltage (e.g., ground). Although
Although header circuitry 302 and header circuitry 402 are shown as including two header transistors, header circuitry 302 and header circuitry 402 may include more than two header transistors.
Although the CRAM device 400 is illustrated as having one header circuitry coupled to a pair bit cells, this is for example purposes only. In one example, each bit cell is coupled to an individual header circuitry.
