Patent Application
20050275034
The invention generally relates to integrated circuit transistors and methods for forming the same and more particularly provides an improved methodology and structure that utilizes double spacers on one type of transistor and single spacers on the complementary type transistor to provide significant impurity and silicide spacing benefits corresponding to the different types of transistors.
The optimization of high performance CMOS (Complementary Metal Oxide Semiconductor) consists of getting the highest performance from both the NFET (N-type field effect transistor and PFET (P-type field effect transistor) devices. Often, as observed in CMOS, the best process for one device may cause lower performance in the other device. The NFET and PFET were found to each be optimum with a different sidewall spacer process. Unfortunately, the processes involved in building two different spacers on two different devices is challenging. The present invention provides a manufacturable way of optimizing the sidewalls on NFET and PFET devices separately, leading to the highest performance CMOS.
The invention provides a method of simultaneously forming different types of transistors on a single substrate and a resulting structure. The method begins by forming first spacers adjacent gate conductors on the substrate. Next, a first mask is formed over regions of the substrate to be occupied by second-type transistors (e.g. PFETs). The invention implants a first-type impurity in portions of the substrate adjacent the first spacers of first-type transistors (e.g., NFETs) and removes the first mask.
This process continues by forming an etch stop layer on all of the first spacers, on the substrate, and on exposed portions of the gate conductors. Next, second spacers are formed on the etch stop layer. After this step, all of the gate conductors have double spacers. Then, the invention forms a second mask over regions of the substrate to be occupied by the NFETs, implants a second-type impurity in portions of the substrate adjacent the second spacers of the PFETs, and then removes the second mask.
After this, the invention forms a third mask over regions of the substrate to be occupied by the PFETs, removes the second spacers from the NFETs, and then removes the third mask. Finally, the exposed areas of the substrate and the gate conductors not covered by the first spacers and the second spacers are silicided.
The etch stop layer prevents the process of removing the second spacers from affecting the first spacers. Before forming the first spacers, extension impurities can be implanted in regions of the substrate adjacent the gate conductors. The first-type and second-type impurities comprise source/drain impurities.
This process produces an integrated circuit structure that has NFETs and PFETs on the same substrate. The NFETs have “first” gate conductors and the PFETs have “second” gate conductors. First spacers are adjacent the first gate conductors and the second gate conductors. An etch stop layer is on the first spacers that are adjacent the second gate conductors. Second spacers are adjacent the first spacers that are adjacent the second gate conductors. The etch stop layer is positioned between the first spacers and the second spacers.
The second spacers are only adjacent the first spacers that are adjacent the second gate conductors and the second spacers are not adjacent the first spacers that are adjacent the first gate conductors. Similarly, the etch stop layer is only on the first spacers that are adjacent the second gate conductors and the etch stop layer is not on the first spacers that are adjacent the first gate conductors.
First-type impurity implants are in areas of the substrate adjacent the first spacers of the first gate conductors, and second-type impurity implants are in areas of the substrate adjacent the second spacers of the second gate conductors. Because the second spacers extend beyond the first spacers in the PFETs, the first-type impurity is spaced closer to the first gate conductors than the second-type impurity is spaced from the second gate conductors. Thus, as shown below, the invention provides a method and structure where the first spacer is made and the NFET is implanted, and then a second spacer is formed and the PFET is implanted. A dry nitride etch is then performed which selectively removes the silicon nitride second spacer, stopping selectively on the etch stop. This all dry removal process is more manufacturable than a wet etch, since it can be controlled to etch at a slower rate and it is not isotropic. This leaves a double nitride spacer on the PFETs and a single nitride spacer on the NFETs, giving the optimal spacer for each type of device. Furthermore, before silicide formation, the etch stop film on the nitride is removed, leading to a silicide edge very close to the gates for the NFETs, which is optimum for NFETs. The double nitride spacer on the PFETs prevents the silicide from getting too close to the PFET gate, which is optimum for PFETs.
These, and other, aspects of the present invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the present invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the present invention without departing from the spirit thereof, and the invention includes all such modifications.
The invention will be better understood from the following detailed description with reference to the drawings, in which:
The present invention and the various features and advantageous details thereof are explained more fully with reference to the nonlimiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the present invention. The examples used herein are intended merely to facilitate an understanding of ways in which the invention may be practiced and to further enable those of skill in the art to practice the invention. Accordingly, the examples should not be construed as limiting the scope of the invention.
The invention creates different spacers on both the NFET and PFET devices. One method that is not necessarily publicly known is called double spacer, where a narrow spacer is put in place and the NFET is implanted. Then a second spacer is put in place and the PFET is implanted. PFETs use boron as an implant species, and the boron diffuses much faster than arsenic during heat cycles. This requires that the boron deep junction be placed further away from the gate than the arsenic deep junction, thus the need for multiple spacers. However, the subsequent cobalt silicide formation is limited by the distance of the final second spacer, which keeps this silicide at a distance of several hundred angstroms. The NFET has been shown to have the highest performance when the silicide is very much closer to the gate, so the double spacer technique does not produce the fastest NFET. If a single narrow spacer was used, the NFET would be optimized, but the close proximity of the silicide for the PFET, along with deep junction overrun will make a poor performance PFET.
In view of the foregoing, the invention provides a method and structure where the first spacer is made and the NFET is implanted. Then, a second spacer is formed and the PFET is implanted. The spacers can comprise, for example, nitride films using an LTO (low temperature oxide) underlayer as the etch stop. Finally, after the second spacer is formed and implanted, a mask is used to block off the PFETS and cover them with photoresist. A dry nitride etch is then performed which selectively removes the silicon nitride second spacer, stopping selectively on the LTO etch stop. The photoresist is then removed, leaving a double nitride spacer on the PFETs and a single nitride spacer on the NFETs, giving the optimal spacer for each type of device. Furthermore, before silicide formation, the LTO etch stop film on the nitride will be removed by HF, leading to a silicide edge very close to the gates for the NFETs while the double nitride spacer on the PFETs prevents the silicide from getting too close to the gate.
One particular process for forming the inventive structure is discussed below. A first spacer is formed on a CMOS gate structure, by depositing a film, which can be silicon dioxide, silicon nitride, or polysilicon and etching the film to form a spacer adjacent to the gate. The spacer is generally 20-50 nm wide. A thin oxide (LTO) or nitride film is then deposited as an etch stop to a thickness of approximately 50-200 A. A second spacer is formed by depositing a film, (again nitride for example) to a thickness of 20-50 nm and again is made into a spacer by anisotropic etching of the film. This forms a double spacer.
More specifically, as shown in
Next, as shown in
As next shown in
Referring now to
Following this, as shown in
This process produces an integrated circuit structure that has NFETs 102 and PFETs 104 on the same substrate 100. The NFETs have “first” spacers 300, but the PFETs have the first 300 and “second” 502 spacers. The etch stop layer 500 is positioned between the first spacers 300 and the second spacers 502.
The second spacers 502 are only above the first spacers 300 that are adjacent the second gate conductors 104, and the second spacers 502 are not above the first spacers 300 that are adjacent the first gate conductors 102. Similarly, the etch stop layer 500 is only on the first spacers 300 that are adjacent the second gate conductors 104, and the etch stop layer 500 is not on the first spacers 300 that are adjacent the first gate conductors 102.
First-type impurity implants 404 are in areas of the substrate 100 adjacent the first spacers 300 of the first gate conductors 102, and second-type impurity implants 604 are in areas of the substrate 100 adjacent the second spacers 502 of the second gate conductors 104. Because the second spacers 502 extend further than the first spacers 300 in the PFETs (extend further from their respective gate conductors), the first-type impurity 404 is spaced closer to the first gate conductors 102 than the second-type impurity 604 is spaced from the second gate conductors 104.
This processing, goes from a double to dual spacer (D2D) where a double spacer is formed on the sides of the gates, meaning two distinct nitride spacers (for example) can be formed along side of one another to space the implants at the exact distance from the channel under the gate. Then, the second spacer is removed on only one device (NFET, for example) thus ending up with a different spacer on the NFET than appears on the PFET.
This process is shown in flowchart form in
This process continues by forming an etch stop layer on all of the first spacers, on the substrate, and on exposed portions of the gate conductors (910). Next, second spacers are formed on the etch stop layer (912). After this step, all of the gate conductors have double spacers. Then, in item 914 the invention forms a second mask over regions of the substrate to be occupied by the NFETs. In item 916, the invention implants a second-type impurity in portions of the substrate adjacent the second spacers of the PFETs, and then in item 918 removes the second mask.
After this, as shown in item 920, the invention forms a third mask over regions of the substrate to be occupied by the PFETs. In item 922, the invention removes the second spacers from the NFETs, and then removes the third mask (924). Finally, the exposed areas of the substrate and the gate conductors not covered by the first spacers and the second spacers are silicided (926).
One ordinarily skilled would understand that while the foregoing examples utilizes single and double spacers, the invention is equally applicable to many more spacer layers, so long as a distinction in overall spacer thickness is made between the different types of transistors. Therefore, the exact number of spacers utilized is not as important as insuring that one type of transistor has a larger spacer (which could be formed by using one or more additional spacer layers) so that the impurities for that type of transistor are spaced further from the channel region when compared to a different type of transistor that can exist with the impurity being placed closer to the channel region. Therefore, the invention could potentially use double spacers on one type of transistor and triple or even quadruple spacers on a different type of transistor to achieve the same result as using single and double spacers that are described the above.
Thus, as shown above, the invention provides a method and structure where the first spacer is made and the NFET is implanted, and then a second spacer is formed and the PFET is implanted. A dry nitride etch is then performed which selectively removes the silicon nitride second spacer, stopping selectively on the etch stop. This all dry removal process is more manufacturable than a wet etch, since it can be controlled to etch at a slower rate and is not isotropic. This leaves a double nitride spacer on the PFETs and a single nitride spacer on the NFETs, giving the optimal spacer for each type of device. Furthermore, before silicide formation, the etch stop film on the nitride is removed, leading to a silicide edge very close to the gates for the NFETs, which is optimum for NFETs. The double nitride spacer on the PFETs prevents the silicide from getting too close to the PFET gate, which is optimum for PFETs.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
