Patent Application
20230341448
Fabrication of integrated circuit devices may involve the processing of semiconductor wafers in a semiconductor processing chamber. Typical processes may involve deposition, in which a semiconductor material may be deposited, such as in a layer-by-layer fashion, as well as removal (e.g., etching) of material in certain regions of the semiconductor wafer. In commercial scale manufacturing, each wafer contains many copies of a set of semiconductor devices, and many wafers may be utilized to achieve the required volumes of semiconductor devices. Accordingly, the commercial viability of a semiconductor processing operation may depend, at least to some extent, upon within-wafer uniformity and upon wafer-to-wafer repeatability of process conditions. Consequently, efforts are made to ensure that each portion of a given wafer, as well as each wafer processed in a semiconductor processing chamber, is subjected to tightly-controlled processing conditions. Variations in processing conditions can bring about undesirable variations in deposition and etch rates, which, in turn, may bring about unacceptable variations in an overall fabrication process. Such variations may degrade circuit performance which, in turn, may give rise to unacceptable variations in performance of higher-level systems that utilize the integrated circuit devices. Accordingly, techniques for monitoring semiconductor processes with increased granularity, as well as an ability to make fine adjustments to process variables during fabrication, continues to be an active area of investigation.
The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In an embodiment, an apparatus, such as an apparatus to null out of phase lag of one or more measurement sensors utilized in a multi-station integrated circuit fabrication chamber, includes one or more measurement sensors disposed to measure voltage applied to, or current coupled to, the multi-station integrated circuit fabrication chamber. The apparatus also includes one or more analog-to-digital converters, coupled to an output port of a corresponding one of the one or more measurement sensors, to provide a digital representation of a radio frequency (RF) signal measured by the one or more measurement sensors. The apparatus also includes a processor, coupled to a memory, configured to compute a frequency response (which may be formulated as a frequency response matrix) from the digital representation of the measured RF signal. The apparatus also includes a digital inverter to divide or to multiply a digital representation of the RF signal measured by elements of the frequency response matrix. In an embodiment, the apparatus may auto correct a nulled-out phase lag.
In some embodiments, the digital inverter includes a digital voltage signal inverter or a digital current signal inverter. In some embodiments, the processor coupled to the memory is configured to compute the elements of the frequency response (which may be formulated as a frequency response matrix) during a calibration phase, and compute the inversion of the frequency response (which may be formulated as a frequency response matrix) to provide the phase lag of the one or more measurement sensors, which occurs during a process performed by the multi-station integrated circuit fabrication chamber. In some embodiments, the digital inverter includes two or more Fast Fourier Transform blocks arranged in parallel. In some embodiments, each of the two or more Fast Fourier Transform blocks is arranged in parallel with a corresponding delay circuit. In some embodiments, the digital inverter includes a logic circuit, which is configured to convey an output signal from the one or more measurement sensors to a first of the two or more Fast Fourier Transform blocks during a first clock portion and is configured to convey the output signal from the one or more measurement sensors to a second of the two or more Fast Fourier Transform blocks during a second clock portion. In some embodiments, the digital inverter includes a concatenation block configured to join output signal representations from the two or more Fast Fourier Transform blocks arranged in parallel into a single output signal representation. In some embodiments, the apparatus further includes a truncation block configured to truncate the size of the single output signal representation. In some embodiments, the truncation block includes a sliding window that is configured to adjust binary digits of the output signal representation.
In an embodiment, an apparatus is configured to null out a phase lag of a measurement sensor. The apparatus includes one or more analog-to-digital converters, coupled to an output port of a corresponding one of the one or more measurement sensors, to provide a digital representation of a radio frequency (RF) signal measured by the one or more measurement sensors. The apparatus also includes a processor, coupled to a memory, configured to compute a frequency response from the digital representation of the measured RF signal measured. The apparatus also includes a digital inverter to divide or multiply a digital representation of the RF signal measured by elements of the frequency response matrix. In some embodiments, a frequency response may be formulated as a frequency response matrix.
In some embodiments, the apparatus is adapted to null out a phase lag of one or more measurement sensors and includes an analog-to-digital converter to convert an analog signal, obtained from one or more output ports of a corresponding number of the one or more measurement sensors to measure voltage applied to (or current coupled to) a multi-station integrated circuit fabrication chamber, to a digital representation. The apparatus also includes a detector to detect the frequency content of the output signals of the one or more measurement sensors. The apparatus also includes a processor coupled to a memory to determine, in response to detecting the frequency content of the output signals of the one or more measurement sensors, a frequency response function of the one or more measurement sensors, the processor coupled to the memory additionally to null out the phase lag of the one or more measurement sensors by inverting a frequency response function of the one or more measurement sensors.
In some embodiments, determining the frequency response (which may include determining coefficients of a frequency response matrix) includes determining a crossing of the digital representation of the signal with a reference signal level. In some embodiments, the apparatus may also include determine, utilizing the crossing of the digital representation of the signal measured by the one or more measurement sensors, a frequency content of the RF signal and the nulled-out phase lag of the one or more measurement sensors. In some embodiments, the crossing may correspond to crossing a RF signal ground. In some embodiments, the one or more measurement sensors include a capacitive voltage transformer operating at any frequency between about 300 kHz and 100 MHz. In some embodiments, the one or more measurement sensors includes a current measurement sensor operating at a frequency of between about 300 kHz and about 100 MHz. In some embodiments, the nulling out of phase lag of the one or more measurement sensors corresponds to canceling phase lag introduced by the one or more measurement sensors. In some embodiments, the frequency response, which may be formulated as a frequency response matrix, forms a frequency response function. In some embodiments, the processor is further configured to provide an estimate of RF power coupled to the multi-station integrated circuit fabrication chamber utilizing a signal received from the one or more measurement sensors that is advanced by an amount corresponding to the phase lag.
In an embodiment, an apparatus is adapted to null out a phase lag of one or more measurement sensors, including an analog-to-digital converter to convert an analog signal, obtained from one or more output ports of a corresponding number of the one or more measurement sensors to measure voltage applied to (or current coupled to) a multi-station integrated circuit fabrication chamber, to a digital representation. The apparatus also includes a detector to detect the frequency content of the output signals of the one or more measurement sensors. The apparatus also includes a processor coupled to a memory to determine, in response to detecting the frequency content of the output signals of the one or more measurement sensors, a frequency response function of the one or more measurement sensors, the processor coupled to the memory additionally to null out the phase lag of the one or more measurement sensors by inverting a frequency response function of the one or more measurement sensors.
In some embodiments, detecting the frequency content of the output signals of the one or more sensors includes detecting a crossing of the digital representation of the obtained analog signal with a reference signal. In some embodiments, the reference signal corresponds to a radio frequency (RF) ground. In some embodiments, a first measurement sensor of the corresponding number of the one or more measurement sensors includes a voltage measurement sensor. In some embodiments, a second measurement sensor of the corresponding number of measurement sensors includes a current measurement sensor. In some embodiments, the processor applies a phase lag correction to measurements performed by the voltage measurement sensor and the current measurement sensor to obtain a corrected instantaneous voltage measurement and corrected instantaneous current measurement. In some embodiments, the processor further operates to compute RF power delivered to the multi-station integrated circuit fabrication chamber by computing the product of a corrected instantaneous voltage and a corrected instantaneous current. In some embodiments, the processor further operates to compute a moving average of successive computations of RF power delivered to the multi-station integrated circuit fabrication chamber to estimate average RF power delivered to the multi-station integrated circuit fabrication chamber. In some embodiments, the processor further operates to compute real-time power delivered to the multi-station integrated circuit fabrication chamber utilizing real-time phase-corrected instantaneous voltage and real-time phase-corrected instantaneous current. In some embodiments, the processor further operates to modify an amount of power generated by a power generator, for coupling to the multi-station integrated circuit fabrication chamber, responsive to computing the real-time power delivered. In some embodiments, the phase lag of the one or more measurement sensors is determined in terms of clock periods.
In an embodiment, an apparatus is configured to estimate radio frequency (RF) power coupled to a load, including a current sensor having a current sensor frequency response function and a voltage sensor having a voltage sensor frequency response function. The apparatus also includes a first analog-to-digital converter coupled to an output port of the current sensor. The apparatus also includes a second analog-to-digital converter coupled to an output port of the voltage sensor; and a processor coupled to a memory to obtain digital representations of instantaneous current and to obtain digital representations of instantaneous voltage, to obtain a phase lag of the instantaneous current and the instantaneous voltage, and to invert the frequency response function of the current sensor and the frequency response function of the voltage sensor to counteract for the obtained phase lag of the instantaneous current and the instantaneous voltage. In some embodiments, the current sensor of the apparatus includes an inductive current transformer. In some embodiments, the voltage sensor includes a capacitive voltage transformer. In some embodiments, the current sensor and the voltage sensor operate at any frequency between about 300 kHz and about 100 MHz.
In an embodiment, an apparatus is adapted to null out a phase lag of one or more measurement sensors, including: an analog-to digital converter to convert an analog signal, obtained from one or more output ports of a corresponding number of the one or more measurement sensors to measure voltage applied to or current coupled to a multi-station integrated circuit fabrication chamber, to a digital representation. The apparatus also includes a detector to detect a sensor response characteristic from the digital representation of the obtained analog signal. The apparatus also includes a processor coupled to a memory to determine, in response to detecting the sensor response characteristic, at least one frequency component present in the digital representation of the obtained analog signal, the processor coupled to the memory additionally to null out the phase lag of the one or more measurement sensors by inverting a frequency response function of the one or more measurement sensors.
In some embodiments, the detector of the apparatus detects the sensor response characteristic by determining a crossing of the digital representation of the obtained analog signal with a reference signal. In some embodiments, the detector detects the sensor response characteristic utilizing an analog representation of the reference signal. In some embodiments, the detector detects the sensor response characteristic utilizing a digital representation of the reference signal. In some embodiments, the processor is coupled to the memory and is configured to determine the at least one frequency component present in the digital representation of the obtained analog signal in response to detecting the crossing of the digital representation of the obtained analog signal with the reference signal. In some embodiments, the processor coupled to the memory performs the inverting of the frequency response function of the one or more measurement sensors in the frequency domain. In some embodiments, the processor coupled to the memory performs the inverting of the frequency response function of the one or more measurement sensors in the time domain.
The various embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements.
In particular embodiments, determination of phase lag in radio frequency (RF) signal sensors may be utilized in conjunction with a variety of equipment utilized in the fabrication of integrated circuits, such as equipment related to plasma-based integrated circuit fabrication. For example, in a multi-station integrated circuit fabrication chamber, in which multiple semiconductor wafers simultaneously undergo deposition or etching processes, determination of phase lag in voltage and current signals provided to the fabrication chamber may allow precise computation, in real-time, of RF power conveyed to the stations of the fabrication chamber. Accordingly, in the event that conditions within the fabrication chamber give rise to changes in the input impedance of the fabrication chamber (which may cause power directed to the input port of the fabrication chamber to be reflected back to the RF power source), component values of an input impedance matching network may be adjusted by precise amounts in response to such changes. Such precise adjustment of component values of the impedance matching network may enable coupling of a specific quantity of power into the fabrication chamber while minimizing power reflected from the fabrication chamber. Consequently, semiconductor processes conducted within a multi-station fabrication chamber may be performed with greater accuracy which may, in turn, result in lower defect ratios and higher yields of devices formed utilizing the fabrication chamber.
In certain embodiments, determination of phase lag in RF signal sensors may allow precise characterization of current and voltage parameters and/or waveforms that bring about undesirable or abnormal operation of an integrated circuit fabrication chamber. For example, if plasma within a fabrication chamber undergoes formation of an electric arc, which may result in an unwanted formation of compounds in a gaseous or plasma state within the fabrication chamber, precise current and/or voltage conditions may be detected and characterized. Such characterization may operate to prevent future occurrences of arcing, perhaps by modifying current and/or voltage parameters that may have previously led to arcing within the fabrication chamber.
Particular embodiments may represent improvements over other approaches of measuring or estimating phase lag in RF signal sensors for use in integrated circuit fabrication processes. For example, in one such approach, phase lag of RF signal sensors may be estimated by utilizing two-dimensional calibration circuits, which may be activated and analyzed in a post-processing environment. Consequently, effects of voltage and/or current sensor measurement errors may go unnoticed until after integrated circuit processing operations are completed, which may allow abnormal conditions to persist within an integrated circuit processing chamber for extended periods of time.
Further, such analog postprocessing utilizing calibration circuits may not predict and/or characterize RF signal sensor phase lag over all frequencies of interest, such as frequencies as low as about 300 kHz and frequencies as high as about 100 MHz. Accordingly, in an effort to characterize phase lag in RF signal sensors, a group of calibration circuits may be constructed, wherein each calibration circuit of the group may provide phase lag information over a specified portion of a about 300 kHz to about 100 MHz range of frequencies. Consequently, characterization of phase lag over such a wide range of frequency may require construction of numerous calibration circuits.
Certain embodiments and implementations may be utilized in conjunction with a number of wafer fabrication processes, such as various plasma-enhanced atomic layer deposition (ALD) processes (e.g., ALD1, ALD2), various plasma-enhanced chemical vapor deposition (e.g., CVD1, CVD2, CVD3) processes, or may be utilized on-the-fly during single deposition processes. In certain embodiments, a RF power generator having multiple output ports may be utilized at any signal frequency, such as at frequencies between about 300 kHz and about 60 MHz, which may include frequencies of about 400 kHz, about 1 MHz, about 2 MHz, about 13.56 MHz, and about 27.12 MHz. However, in other embodiments, RF power generators having multiple output ports may operate at any signal frequency, which may include relatively low frequencies, such as between about 50 kHz and about 300 kHz, as well as higher signal frequencies, such as frequencies between about 60 MHz and about 100 MHz, virtually without limitation.
It should be noted that although particular embodiments described herein may show and/or describe multi-station semiconductor fabrication chambers comprising 4 process stations, claimed subject matter may embrace multi-station integrated circuit fabrication chambers comprising any number of process stations. Thus, in certain embodiments, individual output ports of a RF power generator having multiple output ports may be assigned to a process station of a multi-station fabrication chamber having, for example, 2 process stations or 3 process stations. In other embodiments individual output ports of a RF power generator having multiple output ports may be assigned to process stations of a multi-station integrated circuit fabrication chamber having a larger number of process stations, such as 5 process stations, 6 process stations, 8 process stations, 10 process stations, or any other number of process stations, virtually without limitation.
Additionally, although particular embodiments described herein may show and/or describe utilization of a single, relatively low frequency RF signal, such as a frequency of between about 300 kHz and about 2 MHz, as well as a single, relatively high-frequency RF signal, such as a frequency of between about 2 MHz and about 100 MHz, claimed subject matter may embrace the use of any number of frequencies below about 2 MHz as well as any number of frequencies above about 2 MHz. Further, although particular embodiments, such as described herein, may relate to measurement of characteristics of signals coupled to a multi-station integrated circuit fabrication chamber, which may include voltage and current signals coupled to a fabrication chamber utilizing a two-conductor transmission line (e.g., a coaxial cable), claimed subject matter is intended to embrace measurement of other signal characteristics. For example, particular embodiments may relate to measurement of characteristics such as electric field strength and/or magnetic field strength in a rectangular or circular waveguide, a strip line, or any other type of transmission media coupled to a multi-station integrated circuit fabrication chamber.
Manufacture of semiconductor devices typically involves depositing or etching of one or more thin films on or over a planar or non-planar substrate in an integrated fabrication process. In some aspects of an integrated process, it may be useful to deposit thin films that conform to unique substrate topography. One type of reaction that is useful in many instances may involve chemical vapor deposition (CVD). In typical CVD processes, gas phase reactants introduced into stations of a reaction chamber simultaneously undergo a gas-phase reaction. The products of the gas-phase reaction deposit on the surface of the substrate. A reaction of this type may be driven by, or enhanced by, presence of a plasma, in which case the process may be referred to as a plasma-enhanced chemical vapor deposition (PECVD) reaction. As used herein, the term CVD is intended to include PECVD unless otherwise indicated. CVD processes have certain disadvantages that render them less appropriate in some contexts. For instance, mass transport limitations of CVD gas phase reactions may bring about deposition effects that exhibit thicker deposition at top surfaces (e.g., top surfaces of gate stacks) and thinner deposition at recessed surfaces (e.g., bottom corners of gate stacks). Further, in response to some semiconductor die having regions of differing device density, mass transport effects across the substrate surface may result in within-die and within-wafer thickness variations. Thus, during subsequent etching processes, thickness variations can result in over-etching of some regions and under-etching of other regions, which can degrade device performance and die yield. Another difficulty related to CVD processes is that such processes are often unable to deposit conformal films in high aspect ratio features. This issue can be increasingly problematic as device dimensions continue to shrink. These and other drawbacks of particular aspects of wafer fabrication processes are discussed in relation to
In another example, some deposition processes involve multiple film deposition cycles, each producing a discrete film thickness. For example, in atomic layer deposition (ALD), thickness of a deposited layer may be limited by an amount of one or more film precursor reactants, which may adsorb onto a substrate surface, so as to form an adsorption-limited layer, prior to the film-forming chemical reaction itself. Thus, a feature of ALD involves the formation of thin layers of film, such as layers having a width of a single atom or molecule, which are used in a repeating and sequential matter. As device and feature sizes continue to be reduced in scale, and as three-dimensional devices and structures become more prevalent in integrated circuit (IC) design, the capability of depositing thin conformal films (e.g., films of material having a uniform thickness relative to the shape of the underlying structure) continues to gain in importance. Thus, in view of ALD being a film-forming technique in which each deposition cycle operates to deposit a single atomic or molecular layer of material, ALD may be well-suited to the deposition of conformal films. Typical device fabrication processes involving ALD may include multiple ALD cycles, which may number into the hundreds or thousands, may then be utilized to form films of virtually any desired thickness. Further, in view of each layer being thin and conformal, a film that results from such a process may conform to a shape of any underlying device structure. In certain implementations, an ALD cycle may include the following steps:
Exposure of the substrate surface to a first precursor.
Purge of the reaction chamber in which the substrate is located.
Activation of a reaction of the substrate surface, typically with a plasma and/or a second precursor.
Purge of the reaction chamber in which the substrate is located.
The duration of each ALD cycle may typically be less than about 25 seconds or less than about 10 seconds or less than about 5 seconds. The plasma exposure step (or steps) of the ALD cycle may be of a short duration, such as a duration of about 1 second or less.
Turning now to the figures,
In
Showerhead 106 may operate to distribute process gases and/or reactants (e.g., film precursors) toward substrate 112 at the process station, the flow of which may be controlled by one or more valves upstream from the showerhead (e.g., valves 120, 120A, 105). In the embodiment depicted in
In
In some embodiments, plasma ignition and maintenance conditions are controlled with appropriate hardware and/or appropriate machine-readable instructions in a system controller which may provide control instructions via a sequence of input/output control (IOC) instructions. In one example, the instructions for bringing about ignition or maintaining a plasma are provided in the form of a plasma activation recipe of a process recipe. In some cases, process recipes may be sequentially arranged, so that at least some instructions for the process can be executed concurrently. In some embodiments, instructions for setting one or more plasma parameters may be included in a recipe preceding a plasma ignition process. For example, a first recipe may include instructions for setting a flow rate of an inert (e.g., helium) and/or a reactant gas, instructions for setting a plasma generator to a power set point and time delay instructions for the first recipe. A second, subsequent recipe may include instructions for enabling the plasma generator and time delay instructions for the second recipe. A third recipe may include instructions for disabling the plasma generator and time delay instructions for the third recipe. It will be appreciated that these recipes may be further subdivided and/or iterated in any suitable way within the scope of the present disclosure. In some deposition processes, a duration of a plasma strike may correspond to a duration of a few seconds, such as from about 3 seconds to about 15 seconds, or may involve longer durations, such as durations of up to about 30 seconds, for example. In certain embodiments described herein, much shorter plasma strikes may be applied during a processing cycle. Such plasma strike durations may be on the order of less than about 50 milliseconds, with about 25 milliseconds being utilized in a specific example.
For simplicity, processing apparatus 100 is depicted in
In some embodiments, software for execution by way of a processor of system controller 190 may include input/output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of deposition and deposition cycling of a substrate may include one or more instructions for execution by system controller 190. The instructions for setting process conditions for an ALD/CFD deposition process phase may be included in a corresponding ALD/CFD deposition recipe phase. In some embodiments, the recipe phases may be sequentially arranged, so that all instructions for a process phase are executed concurrently with that process phase.
Other computer software and/or programs stored on a mass storage device of system controller 190 and/or a memory device accessible to system controller 190 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program. A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 108 (of
A process gas control program may include code for controlling gas composition and flow rates and for flowing gas into one or more process stations prior to deposition to bring about stabilization of the pressure in the process station. In some embodiments, the process gas control program includes instructions for introducing gases during formation of a film on a substrate in the reaction chamber. This may include introducing gases for a different number of cycles for one or more substrates within a batch of substrates. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc. The pressure control program may include instructions for maintaining the same pressure during the deposition of differing number of cycles on one or more substrates during the processing of the batch.
A heater control program may include code for controlling the current to heating unit 110 that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate.
In some embodiments, there may be a user interface associated with system controller 190. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.
In some embodiments, parameters adjusted by system controller 190 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions, etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface. The recipe for an entire batch of substrates may include compensated cycle counts for one or more substrates within the batch in order to account for thickness trending over the course of processing the batch.
Signals for monitoring the process may be provided by analog and/or digital input connections of system controller 190 from various process tool sensors. The signals for controlling the process may be output by way of the analog and/or digital output connections of process tool 150. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Sensors may also be included and used to monitor and determine the accumulation on one or more surfaces of the interior of the chamber and/or the thickness of a material layer on a substrate in the chamber. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.
System controller 190 may provide program instructions for implementing the above-described deposition processes. The program instructions may control a variety of process parameters, such as DC power level, pressure, temperature, number of cycles for a substrate, amount of accumulation on at least one surface of the chamber interior, etc. The instructions may control the parameters to operate in-situ deposition of film stacks according to various embodiments described herein.
For example, the system controller may include control logic for performing the techniques described herein, such as determining an amount of accumulated deposition material currently on at least an interior region of the deposition chamber interior, applying the amount of accumulated deposition material determined in (a), or a parameter derived therefrom, to a relationship between (i) a number of ALD cycles required to achieve a target deposition thickness, and (ii) a variable representing an amount of accumulated deposition material, in order to obtain a compensated number of ALD cycles for producing the target deposition thickness given the amount of accumulated deposition material currently on the interior region of the deposition chamber interior, and performing the compensated number of ALD cycles on one or more substrates in the batch of substrates. The system may also include control logic for determining that the accumulation in the chamber has reached an accumulation limit and stopping the processing of the batch of substrates in response to that determination, and for causing a cleaning of the chamber interior.
In addition to the above-identified functions and/or operations performed by system controller 190 of
In particular embodiments, multi-station integrated circuit fabrication chamber 165 may comprise input ports in addition to input port 167 (additional input ports not shown in
It may be appreciated that regardless of the frequencies of RF voltage and current signals coupled to multi-station integrated circuit fabrication chamber 165, it may be advantageous to measure such signals with an increased degree of precision. For example, for sinusoidal voltage and current signals that are in phase with each other, average RF power coupled to multi-station integrated circuit fabrication chamber 165 may be computed substantially in accordance with expression (1) below:
Wherein Vpeak corresponds to a peak voltage signal and wherein Ipeak corresponds to a peak current signal. However, it may be appreciated that that expression (1) refers to a condition in which a sinusoidal voltage signal and a sinusoidal current signal are in phase with each other. Accordingly, to account for instances in which sinusoidal voltage signals and current signals are not in phase with each other, expression (2) may be utilized, in which:
Wherein ϕ of expression (2) represents a phase angle between a voltage signal and a current signal.
Accordingly, from expression (2) it may be apparent that if a significant phase lag (ϕ) exists between the voltage and current signals, average power coupled to a fabrication chamber, such as multi-station integrated circuit fabrication chamber 165, may be decreased. For example, in response to a phase angle (ϕ) of 30° between voltage and current signals coupled to a fabrication chamber, Pavg may be reduced by approximately 13.4%. For more significant values of phase lag (ϕ), such as 60°, Pavg may be reduced by larger amounts, such as 50%. Further, for instances in which a phase angle (ϕ) between voltage and current signals approaches 90°, average power may be reduced to a negligible value (e.g., Pavg=0).
In the embodiment of
In particular embodiments, RF power source 225A may operate to automatically (e.g., without user input) adjust a frequency of an output signal so as to maintain a desired output power level. Thus, in response to changes in input impedance presented by particular pressure/gas combinations within multi-station integrated circuit fabrication chamber 165, RF power source 225A may automatically tune to a nearby frequency, such as a frequency within ±10% of a selected frequency. Such automatic tuning of RF power source 225A may bring about a capability to deliver a relatively constant threshold amount of RF power even during conditions under which impedance presented by chamber 165 may be fluctuating between or among two or more values of real or complex impedance.
As shown in
Similarly, graph 210A of
Thus, in
In the embodiment of
Output signals from analog-to-digital converter 279A may be coupled to an input port of LF filtering module 284 and to an input port of HF filtering module 285. Likewise, output signals from analog-to-digital converter 279B may be coupled to an input port of LF filtering module 282 and to an input port of HF filtering module 283. In the embodiment of
In the context of this disclosure, it is recognized that in high-frequency domains, such as domains in which a frequency of operation exceeds about 50 kHz, inductive current and capacitive voltage sensors may be considered “invasive” in so far as the sensors introduce frequency-dependent alterations, which distort the measured quantity (e.g., current, voltage, electric field, magnetic field). Thus, also in this context, the process of nullifying/eliminating frequency-dependent effects including introduction of phase delay (phase lag) in signals output from a sensor is referred to as an inversion process. To verify that such nullifying/eliminating of frequency-dependent effects may be verified via verification tools 292, which may be utilized to determine when a match between output signals of LF inversion module 288 and LF zero crossing module 290 is obtained. Verification tools 292 may additionally determine when a match between HF inversion module 289 and HF zero crossing module 291 is obtained. When such matches are obtained, values for phase lag in the relatively controlled environment of
In particular embodiments, and as previously mentioned herein, phase lag introduced by an inductive current transformer may significantly exceed the phase lag introduced by a capacitive voltage transformer. Accordingly, in some embodiments, such as that of
In such instances, verification tools 292 may operate to perform comparisons between output signals from LF filtering module 282 and output signals from LF zero crossing module 286. Similarly, verification tools 292 may perform comparisons between output signals from HF filtering module 283 and HF zero crossing module 287. Further, verification tools 292 may be utilized to determine accuracy of steady-state power measurements performed by moving average module 299.
Accordingly, returning now to
In particular embodiments, RF power sources 302 and 304 may operate to automatically (e.g., without user input) adjust frequency of an output signal so as to maintain a desired output power level. Thus, in response to changes in input impedance presented by particular pressure/gas combinations within multi-station integrated circuit fabrication chamber 165, for example, RF power sources 302 and 304 may automatically tune to a nearby frequency, such as a frequency within +10%/o of a selected frequency. Such automatic tuning of RF power sources 302 and 304 may bring about a capability to deliver a relatively constant threshold amount of RF power even during conditions under which impedance presented by chamber 165 may be fluctuating between or among two or more values of real or complex impedance.
Signals from RF power sources 302 and 304 may be combined using combiner 306, which may operate to combine output signals from the RF power sources for transmission along a single transmission line, such as a single coaxial cable, for example. Output signals from combiner 306 may be coupled to an input port of impedance matching network 308, which may operate to match the impedance of inductive current transformer 310 and multi-station integrated circuit fabrication chamber 165 to the characteristic impedance of transmission line 307. In particular embodiments, impedance matching network 308 may include reactive components, such as inductors and capacitors arranged according to various circuit topologies, which may operate to maximize power transferred from combiner 306 to inductive current transformer 310 and multi-station integrated circuit fabrication chamber 165. In particular embodiments, matching network 308 may operate to reduce a voltage standing wave ratio (VSWR) on transmission line 307 to below a threshold value (e.g., 1.25:1, 1.5:1, 1.75:1, etc.).
In the embodiment of
Capacitive voltage transformer 305, in contrast, may present a high impedance (such as a virtually infinite impedance) to RF signals from impedance matching network 308. Thus, RF voltage signals from impedance matching network 308 may not be significantly altered by the presence of capacitive voltage transformer 305. In particular embodiments, a capacitive voltage transformer may operate to transform a high-amplitude voltage signal into a low-voltage signal. Such transformation utilizes a frequency-dependent transfer function, which may reflect parasitic inductances, which also represent phase lag introduced by the capacitive voltage transformer. In a validation set up, such as described in reference to
An output port of capacitive voltage transformer 305 is coupled to an input port of analog-to-digital converter 316. Similarly, an output port of inductive current transformer 310 is coupled to an input port of analog-to-digital converter 322. In particular embodiments, analog-to-digital converters 316 and 322 utilize a successive-approximation approach in which an input signal is held steady by a sample-and-hold circuit while a flash analog-to-digital converter quantizes the sampled signal into a relatively small number of binary digits (e.g., 3 binary digits). The binary digits are then coupled to a digital-to-analog converter, which may be accurate to, for example, 12 binary digits. An analog output signal from the digital-to-analog converter may then be subtracted from the input signal to the analog-to-digital converter (316 or 322). The difference between the analog output signal from the digital-to-analog converter and the input signal to the analog-to-digital converter, which may be considered a “residue,” is amplified and coupled to a subsequent stage of the analog-to-digital converter, and the above-described process may be repeated. In such a successive-approximation architecture, the amplified residue is conveyed through successive stages of the converter, thereby providing small number of binary digits at each stage (e.g., 3 binary digits) until the residue reaches a subsequent flash analog-to-digital converter which operates to resolve the least-significant binary digits.
It should be noted that although analog-to-digital converters 316/322 are described as employing a successive-approximation architecture, in other embodiments, alternative architectures may be utilized. For example, in some embodiments, an analog-to-digital converter architecture may be selected after performing a trade-off analysis, which may balance accuracy with frequency performance. Accordingly, in particular embodiments, an analog-to-digital converter may utilize a pipelined architecture or any other conventional or unconventional architecture according to particular system parameters and requirements.
Digitized measurements of a voltage signal from analog-to-digital converter 316 may be loaded into a first matrix, depicted as [V′] 318 in
An output signal from zero crossing module 330 is coupled to an input port of frequency module 332, which may operate to utilize zero crossing characteristics of the current signal to determine a precise operating frequency of one or more of RF power sources 302/304. In particular embodiments, zero crossing modules 320 and 330 may operate by determining a period in between successive zero crossings of a digitized signal, multiplying by a factor of 2, and computing the reciprocal of the determined period. It should be noted that although the embodiment of
Lookup tables 295 and 297, which store characterized voltage and current waveforms determined in the more controlled environment of
However, in other embodiments, values for voltage signal phase lag may be arranged in the form of N×2 matrix that may be arranged in terms of frequency and corresponding phase lags expressed in terms of units of time, so as to comprise a form substantially in accordance with expression (4) below:
In addition, in other embodiments, values for voltage signal phase lag may be arranged in the form of N×2 matrix that may be arranged in terms of frequencies and corresponding phase lags expressed in terms of clock cycles, so as to comprise a form substantially in accordance with expression (5) below:
Likewise, values for current signal phase lag may be arranged as a function of frequency in the form of a N×2 matrix, which are stored in matrix 338 [I]. Further, arrangement of current signal phase lag as a function of frequency may be similar to the voltage phase lag matrices of expressions (3), (4), and (5). In particular embodiments, values for current signal phase lag may exceed those of voltage signal phase lag.
In response to determining voltage, phase-corrected values for digitized voltage may be stored in corrected voltage signal matrix 336 [V]. Similarly, phase-corrected values for digitized current may be stored in corrected current signal matrix 338 [I]. Phase-corrected voltage and current values may be coupled to input ports of multiplier module 340. Multiplier module 340 may compute average RF power utilizing expression (2), repeated here for convenience:
Wherein ϕ of expression (2) represents a phase angle between a voltage signal and a current signal. Thus, since phase angle ϕ has been accurately determined in accordance with the above-described components of
Digitized voltage values stored in voltage signal matrix 336 may be utilized by F1/F2 filtering module 362 to separate frequency components into constituent components (e.g., first and second frequencies). Min/max detect module 380 may then operate to determine, for example, DC bias present in digitized voltages. Mm/max detect module 380 may additionally operate to determine peak voltage values present in digitized voltages. In a similar manner, digitized current values stored in current signal matrix 338 may be utilized by F1/F2 filtering module 364 bring about separation of frequency components into constituent components (e.g., first and second frequencies). Min/max detect module 382 may then operate to determine, for example, DC bias present in digitized currents. Min/max detect module 382 may additionally operate to determine peak current values present in digitized currents.
Thus, the apparatus of
It should be noted that in particular embodiments, the embodiment of
It should be noted that although certain embodiments described herein involve detection of zero crossing of current and voltage signals, (e.g., utilizing zero crossing modules 320 and 330) nulling of phase lag of a sensor may be performed via other approaches. However, regardless of an approach utilized to characterize a sensor's frequency response, such response can be represented in a frequency domain in a closed form, such as when the sensor's frequency response is relatively simple. In some instances, a closed form expression of a sensor's frequency response may involve first or second order lags, such as may be found responsive to use of a low-pass filter. In other instances, a frequency response may be represented via a Fast Fourier Transform when a sensor's frequency response cannot be conveniently described via a closed form expression. Responsive to determination of a sensor's frequency response, such response may then be inverted, such as via inversion of a closed form expression or by way of inverting of a matrix representation of the sensor's frequency response. Accordingly, the inverted representation of the sensor's frequency response may be applied to a signal, which may operate to remove or counteract (at least in part) the effects of phase lag introduced by the sensor.
The method may continue at 420, which may involve detection of a crossing of a digital representation of the obtained analog signal with a digital or analog representation of a reference signal level. In certain embodiments, a reference signal level may correspond to a RF signal ground, in which case 420 may involve use of a zero-crossing detector, such as zero crossing detectors 320/330 of
In the embodiment of
In the embodiment of
V
measured(f)=Vtrue(f)×HCVT(f) (6)
Similarly, during a calibration operation, a transfer function for ICT 278A can be determined substantially in accordance with expression (7):
I
measured(f)=Itrue(f)×HICT(f) (7)
Thus, from expression (6) and (7) it may be recognized that to determine phase-corrected values (such as automatically phase-corrected values) for measured current and measured voltage, and inversion operation (e.g., division, or multiplication by an inverse) can be performed. Thus, rearranging expressions (6) and (7), expressions (8) and (9) can be formed, as follows:
It should be noted that although not explicitly shown in
As shown in
In response to a division (or multiplication by an inverse) operation (indicated at 625), an inverse Fast Fourier transform (FFT−1) may be performed (such as by FFT−1 module 630) on the resulting signal. In some embodiments, an inverse Fast Fourier transform may result in a digital representation of time domain signals representing Vtrue(f) and Itrue(f) of expressions (8) and (9). The resulting inverted transfer function, in which the apparent effect of phase lag in V(t) and in I(t), are removed from the frequency-transformed representation of V(t) (e.g., Vtrue(f) in expression (8)) and from the frequency-transformed representation of I(t) (e.g., Itrue(f) in expression (9). In response to inversion of the transfer function (e.g., HCVT(f) and HICT(f)) of expressions (8) and (9), an analog representation of Vtrue(f) and Itrue(f) is provided at an output port of digital-to-analog converter 640. As explained further with reference to
Also as explained further in reference to
The method may continue at block 725, which may include accessing transfer function H(ω) values stored in a memory. In some embodiments, block 725 may involve accessing a memory, such as memory 520A and/or memory 520B of a spectrum analyzer, that contains a frequency-domain representation of a voltage sensor (e.g., Hν(ω)). Block 730 may include dividing (or multiplying by an inverse) the frequency-domain representation of a voltage signal ((e.g., V(ω)) by a frequency response function (e.g., voltage transfer function) a voltage sensor ((e.g., Hν(ω)). Block 735 may include performing an inverse Fast Fourier transform (FFT−1) to arrive at a digital representation of phase-corrected signals from a voltage sensor. Block 740 may include concatenating delayed and non-delayed digital representations of phase-corrected signals from a voltage sensor. Block 745 may include truncating, such as by way of a sliding window, to reduce the bit length of the digital representations of phase-corrected signals from a voltage sensor. Block 750 may include filtering, such as utilizing a low-pass filter, to obtain frequency components, such as low-frequency components and high-frequency components. Block 755 may include performing matrix multiplication operations to determine LF power as well as performing matrix multiplication operations to determine HF power. Block 760 may include computing a moving average for power measurements resulting the matrix multiplication operations of block 755. Block 760 may include applying a moving average filter having a time window of between about 100 μs (or more or less) to about 10 ms (or more or less), which may operate to damp undesirably large fluctuations in computed power.
The method may continue at block 825, which may include accessing transfer function H(w) values stored in a memory. In some embodiments, block 825 may involve accessing a memory, such as memory 520A and/or memory 520B of a spectrum analyzer, that contains a frequency-domain representation of a current measurement signal (e.g., HI(ω)). Block 830 may include dividing (or multiplying by an inverse) the frequency-domain representation of a current measurement signal ((e.g., I(ω)) by a frequency response function (e.g., current sensor transfer function, HI(ω)). Block 835 may include performing an inverse Fast Fourier transform (FFT−1) to arrive at a digital representation of phase-corrected signal from a current measurement sensor. Block 840 may include concatenating delayed and non-delayed digital representations of phase-corrected signals from a current measurement sensor. Block 845 may include truncating, such as by way of a sliding window, to reduce the bit length of the digital representations of phase-corrected signals from a current measurement sensor. Block 850 may include filtering, such as utilizing a low-pass filter, to obtain frequency components, such as low-frequency components and high-frequency components. Block 855 may include performing matrix multiplication operations to determine LF power as well as performing matrix multiplication operations to determine HF power. Block 860 may include computing a moving average for power measurements resulting from the matrix multiplication operations of block 855. Block 860 may include applying a moving average filter having a time window of between about 100 μs (or more or less) to about 10 ms (or more or less), which may operate to damp undesirably large fluctuations in computed power.
Referring back to
Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers or field-programmable gate arrays (FPGA) or FPGA with system-on-a-chip (SoC) that that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.
The controller, in some embodiments, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
In the foregoing detailed description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments or embodiments. The disclosed embodiments or embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as to not unnecessarily obscure the disclosed embodiments or embodiments. While the disclosed embodiments or embodiments are described in conjunction with the specific embodiments or embodiments, it will be understood that such description is not intended to limit the disclosed embodiments or embodiments.
The foregoing detailed description is directed to certain embodiments or embodiments for the purposes of describing the disclosed aspects. However, the teachings herein can be applied and implemented in a multitude of different ways. In the foregoing detailed description, references are made to the accompanying drawings. Although the disclosed embodiments or embodiment are described in sufficient detail to enable one skilled in the art to practice the embodiments or embodiment, it is to be understood that these examples are not limiting; other embodiments or embodiment may be used and changes may be made to the disclosed embodiments or embodiment without departing from their spirit and scope. Additionally, it should be understood that the conjunction “or” is intended herein in the inclusive sense where appropriate unless otherwise indicated; for example, the phrase “A, B, or C” is intended to include the possibilities of “A,” “B,” “C,” “A and B,” “B and C,” “A and C,” and “A, B, and C.”
In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically includes a diameter of 200 mm, or 300 mm, or 450 mm. The foregoing detailed description assumes embodiments or embodiments are implemented on a wafer, or in connection with processes associated with forming or fabricating a wafer. However, the claimed subject matter is not so limited. The work piece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of claimed subject matter may include various articles such as printed circuit boards, or the fabrication of printed circuit boards, and the like.
Unless the context of this disclosure clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also generally include the plural or singular number respectively. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The term “embodiment” refers to implementations of techniques and methods described herein, as well as to physical objects that embody the structures and/or incorporate the techniques and/or methods described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202031027674 | Jun 2020 | IN | national |
A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2021/038457 | 6/22/2021 | WO |
