Patent Application
20060214679
1. Technical Field
The present invention relates to an interface for monitoring test signals provided to and from a probe card used for contacting and testing devices under test (DUTs) on a wafer.
2. Related Art
Test systems for testing DUTs on wafers during manufacture typically include an Automatic Test Equipment (ATE) tester or test system controller, and a probe card for connecting channels from the test system controller to DUTs on a wafer. A conventional test system is shown in
The ATE test system controller is a significant cost factor in a test system, and includes equipment to generate test signals on channels to provide to contact pads on multiple DUTs. The test system controller further receives and analyzes responses from the DUTs. Test results for all DUTs on a wafer are displayed by the test system controller on a user interface.
The probe cards that carry signals between the test system controller and DUTs on a wafer are much less expensive than the test system controllers. Different probe cards are, thus, used to connect a single test system controller to many possible DUT pin configurations on a wafer to eliminate the expense of purchasing a new test system controller for each configuration of DUTs on a wafer. Probe cards, serving as an interface between a test system controller and a wafer, are typically much less expensive than a test system controller, and typically replaced after a much shorter lifecycle than the test system controller due to wear of probes on the probe card.
Wafer test systems are typically used in one instance to test memory components, such as dynamic random access memory (DRAM) on a wafer during manufacture before the wafer is diced up into individual chips. For DRAM redundant rows of memory devices can be created, and the test system is used to identify rows with failed memory cells or locations. In one manufacturing method, rows of DUTs with faulty cells are disconnected before manufacture is completed. In another process, after testing, additional manufacturing steps may be performed to correct defects in particular cells before manufacturing is completed.
In the test system, test signals are generated by the test system controller 4 and transmitted through the communication cable 6, test head 8, probe card 18, probes 16 and ultimately to DUTs on the wafer 14. Test data provided from the test system controller 4 is divided into the individual test channels provided through the cable 6 and separated in the test head 8 so that each channel is carried to a separate one of the probes 16. The channels from the test head 8 are linked by connectors 24 to the probe card 18. The probe card 18 then links each channel to a separate one of the probes 16. Test results are then provided from DUTs on the wafer 14 back through the probe card 18 to the test head 8 for transmission back to the test system controller 4. Once testing is complete, the wafer is diced up to separate the DUTs.
Mechanical support for the electrical components is provided by a back plate 50, bracket (Probe Head Bracket) 52, frame (Probe Head Locating Frame) 54, leaf springs 56, and leveling pins 62. The back plate 50 is provided on one side of the PCB 30, while the bracket 52 is provided on the other side and attached by screws 59. The leaf springs 56 are attached by screws 58 to the bracket 52. The leaf springs 56 extend to movably hold the frame 54 within the interior walls of the bracket 52. The frame 54 then includes horizontal extensions 60 for supporting the space transformer 34 within its interior walls. The frame 54 surrounds the probe head and maintains a close tolerance to the bracket 52 such that lateral motion is limited.
Leveling pins 62 complete the mechanical support for the electrical elements and provide for leveling of the space transformer 34. The leveling pins 62 are adjusted so that brass spheres 66 provide a point contact with the space transformer 34. The spheres 66 contact outside the periphery of the LGA of the space transformer 34 to maintain isolation from electrical components. Leveling of the substrate is accomplished by precise adjustment of these spheres through the use of advancing screws, or leveling pins 62. The leveling pins 62 are screwed through supports 65 in the back plate 50 and PCB 30. Motion of the leveling pin screws 62 is opposed by leaf springs 56 so that spheres 66 are kept in contact with the space transformer 34.
In some cases, manufacturers testing DUTs on a wafer desire to determine results from only one DUT, or less than all the DUTs being tested. In one instance, monitoring test results from one DUT is desirable to verify accuracy of the test results performed by the test system controller on all DUTs being tested. In another instance, tests from only one DUT may be desired to indicate repairs needed to one or more of the DUTs, since taking time to receive and process results from all DUTs connected to a test system may be unnecessary and time consuming. Accordingly, it is desirable to provide a system for testing a number of DUTs while providing an optional interface for providing test results from one or a limited number of the DUTs.
In accordance with the present invention, monitoring of test signals is provided between the test system controller and one or more DUTs during testing. Such monitoring enables confirmation of test results from at least one DUT. Such monitoring further provides a number of features including—(1) ensuring that the test system controller is functioning properly, (2) enabling a test operator to verify operation more rapidly rather than waiting for a compilation of data from the test system controller, and (3) enabling a test operator to monitor a particular DUT quickly which is posing problems or so that modifications can be made on the particular DUT and confirmed before similar modifications are made to the remaining DUTs on a wafer.
Monitoring of test signals is provided by including a diagnostic interface connection on the PCB of the probe card. The diagnostic interface includes a connector that contacts the channel lines provided to one or more of the particular DUTs. The diagnostic interface connection to the PCB of the probe card allows signals to be brought out from a convenient position to connect to a user interface such as a personal computer. To prevent signal distortion in test signals on the channel lines due to long lines of the diagnostic interface, in one embodiment buffers are provided on the PCB as part of the interface connector connecting to the channels.
The signals from the interface connector in one embodiment are further provided to an adapter pod for processing so that the test results can be directly displayed to a system user. The adapter pod can include a digital signal processor (DSP) connected through an AMD converter for receiving analog current and voltages provided to and from a DUT. The DSP then functions to provide a displayable list of the test voltages and currents from particular inputs and outputs of the one or more DUTs being monitored. In another embodiment, the interface pod receives digital signals provided to and from the DUTs at the DSP that bypass the A/D converter, and the DSP functions to provide data indicating the accuracy of the test results based on the digital signals received.
In another embodiment, the adapter pod serves to distribute test signals to a plurality of output connectors without processing by a DSP. The adapter pod output connectors in one embodiment distribute the same signals to a number of different display devices. In another embodiment, the output connectors are connected to divide up the signal lines from the input interface connector. For example, one adapter pod output connector can carry only input signals to the DUT, while another can carry only output signals from the DUT, while yet another can carry the power supply line signals.
Further details of the present invention are explained with the help of the attached drawings in which:
The diagnostic interface connector 70 is preferably a fine pitch impedance controlled socket that may be a pogo pin type connector, a ZIF connector, or other vertical interface connector depending on design requirements. The diagnostic interface connector 70 is shown connected to a flexible ribbon cable type connector 72. Although shown as a flexible ribbon cable type connector, the connector 72 can be one of a number of connection types, such as soldered wires or another more rigid type connector. The connector 72 can connect directly to a user interface, such as a personal computer, or it can be connected to one or more user interfaces through an adapter pod 74, as shown in
The adapter pod 74 can include different components, depending on the amount of processing of the test signals that is desired prior to providing test results to one or more user interfaces. In one embodiment the adapter pod 74 includes components that process the signals provided from the DUTs to provide test result data to a user interface device. The adapter pod 74 can further include components that distribute the signals received from the interface connector 70 to a plurality of connections 76, as shown, with or without the adapter pod 74 performing processing. The plurality of connections 76 can provide identical signals to multiple user interface devices, or can separate the signals into one or a number of categories such as DUT inputs, DUT outputs, and DUT power supply lines. Connections to a user interface device can be provided by the ribbon cable connector 78 shown in
Although shown provided as part of the connector 70, in one embodiment, the buffers 80 and capacitor 81 can be provided in a buffer card that is attached to the PCB 30. The buffer card can be formed as a separate layer of the PCB 30, or attached to the PCB 30 as a separate daughter card by connectors on the PCB 30. The buffers 80 and capacitors 81 supported on the buffer card then connect the channel lines of the PCB 30 to the separate diagnostic interface connector 70.
The lines from the interface connector 70 in
The DSP 88 can be programmed to recognize the test being performed based on the signals received, or alternatively can have a connection (not shown) to the test system controller 4 to enable the DSP 88 to determine the type of test and to process the test results. As an alternative to the DSP 88, another type processor can be used with programming controlled by software stored in an attached memory device. Test signals measured by the DSP 88 may result from parametric tests where leakage current or voltage is measured, requiring the AID converter 86 and analog measurement analysis to process test results from buffers 82. The test signals measured may alternatively include a digital signal from a DUT output, requiring the digital signals provided from buffers 84 to enable the DSP 88 to process test results. Test results from the DSP 88 are provided through connectors 76 and 78 to a user interface device where either display of the results or further manipulation of the test results may be performed.
Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many additional modifications will fall within the scope of the invention, as that scope is defined by the following claims.
