Patent Application
20250061935
In an embodiment, an interposer (or alternatively, a silicon bridge) interconnecting a first integrated circuit (e.g., CPU, controller, System on a Chip—SoC, etc.) and a second integrated circuit (e.g., DRAM, high-bandwidth memory stack—HBM, etc.) includes active circuitry. The “active” interposer converts high-speed signals into lower-speed, but more parallelized, signals for transmission across the active interposer. The parallelized signals may be buffered or amplified (a.k.a., re-driven) at intervals while crossing the active interposer.
In an embodiment, the high-speed to low-speed, and back, conversions may be performed by an appropriately configured and controlled multiplexer/demultiplexer (MUX/DEMUX) circuitry (a.k.a., serializer/deserializer-SERDES circuitry). The supply voltages for the SERDES circuitry and re-drivers may be different than the supply voltages for the interfaces with the first and second integrated circuit. One or more of the interconnected integrated circuits may supply, and/or calibrate the supply voltages for the SERDES and re-drive circuitry. Timing signals provided by one or more of the interconnected integrated circuits may also be calibrated using circuitry on the active interposer.
Controller 120 and memory device 130 may comprise integrated circuit type devices, such as those commonly referred to as “chips”. In an embodiment, memory device 130 may be, or comprise, a stacked die component comprising a stack of dynamic random access memory (DRAM) integrated circuit die co-packaged together and coupled to each other via wired bonds and/or through-silicon vias (TSVs). Examples of a stacked die component comprising DRAM integrated circuit dies include High Bandwidth Memory (HBM) type components.
A memory controller, such as controller 120, manages the flow of data going to and from memory devices. Functionality of a memory controller may be included on a single die with a microprocessor, or included as part of a more complex integrated circuit system as a block of a system on a chip (SOC). For example, a memory controller may be a northbridge chip, an application specific integrated circuit (ASIC) device, a load-reduction memory buffer, a graphics processor unit (GPU), a system-on-chip (SoC) or an integrated circuit device that includes many circuit blocks such as ones selected from graphics cores, processor cores, and MPEG encoder/decoders, etc.
In an embodiment, interposer 110 interconnects controller 120 and memory device 130. In particular, interposer 110 functions to communicate high-speed signals (e.g., data-DQ, and command/address-CA, signals) transmitted or received via channel interface 122 of controller 120 (and thus also via channel interface 112 of interposer 110) and channel interface 132 of memory device 130 (and thus also via channel interface 113 of interposer 110) between channel interface 122 of controller 120 and channel interface 132 of memory device 130. Interposer 110 converts high-speed signals received via channel interface 112 and channel interface 113 (i.e., received from controller 120 and memory device 130, respectively) into multiple lower-speed parallel signals. These lower-speed parallel signals may be re-driven by a series of buffers (e.g., buffer circuitry 114a-114b) while being propagated across interposer 110. After being propagated to near their respective destination interface 112-113, the lower-speed parallel signals are converted back to higher-speed signals for transmission via their respective destination interface 112-113 to controller 120 and memory device 130, respectively.
Conversion of the signals between high-speed to lower-speed may be performed by MUX/DEMUX functions (e.g., MUX/DEMUX circuitry 115a-115b) that are synchronized by strobe signals (e.g., read data strobes—RDQS, write data strobes—WDQS) provided by controller 120 and/or memory device 130. These strobe signals are also propagated (and optionally buffered—e.g., by strobe buffers 116a-116b 177a-117b) across interposers 110 to synchronize the communication of data with controller 120 and memory device 130.
In an embodiment, the MUX/DEMUX function (e.g., MUX/DEMUX circuitry 115a-115b) and the re-drive buffers (e.g., buffer circuitry 114a-114b) operate using different power supply voltages (e.g., VDDQ and VDD). These different power supply voltages may be calibrated separately (or independently) of each other in order to meet power consumption and/or delay targets or optimizations. In particular, as the VDD voltage level is increased, the delay through buffer circuitry 114a-114b, strobe buffers 116a-116b, and/or strobe buffers 117a-117b is decreased while the power consumed by buffer circuitry 114a-114b, strobe buffers 116a-116b, and/or strobe buffers 117a-117b is increased. Thus, controller 120 may set the voltage level of VDD to tradeoff power consumption by interposer 110 versus delay through interposer 110 in order to meet desired delay and power consumption goals for a given application/use case.
Strobe signals may also be calibrated by controller 120, memory device 130, and/or interposer 110. In an embodiment, one or more strobe signals may be calibrated by interposer 110 in response to commands or signals from controller 120 (e.g., under the control of control circuitry 121).
In
While the lower-speed signals are propagated from/to MUX/DEMUX circuitry 115a (shown as CIDQ[ ] at MUX/DEMUX circuitry 115a) to/from MUX/DEMUX circuitry 115b (shown as memory-side intermediate DQ signals—MIDQ[ ] at MUX/DEMUX circuitry 115b), buffer circuitry 114a-114b may re-drive the propagating lower-speed signals. Buffer circuitry 114a-114b may re-drive the propagating lower-speed signals in order to improve signal integrity, decrease delay and/or reduce overall power consumption (when compared to not re-driving the lower-speed signals).
The lower-speed signals (MIDQ[ ]) are also coupled with MUX/DEMUX circuitry 115b. MUX/DEMUX circuitry 115b converts lower-speed parallel signals (MIDQ[ ]) to/from high-speed data signals (memory-side DQ signals—MDQ[ ]) that are operatively coupled to channel interface 113 (and thus coupled with memory device 130). For example, MUX/DEMUX circuitry 115b may convert each higher-speed data signal from/to N number of lower-speed parallel signals (i.e., a serialization/deserialization factor of N) that are communicated with memory device 130 via interface 113.
In
First strobe signals (shown as controller-side write data strobe signals—CWDQS[ ] at interface 112) are transmitted by controller 120 via interface 122 and interface 112 to synchronize the high-speed signals transmitted by controller 120 via interposer 110 to memory device 130. Controller 120 adjusts the timing of the first (one or more) strobe signals in order to ensure correct serialization (e.g., by MUX/DEMUX circuitry 115a), correct deserialization (e.g., by MUX/DEMUX circuitry 115b), and correct communication with memory device 130 (e.g., via interface 113 and interface 132). Variable delay 119 (if present), is coupled between strobe buffer 116b and channel interface 113 to change the timing of the MWDQS[ ] strobe signals received by memory device 130. Controller 120 may adjust variable delay 119 to compensate for a strobe signal tree inside memory device 130.
The first strobe signals are propagated from interface 112 to interface 113 by interposer 110. While the first strobe signals are being propagated, strobe buffers 116a-116b may re-drive the propagating first strobe signals (shown as memory-side write data strobe signals—MWDQS[ ] at interface 113). Strobe buffers 116a-116b may re-drive the propagating lower-speed signals in order to improve signal integrity, match, or compensate for, the data signal (e.g., CDQ[ ], MDQ[ ]) propagation delays across interposer 110, decrease delay and/or reduce overall power consumption (when compared to not buffering the first strobe signals).
Second strobe signals (shown as memory-side read data strobe signals—MRDQS[ ]) are transmitted by memory device 130 via interface 132 and interface 113 to synchronize the high-speed signals transmitted by memory device 130 via interposer 110 to controller 120. Memory device 130 (e.g., under the control of, or in response to a command from controller 120) may adjust the timing of the second (one or more) strobe signals in order to ensure correct deserialization (e.g., by MUX/DEMUX circuitry 115b), correct serialization (e.g., by MUX/DEMUX circuitry 115a), and correct communication with controller 120 (e.g., via interface 112 and interface 122). The second strobe signals are propagated from interface 113 to interface 112 by interposer 110. While the second strobe signals are being propagated, strobe buffers 117a-117b may re-drive the propagating second strobe signals (shown as controller-side read data strobe signals—CRDQS[ ] at interface 112). Strobe buffers 117a-117b may re-drive the propagating lower-speed signals in order to improve signal integrity, match, or compensate for, the data signal (e.g., CDQ[ ], MDQ[ ]) propagation delays across interposer 110, decrease delay and/or reduce overall power consumption (when compared to not buffering the second strobe signals).
In an embodiment, the direction (i.e., from MUX/DEMUX circuitry 115a to MUX/DEMUX circuitry 115b, or from MUX/DEMUX circuitry 115b to MUX/DEMUX circuitry 115a) that buffer circuitry 114a-114b is controlled to propagate the lower-speed signals is controlled by a read/write (RW) signal from controller 120. In another embodiment (not shown in
The read/write signal (or derived read/write signal) also controls which of the first strobe signals and the second strobe signals are to synchronize the serialization/deserialization functions performed by MUX/DEMUX circuitry 115a and MUX/DEMUX circuitry 115b). In particular, when the read/write signal is indicating a write from controller 120 to memory device 130, strobe selector 118a selects the first strobe signals (i.e., controller-side WDQS—CWDQS[ ]) to synchronize the deserialization performed by MUX/DEMUX circuitry 115a. Also when the read/write signal is indicating a write from controller 120 to memory device 130, strobe selector 118b selects the propagated first strobe signals (i.e., memory-side WDQS—MWDQS[ ]) to synchronize the reconstruction (a.k.a., re-serialization or serialization) of the high-speed signals performed by MUX/DEMUX circuitry 115b.
When the read/write signal is indicating a read from memory device 130 by controller 120, strobe selector 118b selects the second strobe signals (e.g., memory-side RDQS—MRDQS[ ]) transmitted by memory device 130 to synchronize the deserialization performed by MUX/DEMUX circuitry 115b. Also when the read/write signal is indicating a read from memory device 130 by controller 120, strobe selector 118a selects the propagated second strobe signals (e.g., controller-side RDQS—CRDQS[ ]) to synchronize the reconstruction (a.k.a., re-serialization or serialization) of the high-speed signals performed by MUX/DEMUX circuitry 115a.
It should also be understood that command/address (CA) signals may be propagated (and buffered, etc.) between controller 120 and memory device 130 by interposer 110. However, for the sake of clarity and brevity, the CA signals associated with interface 112 and interface 113 have been omitted from
Decoder 260 receives data strobe signals and produces a plurality (e.g., 4) “one-hot” signals from the data strobe signals. In other words, decoder 260 decodes overlapping data strobe signals that have a plurality unique states (e.g., 00, 01, etc.) into a corresponding plurality of signals that are each only active during a corresponding one of the unique states.
By the data channel, the data signals are deserialized into deserialized data signals that are communicated via parallel data interconnections of the data channel that are operated at a lower data rate than the data signals (404). For example, MUX/DEMUX circuitry 115a may deserialize high-speed data signals CDQ[ ] from interface 112 into a plurality of lower-speed data signals CIDQ[ ] that are operated (e.g., propagated to MUX/DEMUX circuitry 115b) at a lower data rate (e.g., a data rate that is 1/N times slower than CDQ[ ], where N is the deserialization factor—e.g., 4, 8, etc.). In another example, MUX/DEMUX circuitry 115b may deserialize high-speed data signals MDQ[ ] from interface 113 into a plurality of lower-speed data signals MIDQ[ ] that are operated (e.g., propagated to MUX/DEMUX circuitry 115a) at a lower data rate (e.g., a data rate that is 1/N times slower than MDQ[ ], where N is the deserialization factor—e.g., 4, 8, etc.).
By the data channel, the deserialized data signals are serialized into reconstructions of the data signals (406). For example, after lower-speed CIDQ[ ] signal are propagated to MUX/DEMUX circuitry 115b (becoming MIDQ[ ] signals), MUX/DEMUX circuitry 115b may serialize the MIDQ[ ] signals to reconstruct the original high-speed CDQ[ ] signals as MDQ[ ] signals. In another example, after lower-speed MIDQ[ ] signal are propagated to MUX/DEMUX circuitry 115a (becoming CIDQ[ ] signals), MUX/DEMUX circuitry 115a may serialize the CIDQ[ ] signals to reconstruct the original high-speed MDQ[ ] signals as CDQ[ ] signals.
The reconstructions of the data signals are communicated with at least one integrated circuit at the data rate of the data signals (408). For example, the reconstructed high-speed data signals (MDQ) may be communicated with memory device 130 via interface 113 and interface 132. In another example, the reconstructed high-speed data signals (CDQ) may be communicated with controller 120 via interface 112 and interface 122.
At least one strobe signal is calibrated to produce correct deserializations by the data channel (410). For example, during a calibration period, controller 120 may transmit a calibration pattern via MDQ[ ] (e.g., a toggling pattern). Memory device 130 may report back to controller 120 one or more error status indicators. Alternatively, memory device 130 may transmit the calibration pattern as received by memory device 130 back to controller 120, where controller 120 may then determine whether there were errors. Based on the error and/or loop-back information received by controller 120 from memory device 130, controller 120 may adjust the timing of one or more strobe signals transmitted by controller 120 (e.g., CWDQS[ ]), and/or cause (or command) interposer 110 to adjust the timing of one or more strobe signals and/or control circuitry 111 to adjust the timing of CWDQS[ ] that is provided to MUX/DEMUX circuitry 115a). In another example, based on the error and/or loop-back information received by controller 120 from memory device 130, controller 120 may instruct memory device 130 to adjust the timing of one or more strobe signals transmitted by memory device 130 (e.g., MRDQS[ ]), and/or cause (or command) interposer 110 to adjust the timing of one or more strobe signals that are provided to MUX/DEMUX circuitry 115b.
At least one strobe signal is calibrated to produce correct reconstructions of the data signals by the data channel (412). For example, during a calibration period, controller 120 may transmit a calibration pattern via MDQ[ ] (e.g., a toggling pattern). Memory device 130 may report back to controller 120 one or more error status indicators. Alternatively, memory device 130 may transmit the calibration pattern as received by memory device 130 back to controller 120, where controller 120 may then determine whether there were errors. Based on the error and/or loop-back information received by controller 120 from memory device 130, controller 120 may adjust the timing of one or more strobe signals (e.g., CWDQS[ ]), and/or cause (or command) interposer 110 to adjust the timing of one or more strobe signals (e.g., using control circuitry 111 to adjust the timing of MWDQS[ ] that is provided to MUX/DEMUX circuitry 115b). In another example, based on the error and/or loop-back information received by controller 120 from memory device 130, controller 120 may instruct memory device 130 to adjust the timing of one or more strobe signals transmitted by memory device 130 (e.g., CRDQS[ ]), and/or cause (or command) interposer 110 to adjust the timing of one or more strobe signals that are provided to MUX/DEMUX circuitry 115a). In another example, based on the error and/or loop-back information received by controller 120 from memory device 130, controller 120 may instruct and/or cause interposer 110 to adjust, independent of MUX/DEMUX 115a-115b and buffer circuitry 114a-114b timing, the timing of one or more strobe signals (e.g., MWDQS[ ]) that are provided to memory device 130 in order to compensate for variations inside of memory device 130 (e.g., data strobe fanout delays that alter the timing relationship between MWDQS[ ] and MDQ[ ]).
Bidirectional data signals are communicated with the first integrated circuit synchronized using strobe signals received from the first integrated circuit (504). For example, controller 120 may communicate high-speed bidirectional data signals (e.g., CDQ[ ]) with interposer 110. Each data signal is deserialized into a plurality of deserialized data signals (506). For example, MUX/DEMUX circuitry 115a may deserialize each high-speed data signals CDQ[ ] from interface 112 into a respective plurality of lower-speed data signals CIDQ[ ] that are each operated at a lower data rate than CDQ[ ] is operated.
To serialization circuitry, each of the deserialized signals are communicated to serialization circuitry via parallel data couplings that are each operated at a lower data rate than the data signals (508). For example, MUX/DEMUX circuitry 115a and buffer circuitry 114a-114b may propagate CIDQ[ ] signals, which are each at a lower data rate than CDQ[ ], to MUX/DEMUX circuitry 115b (where they are received as MIDQ[ ] signals). Each of the deserialized data signals are serialized into respective reconstructions of the data signals (510). For example, MUX/DEMUX circuitry 115b may serialize the MIDQ[ ] signals to reconstruct the original high-speed CDQ[ ] signals as MDQ[ ] signals. The respective reconstructions of the data signals are communicated with a second integrated circuit (512). For example, the reconstructed high-speed data signals (MDQ) may be communicated with memory device 130 via interface 113 and interface 132.
Based on first information from the first integrated circuit, at leas one of the strobe signals is calibrated to produce correct deserializations of the data signals and correct reconstructions of the data signals (514). For example, during a calibration period, controller 120 may transmit a calibration pattern via CDQ[ ] (e.g., a toggling pattern). Memory device 130 may report back to controller 120 one or more error status indicators. Alternatively, memory device 130 may transmit the calibration pattern as received by memory device 130 back to controller 120, where controller 120 may then determine whether there were errors. Based on the error and/or loop-back information received by controller 120 from memory device 130, controller 120 may adjust the timing of one or more strobe signals transmitted by controller 120 (e.g., CWDQS[ ]), and/or cause (or command) interposer 110 to adjust the timing of one or more strobe signals (e.g., using control circuitry 111 to adjust the timing of CWDQS[ ] that is provided to MUX/DEMUX circuitry 115a).
The first power supply voltage is adjusted (516). For example, based on error and/or loop-back information received by controller 120 from memory device 130, controller 120 may adjust and/or cause (or command) interposer 110 to adjust the first power supply voltage (e.g., VDD) that powers the circuits in VDD domain 140.
Strobe signals are transmitted to synchronize communication of bidirectional data signals with the first integrated circuit (604). For example, controller 120 may transmit strobe signals WDQS[ ] to synchronize communication, with interposer 110 via interface 122 and interface 112, of high-speed bidirectional data signals (e.g., CDQ[ ]). Based on first information from the first integrated circuit, calibrate at least one of the strobe signals to produce correct deserializations of the data signals by the first integrated circuit and correct reconstructions of the data signals by the first integrated circuit (606). For example, during a calibration period, controller 120 may transmit a calibration pattern via CDQ[ ] (e.g., a toggling pattern). Memory device 130 may report back to controller 120 one or more error status indicators. Alternatively, memory device 130 may transmit the calibration pattern as received by memory device 130 back to controller 120 via interposer 110, where controller 120 may then determine whether there were errors. Based on the error and/or loop-back information received by controller 120 from memory device 130 via interposer 110, controller 120 may adjust the timing of one or more strobe signals transmitted by controller 120 (e.g., CWDQS[ ]), and/or cause (or command) interposer 110 to adjust the timing of one or more strobe signals to adjust the timing of CWDQS[ ] that is provided to MUX/DEMUX circuitry 115a and adjust the timing of MWDQS[ ] provided to MUX/DEMUX circuitry 115b. In another example, based on the error and/or loop-back information received by controller 120 from memory device 130 via interposer 110, controller 120 may instruct memory device 130 to adjust the timing of one or more strobe signals transmitted by memory device 130 (e.g., MRDQS[ ]), and/or cause (or command) interposer 110 to adjust the timing of one or more strobe signals to adjust the timing of MRDQS[ ] that is provided to MUX/DEMUX circuitry 115b and adjust the timing of CRDQS[ ] provided to MUX/DEMUX circuitry 115a.
The first power supply voltage is adjusted to meet a power consumption and delay goal for the first integrated circuit (608). For example, controller 120 may adjust and/or cause (or command) interposer 110 to adjust the first power supply voltage (e.g., VDD) that powers the circuits in VDD domain 140 in order to meet a power consumption by, and delay through, circuits in VDD domain 140. Optionally, step 606 and 608 are iterated to meet timing and power target.
From the first integrated circuit and via the active interposer integrated circuit, first error information about the first integrated circuit's reception of the first calibration pattern is received (704). For example, memory device 130 may report, via interposer 110, one or more reception error status indicators to controller 120 Alternatively, memory device 130 may transmit the calibration pattern, as received by memory device 130, back to controller 120 and via interposer 110. Based on the first error information, the active interposer is instructed to adjust at least one of a phase and duty cycle of the data strobes (706). For example, based on the error and/or loop-back information received by controller 120 from memory device 130 via interposer 110, controller 120 may instruct (or command) interposer 110 to adjust the timing of CWDQS[ ] that is provided to MUX/DEMUX circuitry 115a (and MUX/DEMUX circuitry 115b as MWDQS[ ]) using control circuitry 111.
To a first integrated circuit and via an active interposer integrated circuit, a first calibration pattern synchronized by data strobes is transmitted (804). For example, during a calibration period, controller 120 may transmit, to memory device 130 and via interposer 110, a calibration pattern that is synchronized by data strobes CWDQS[ ]. From the first integrated circuit and via the active interposer integrated circuit, first error information about the first integrated circuit's reception of the first calibration pattern is received (806). For example, memory device 130 may report, via interposer 110, one or more reception error status indicators to controller 120 Alternatively, memory device 130 may transmit the calibration pattern, as received by memory device 130, back to controller 120 and via interposer 110.
Based on the first error information, at least one of the first power supply voltage and the second power supply voltage are adjusted (808). For example, based on the error and/or loop-back information received by controller 120 from memory device 130 via interposer 110, controller 120 may adjust VDD and/or VDDQ to meet goals, thresholds, and or optimizations, for power consumed by, and/or delay through, interposer 110.
The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of system 100, MUX/DEMUX circuitry 200, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.
Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3½ inch floppy media, CDs, DVDs, and so on.
Processors 902 execute instructions of one or more processes 912 stored in a memory 904 to process and/or generate circuit component 920 responsive to user inputs 914 and parameters 916. Processes 912 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and/or verify electronic circuitry and/or generate photomasks for electronic circuitry. Representation 920 includes data that describes all or portions of system 100, MUX/DEMUX circuitry 200, and their components, as shown in the Figures.
Representation 920 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 920 may be stored on storage media or communicated by carrier waves.
Data formats in which representation 920 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email
User inputs 914 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 916 may include specifications and/or characteristics that are input to help define representation 920. For example, parameters 916 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and/or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).
Memory 904 includes any suitable type, number, and/or configuration of non-transitory computer-readable storage media that stores processes 912, user inputs 914, parameters 916, and circuit component 920.
Communications devices 906 include any suitable type, number, and/or configuration of wired and/or wireless devices that transmit information from processing system 900 to another processing or storage system (not shown) and/or receive information from another processing or storage system (not shown). For example, communications devices 906 may transmit circuit component 920 to another system. Communications devices 906 may receive processes 912, user inputs 914, parameters 916, and/or circuit component 920 and cause processes 912, user inputs 914, parameters 916, and/or circuit component 920 to be stored in memory 904.
Implementations discussed herein include, but are not limited to, the following examples:
Example 1: An integrated circuit, comprising: a data interface to communicate a plurality of data signals with at least one integrated circuit via a data channel and synchronized using strobe signals, each respective data signal of the plurality of data signals to be deserialized, by the data channel, into a plurality of deserialized data signals communicated via parallel data interconnections that are each operated at a lower data rate than the respective data signal of the plurality of data signals, the plurality of deserialized data signals associated with each respective data signal of the plurality of data signals to be serialized, by the data channel, into a reconstruction of the respective data signal of the plurality of data signals and communicated to the at least one integrated circuit; strobe calibration circuitry to calibrate at least one of the strobe signals to produce correct deserializations, by the data channel, of the plurality of data signals, and to produce, by the data channel, correct reconstructions of the plurality of data signals; and circuitry to provide at least one supply voltage to be used by the data channel.
Example 2: The integrated circuit of example 1, wherein the data channel is to receive, from the integrated circuit, a first power supply voltage and a second power supply voltage.
Example 3: The integrated circuit of example 2, wherein the first power supply voltage is used by data channel circuitry that communicates deserialized versions of the plurality of data signals via the parallel data interconnections.
Example 4: The integrated circuit of example 3, further comprising: supply voltage calibration circuitry to adjust the first power supply voltage to tradeoff power consumption by the data channel and delay through the data channel.
Example 5: The integrated circuit of example 2, wherein the second power supply voltage is used by data channel circuitry that performs deserialization and data channel circuitry that performs serialization.
Example 6: The integrated circuit of example 2, wherein the first power supply voltage is used by data channel circuitry that communicates deserialized versions of the plurality of data signals via the parallel data interconnections, and wherein the second power supply voltage is used by data channel circuitry that performs deserialization and data channel circuitry that performs serialization.
Example 7: The integrated circuit of example 6, wherein the first power supply voltage and the second power supply voltage are independent of a third power supply voltage used by the data interface.
Example 8: The integrated circuit of example 1, wherein the integrated circuit is a controller and a first one the at least one integrated circuit is a memory device.
Example 9: An integrated circuit, comprising: a first data interface to communicate a plurality of bidirectional data signals with a first integrated circuit synchronized using strobe signals received from the first integrated circuit; deserialization circuitry to deserialize each respective data signal of the plurality of bidirectional data signals into a plurality of deserialized data signals to be communicated via parallel data interconnections of the integrated circuit that are each operated at a lower data rate than the respective data signal of the plurality of bidirectional data signals; serialization circuitry to serialize each of the plurality of deserialized data signals into a respective reconstruction of the respective data signal of the plurality of bidirectional data signals; a second data interface to communicate, with a second integrated circuit, respective reconstructions of the respective data signals of the plurality of bidirectional data signals; strobe calibration circuitry to, based on first information received from the first integrated circuit, calibrate at least one of the strobe signals to produce correct deserializations of the plurality of bidirectional data signals, and to produce correct reconstructions of the plurality of bidirectional data signals; and circuitry to receive, from the first integrated circuit, a first power supply voltage and a second power supply voltage.
Example 10: The integrated circuit of example 9, wherein the first power supply voltage is used by circuitry that communicates deserialized versions of the plurality of bidirectional data signals via the parallel data interconnections.
Example 11: The integrated circuit of example 10, further comprising: supply voltage calibration circuitry to adjust the first power supply voltage to tradeoff power consumption by the integrated circuit and delay through the integrated circuit.
Example 12: The integrated circuit of example 10, wherein the second power supply voltage is used by the deserialization circuitry and the serialization circuitry.
Example 13: The integrated circuit of example 12, wherein the first power supply voltage and the second power supply voltage are independent of a third power supply voltage used by the first data interface and the second data interface.
Example 14: The integrated circuit of example 9, wherein the first integrated circuit is a controller and the second integrated circuit is a memory device.
Example 15: An integrated circuit, comprising: a data interface to communicate a plurality of bidirectional data signals with another integrated circuit via a data channel integrated circuit, the communication of the plurality of bidirectional data signals via the data interface to by synchronized by strobe signals, the data channel integrated circuit to deserialize, using deserialization circuitry, each respective data signal of the plurality of bidirectional data signals into a plurality of deserialized data signals, the data channel integrated circuit to communicate, via parallel data interconnections that are each operated at a lower data rate than the respective data signal of the plurality of bidirectional data signals, the plurality of deserialized data signals to serialization circuitry, the serialization circuitry to reconstruct each of the respective data signals of the plurality of bidirectional data signals and communicate reconstructed versions of each of the respective data signals of the plurality of bidirectional data signals to the another integrated circuit; strobe calibration circuitry to calibrate at least one of the strobe signals to produce correct deserializations by the deserialization circuitry and to produce correct reconstructed versions of the plurality of bidirectional data signals by the serialization circuitry; and circuitry to provide at least one supply voltage to be used by data channel integrated circuit.
Example 16: The integrated circuit of example 15, wherein the data channel integrated circuit is to receive, from the integrated circuit, a first power supply voltage and a second power supply voltage.
Example 17: The integrated circuit of example 16, wherein the first power supply voltage is used by the data channel integrated circuit to power circuitry that communicates deserialized versions of the plurality of bidirectional data signals via the parallel data interconnections.
Example 18: The integrated circuit of example 17, further comprising:
Example 19: The integrated circuit of example 16, wherein the second power supply voltage is used by the data channel integrated circuit to power the deserialization circuitry and the serialization circuitry.
Example 20: The integrated circuit of example 15, wherein the integrated circuit is a controller and the another integrated circuit is a memory device.
The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.
| Number | Date | Country | |
|---|---|---|---|
| 63533093 | Aug 2023 | US |
