Adjustable resistor embedded in multi-layered substrate and method for forming the same

Abstract

An adjustable resistor embedded in a multi-layered substrate and method for forming the same. The adjustable resistor comprises: a planar resistor, having a plurality of terminals; and a plurality of connecting lines connected to the planar resistor, each of the connecting lines being drawn from each of the terminals of the planar resistor so as to form a resistor network, wherein the connecting lines are selectively broken by a process for drilling the substrate to form a number of combinations of opened connecting lines such that the resistance value of the adjustable resistor is varied and thus the resistance value of the adjustable resistor can be precisely adjusted.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, spirits and advantages of the preferred embodiments of the present invention will be readily understood by the accompanying drawings and detailed descriptions, wherein:

FIG. 1 is a schematic diagram showing a conventional surface coated resistor;

FIG. 2 is a schematic diagram showing an adjustable resistor embedded in a multi-layered substrate according to the preferred embodiment of the present invention;

FIG. 3 is an equivalent circuit diagram showing an adjustable resistor embedded in a multi-layered substrate according to the preferred embodiment of the present invention;

FIG. 4 is a table showing the resistance value of an adjustable resistor embedded in a multi-layered substrate according to the preferred embodiment of the present invention;

FIG. 5 is a graph showing the resistance variance of an adjustable resistor embedded in a multi-layered substrate according to the preferred embodiment of the present invention;

FIG. 6 is a schematic diagram showing an adjustable resistor embedded in a multi-layered substrate according to another preferred embodiment of the present invention;

FIG. 7 is a schematic diagram showing an adjustable resistor embedded in a multi-layered substrate according to still another preferred embodiment of the present invention.

Claims

1. An adjustable resistor embedded in a multi-layered substrate, the adjustable resistor being formed in one layer in the multi-layered substrate, the adjustable resistor comprising: a planar resistor with a plurality of terminals; anda plurality of connecting lines connected to the planar resistor, each of the connecting lines being drawn from each of the terminals of the planar resistor so as to form a resistor network,wherein the connecting lines are selectively broken by a process for drilling the substrate to form a number of combinations of opened connecting lines such that the resistance value of the adjustable resistor is precisely adjusted.

2. The adjustable resistor embedded in a multi-layered substrate as recited in claim 1, wherein the plurality of terminals are arbitrarily positioned.

3. The adjustable resistor embedded in a multi-layered substrate as recited in claim 1, wherein the multi-layered substrate is a printed circuit board (PCB), a ceramic substrate or an integrated circuit (IC) substrate.

4. A method for forming an adjustable resistor embedded in a multi-layered substrate, comprising steps of: forming a resistor network in one layer in the multi-layered substrate, the resistor network comprising a planar resistor with a plurality of terminals and a plurality of connecting lines connected to the planar resistor, each of the connecting lines being drawn from each of the terminals of the planar resistor; andselectively breaking the connecting lines by a process for drilling the substrate to form a number of combinations of opened connecting lines such that the resistance value of the adjustable resistor is precisely adjusted.

5. The method for forming an adjustable resistor embedded in a multi-layered substrate as recited in claim 4, wherein the plurality of terminals are arbitrarily positioned.

6. The method for forming an adjustable resistor embedded in a multi-layered substrate as recited in claim 4, wherein the multi-layered substrate is a printed circuit board (PCB), a ceramic substrate or an integrated circuit (IC) substrate.