Claims
- 1. A method for the fabrication of a semiconductor memory device having a floating gate, a sense transistor, an electron injector and a hole injector, comprising the steps of:
- a) forming a p- region in an n-type semiconductor substrate;
- b) then forming at least three p+ regions in said substrate, one of which is contiguous with said p- region, and two others of which form the source and drain at said sense transistor;
- c) then forming an n+ region in said substrate, also contiguous with said p- region;
- d) then implanting an n-type region in said substrate which overlaps a portion of said n+ region and a portion of said source or said drain, said implanted region having a dopant concentration between 5 .times. 10.sup.16 and 2 .times. 10.sup.17 cm.sup.-3 ;
- e) then forming said floating gate with selected portions spaced narrowly from (1) the channel region between said source and drain, (2) the p+n+ junction formed by said implanted region, and (3) the n+p- junction formed by said p- region and contiguous n+ region; whereby the implanted n+ region together with its overlapped p+ region forms the electron injector junction, said p- region together with its contiguous n+ region forms the hole injector region.
- 2. A method as in claim 1 wherein said implantation step comprises a dose of 1.0 .times. 10.sup.13 cm.sup.-2 phosphorus atoms, accelerated to an energy of 100 Kev.
- 3. A method as in claim 1 wherein the distance between said regions overlapped by the implantation step is about 0.5 mil.
Parent Case Info
This is a division, of application Ser. No. 644,983, filed Dec. 29, 1973, now is Pat. No. 4,035,820.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
3881180 |
Gosney |
Apr 1975 |
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Divisions (1)
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Number |
Date |
Country |
Parent |
644983 |
Dec 1975 |
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