This application claims the benefit of priority to Patent Application No. 202011131448.9, filed in China on Oct. 21, 2020; the entirety of which is incorporated herein by reference for all purposes.
The disclosure generally relates to vector computing and, more particularly, to apparatuses and methods for configuring cooperative warps in a vector computing system.
A vector computer is a computer for executing dedicated vector instructions to increase the speed of vector processing. The vector computer can process the data calculation of multiple warps at the same time. The vector computer is much faster than a scalar computer in terms of processing the data of warps. However, it might conflict when multiple warps access to general-purpose register (GPR) files. Therefore, the present invention proposes apparatuses and methods for configuring cooperative warps in a vector computing system to address or reduce the aforementioned problems.
The disclosure relates to an embodiment of an apparatus for configuring cooperative warps in a vector computing system. The apparatus includes general-purpose registers (GPRs); an arithmetic logical unit (ALU); and a warp instruction scheduler. The warp instruction scheduler is arranged operably to: allow each of a plurality of warps to access to data of a whole or a designated portion of the GPRs through the ALU in accordance with a configuration by a software when being executed; and complete calculations of each warp through the ALU.
The disclosure further relates to another embodiment of an apparatus for configuring cooperative warps in a vector computing system. The apparatus includes an ALU; and a warp instruction scheduler. The warp instruction scheduler is arranged operably to: allow each of a plurality of warps to have a portion of relatively independent instructions in a kernel in accordance with warp dispatch instructions in the kernel, thereby enabling the ALU to execute the warps independently and in parallel.
The disclosure relates to an embodiment of a method for configuring cooperative warps in a vector computing system. The method includes steps of: allowing each of a plurality of warps to access to data of a whole or a designated portion of GPRs through an ALU in accordance with a configuration by a software when being executed; and completing calculations of each warp through the ALU.
Both the foregoing general description and the following detailed description are examples and explanatory only, and are not restrictive of the invention as claimed.
Reference is made in detail to embodiments of the invention, which are illustrated in the accompanying drawings. The same reference numbers may be used throughout the drawings to refer to the same or like parts, components, or operations.
The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words described the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent.” etc.)
Refer to
Refer to
In some implementations, the GPRs 230 may be physically or logically divided into multiple blocks of equal length, and the storage space of each block is configured to be accessed by only one warp. The storage space between different blocks does not overlap, which is used to avoid access conflicts between different warps. Refer to
In order to eliminate or alleviate the aforementioned problems, from one aspect, the warp instruction scheduler 220 allows each of the warps to access to data of the whole or the designated portion of GPRs 230 through the ALU 210 in accordance with the configurations by the software during execution, and completes the calculations for each warp through the ALU 210. By allowing the software to dynamically adjust and configure the GPRs to be accessed by components for different warps, it would widely adapted to applications, such as big data, artificial intelligence, or other computations.
From another aspect, embodiments of the present invention provide an environment that allows software to determine the instruction segments included in each warp. In some embodiments, instructions in a kernel are divided into segments, in which each instruction segment is independent from the others, and is executed with one warp. Exemplary pseudo code of a kernel is illustrated as follows:
Assume that each SM 100 runs at most eight warps, and each warp has a unique identifier (ID): The warp instruction scheduler 220 when fetching the aforementioned kernel instructions inspects the warp ID for the designated warp to jump to the instruction segment associated with this warp, and stores the jumped instruction segment in the instruction cache 240. Then, the warp instruction scheduler 220 obtains an instruction from the instruction cache 240 in accordance with the value of corresponding program counter, and sends the obtained instruction to the ALU 210 to complete the designated calculation. In this case, each warp could perform tasks independently, and all warps could be run at the same time, so that the pipeline in the ALU 210 would be as busy as possible to avoid bubbles. Instructions of each segment in the same kernel may be called relatively independent instructions. Although the above example is to add conditional judgment instructions to the kernel to achieve the instruction segmentation, those artisans may use other different instructions that can achieve the same or similar functions to complete the instruction segmentation in the kernel. In the kernel, those instructions used to achieve the instruction segmentation for warps are also referred to as warp dispatch instructions. In general, the warp instruction scheduler 240 allows each warp to have a portion of relatively independent instructions in accordance with the warp dispatch instructions in the kernel, so that the ALU 210 executes the warps independently and in parallel.
The barriers register 250 stores information to be used to synchronize executions between different warps, including the number of warps that need to wait for the completion of other warps, and the number of warps currently waiting to continue execution. In order to coordinate with the execution progress of different warps, the software sets the content of the barriers register 250 to record the number of warps that need to wait for the completion of other warps. A barrier instruction may be inserted into each instruction segment in the kernel in accordance with the system requirement. The warp instruction scheduler 220 when fetching the barrier instruction for a warp increase the number of warps currently waiting to continue execution by one, and puts this warp into the waiting state. Then, the warp instruction scheduler 220 examines the content of barriers register 250 to determine whether the number of warps currently waiting to continue execution is equal to or greater than the number of warps that need to wait for the completion of other warps. If so, the warp instruction scheduler 220 wakes up all waiting warps, so that these warps can continue to execute. Otherwise, the warp instruction scheduler 220 fetches the next warp instruction from the instruction cache 240.
Moreover, the realized segmentation as shown in
From another aspect, although one SM 100 has the capability of executing multiple warps, embodiments of the invention do not divide the GPRs 230 for different warps in advance. In detail, in order to adapt to different applications more widely, the SM 100 does not divide the GPRs 230 into multiple blocks of equal length for different warps, but provides an environment to allow the software to dynamically adjust and configure the GPRs 230 for different warps, so that the software would assign the whole or the designated portion of GPRs 230 to each warp in accordance with the application requirements.
In alternative embodiments, each SM 100 includes the resource-per-warp register 260 for storing information about a base position for each warp, and each base position points to a specific address of the GPRs 230. In order to allow different warps to access to non-overlapping storage space in the GPRs 230, the software dynamically modifies the content of resource-per-warp registers 260 to set the base position for each warp. For example, refer to
Dest_addr=Instr_i(Src_addr0,Src_addr1)
where Instr_i represents the operation code (OpCode) of the instruction assigned to the ith warp, Src_addr0 represents the 0th source address, Src_addr1 represents the 1st source address, and Dest_addr represents the destination address.
The warp instruction scheduler 220 modifies the aforementioned instruction to become:
Base #i+Dest_addr=Instr_i(Base #i+Src_addr0,Base #i+Src_addr1)
where Base #i represents the base position recorded in the resource-per-warp register 260 #i. That is, the warp instruction scheduler 220 adjusts the source addresses and the destination address of the instruction in accordance with the content of corresponding resource-per-warp register 260, so that the designated portions in the GPRs mapped for different warps are not overlapped.
In alternative embodiments, not only instructions in one kernel are divided into multiple independent segments, and each instruction segment is executed with one warp, but also the software sets the content of resource-per-warp registers 260 #0 to 260 #7 before or at the beginning of the execution of the kernel to point to the base address of the GPRs 230, which is associated with each warp.
The present invention may be applied to cooperative warps that perform tasks in parallel. Refer to the exemplary flowchart as illustrated in
Step S510: The warp instruction scheduler 220 starts to fetch instructions for each warp and stores the fetched instructions in the instruction cache 240.
Steps S520 to S540 form a loop. The warp instruction scheduler 220 may use a scheduling method (such as, the round-robin algorithm, etc.) to obtain the designated instructions from the instruction cache 240 one by one in accordance with the corresponding program counters of the warps. The designated instructions are sent to the ALU 210 for execution. For example, the warp instruction scheduler 220 may sequentially obtain the instruction indicated by the program counter of the 0th warp, the instruction indicated by the program counter of the 1st warp, and so on.
Step S520: The warp instruction scheduler 220 obtains the instruction for the 0th or the next warp from the instruction cache 240.
Step S530: The warp instruction scheduler 220 sends the obtained instruction to the ALU 210.
Step S540: The ALU 210 performs the designated calculation in accordance with the input instruction. In the pipeline for executing the instruction, the ALU 210 obtains data from the source address(es) in the GPRs 230, performs the designated operation on the obtained data, and stores the calculation result in the destination address in the GPRs 230.
In order to prevent different warps from conflicting when accessing to the GPRs 230, in some embodiments of step S510, the warp instruction scheduler 220 allows each warp to process instructions (also called as relatively independent instructions) of the designated segment in the same kernel in accordance with the warp dispatch instructions (may refer to the above pseudo code). The instruction segments are arranged to be independent from each other, and can be executed in parallel.
In alternative embodiments, the warp instruction scheduler 220 before sending the instruction to the ALU (before step S530), modifies the source address(es) and the destination address of the instruction in accordance with the content of corresponding resource-per-warp register 260 to map to the storage space in the GPRs 230, which is dynamically configured to this warp.
In alternative embodiments, the warp instruction scheduler 220 not only allows each warp to process instructions (also called as relatively independent instructions) of the designated segment in the same kernel in accordance with the warp dispatch instructions (may refer to the above pseudo code) in step S510, but also, before sending the instruction to the ALU (before step S530), modifies the source address(es) and the destination address of the instruction in accordance with the content of corresponding resource-per-warp register 260.
The present invention would be applied to the executions of cooperative producer-consumer warps. Refer to
Regarding the producer-consumer task executions, for details, refer to the exemplary flowchart as shown in
Step S710: The warp instruction scheduler 220 starts to fetch instructions for each warp and stores the fetched instructions in the instruction cache 240. The warp instruction scheduler 220 may make each warp responsible for processing instructions of the designated segment in the same kernel in accordance with the warp dispatch instructions (may refer to the above pseudo code). These instruction segments are arranged to form the producer-consumer relationship.
Step S720: The warp instruction scheduler 220 obtains the barrier instruction 621 from the instruction cache 240 for the consumer warp 610, and accordingly forces the consumer warp 610 to enter the waiting state.
Step S730: The warp instruction scheduler 220 obtains a series of instructions 661 from the instruction cache 240 for the producer warp 650, and sends the obtained instructions to the ALU 210 sequentially.
Step S740: The ALU 210 performs the designated calculation in accordance with the input instruction. In the pipeline for executing the instruction, the ALU 210 obtains data from the source address(es) in the GPRs 230, performs the designated operation on the obtained data, and stores the calculation result in the destination address in the GPRs 230.
Step S750: The warp instruction scheduler 220 obtains the barrier instruction 663 from the instruction cache 240 for the producer warp 650, and accordingly wakes up the consumer warp 610. In some embodiments, the warp instruction scheduler 220 may force the producer warp 650 to enter the waiting state.
Step S760: The warp instruction scheduler 220 obtains a series of instructions 623 from the instruction cache 240 for the consumer warp 610, and sends the obtained instructions to the ALU 210 sequentially.
Step S770: The ALU 210 performs the designated calculation in accordance with the input instruction. In the pipeline for executing the instruction, the ALU 210 obtains data (including the data previously generated by the producer warp 650) from the source address(es) in the GPRs 230, performs the designated operation on the obtained data, and stores the calculation result in the destination address in the GPRs 230.
It is to be noted that the content of steps S730, S740, S760, and S770 are merely brief descriptions for easy understanding. During the execution of steps S730, S740, S760, and S770, the warp instruction scheduler 220 may obtain instructions from the instruction cache 240 for other warps (that is, neither the warp 610 nor the warp 650), and drive the ALU 210 to perform relevant calculations.
Although the embodiment has been described as having specific elements in
While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
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202011131448.9 | Oct 2020 | CN | national |