Claims
- 1. A memory device, comprising:
a dynamic memory core having memory cells arranged in rows and columns; a plurality of external connections; and interface circuitry coupled to said memory core and coupled to said external connections to receive row operation and column operation information, wherein said interface circuitry is configured to perform data transfers on said external connections in response to said column operation information, wherein said interface circuitry is configured to receive row operation information concurrently with data transfers on said external connections and wherein said interface circuitry is configured to receive column operation information concurrently with row operation information.
- 2. A memory device, comprising:
a static memory core having memory cells arranged in rows and columns; a plurality of external connections; and interface circuitry coupled to said memory core and coupled to said external connections to receive row operation and column operation information pertaining to said static memory core, said interface circuitry configured to perform data transfers in response to said column operation information, wherein said interface circuitry is configured to receive a row operation information separately from column operation information.
- 3. A memory device, comprising:
a read-only memory core having memory cells arranged in rows and columns; a plurality of external connections; and interface circuitry coupled to said memory core and coupled to said external connections to receive row operation and column operation information pertaining to said read-only memory core, said interface circuitry configured to perform data transfers in response to said column operation information, wherein said interface circuitry is configured to receive row operation information separately from column operation information.
- 4. A method of operating a memory device having a dynamic memory core and an interface for receiving row and column operation information and for transferring data information comprising the steps of:
receiving row operation information concurrently with data transfers; receiving column operation information concurrently with receiving row operation information; and performing data transfers at said interface in response to said column operation information.
- 5. A method of operating a memory device having a static memory core and an interface for receiving row operation and column operation information and for transferring data information, said method comprising the steps of:
receiving row operation information separately from column operation information; and performing data transfers in response to said column operation information.
- 6. A method of operating a memory device having a read-only memory core and an interface for receiving row operation and column operation information and for transferring data information, said method comprising the steps of:
receiving row operation information separately from column operation information; and performing data transfers in response to said column operation information.
Parent Case Info
[0001] This application is a divisional of application Ser. No. 10/053,632 filed on Jan. 18, 2002; which is a divisional of application Ser. No. 09/169,526 filed on Oct. 9, 1998, now U.S. Pat. No. 6,356,975 which issued on Mar. 12, 2002; which claims priority to provisional application Ser. No. 60/061,682 filed Oct. 10, 1997.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60061682 |
Oct 1997 |
US |
Divisions (2)
|
Number |
Date |
Country |
Parent |
10053632 |
Jan 2002 |
US |
Child |
10817781 |
Apr 2004 |
US |
Parent |
09169526 |
Oct 1998 |
US |
Child |
10053632 |
Jan 2002 |
US |