Claims
- 1. A Flash memory unit comprising:
a plurality of Flash memory cells, each Flash memory cell including a source, a drain, a well, a floating gate, and a control gate, a dummy Flash memory cell, each Flash memory cell including a source, a drain, a well, a floating gate, and a control gate, a comparison circuit for comparing the current through the dummy Flash memory cell with the current through one of the Flash memory cells, and a control circuit for controlling when the current through the Flash memory cell represents a predetermined amount of charge stored on the floating gate of the Flash memory cell.
- 2. The Flash memory unit as recited in claim 1 wherein one amount of charge defines the logic states for a NORMAL READ operation and a larger second amount of charge amount defines the logic states for a TEST READ operation.
- 3. The Flash memory unit as recited in claim 2 wherein a third amount of charge, larger than the second charge amount, defines the logic states for an amount of charge stored on the floating gate as a result of a WRITE operation.
- 4. The Flash memory unit as recited in claim 1 further comprising a state machine, the state machine controlling the control circuit, the control circuit thereby determining the identification of a logic state identified by a NORMAL READ operation and the logic state identified by a TEST READ operation.
- 5. The Flash memory unit as recited in claim 4 wherein, when the logic state for a Flash memory cell determined by a TEST READ operation is different then the logic state for the same cell determined by a NORMAL READ operation, the state machine refreshes the charge stored on the floating gate of the Flash memory cell cell.
- 6. A method of providing a charge margin for the cells of a Flash memory unit, the method comprising:
adding charge to a Flash memory cell when the charge stored on the floating gate of a memory cell is less that a predetermined amount.
- 7. The method as recited in claim 6 further comprising defining a logic state determined by a first charge for a NORMAL READ operation, defining a logic state determined by a second charge greater than the first charge for a TEST READ operation.
- 8. The method as recited in claim 7 further comprising determining a presence of at least the first charge and a presence of at least the second charge by comparing the current through the Flash memory cell with the current through a dummy Flash memory cell.
- 9. The method as recited in claim 7 wherein the comparing step is implemented with the same voltages being applied to the Flash memory cell during the NORMAL READ operation and the TEST READ operation.
- 10. The method as recited in claim 9 further comprising, after using a series of TEST READ operations for all the memory cells of the memory unit, computing a checksum to determine whether further refreshing of cells in the Flash memory unit is necessary.
- 11. The method as recited in claim 7 further comprising implementing a WRITE operation that results in a stored charge greater than a third stored charge, the third stored charge being greater than the second stored charge.
- 12. A Flash memory cell unit comprising:
a plurality Flash memory cells, at least one dummy Flash memory cell, and a comparison circuit for comparing the current flowing through a selected Flash memory cell and the dummy Flash memory cell, comparison circuit determining a first logic state for the selected Flash memory cell during a NORMAL READ operation when the a charge stored on the floating gate is greater that a first charge amount, the comparison circuit determining the first logic state for a TEST READ operation when the charge stored on the floating gate is greater that a second charge amount, the second charge amount being greater than the first charge amount.
- 13. The Flash memory unit as recited in claim 12 wherein, when the first logic state is identified in the NORMAL READ operation but not in the TEST READ operation, the charge stored on the floating gate of the selected Flash memory cell has decayed by an unacceptable amount.
- 14. The Flash memory unit as recited in claim 12 wherein a TEST READ operation is performed on all of the Flash memory cells as part of test checksum calculation.
- 15. Apparatus for testing a Flash memory cell, the apparatus comprising:
a dummy memory cell; a component for generating a first voltage proportional to current through the dummy cell; a component for generating a second voltage proportional to the current through the Flash memory cell, wherein the factor of proportionality between the second voltage and the current through the Flash memory cell is controllable; and voltage supply units for activating the dummy cell and the Flash memory cell.
- 16. The apparatus as recited in claim 15 wherein a first factor of proportionality tests the Flash memory cell for a NORMAL READ operation, and wherein a second factor of proportionality tests the Flash memory unit for a TEST READ operation.
- 17. The apparatus as recited in claim 16 wherein the activation parameters for the Flash memory cell during the TEST READ operation are the same as the parameters during the NORMAL READ operation
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Application No. 60/2555,270, filed Dec. 13, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
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60255270 |
Dec 2000 |
US |