Patent Application
20050133165
(1) Technical Field
This invention relates generally to semiconductor processes and more particularly to improvements to vapor deposition equipment for the prevention of high energy arcing causing particulate contaminants to settle on semiconductor substrates during deposition of titanium nitride.
2. Description of the Prior Art
The fabrication of integrated circuit devices is a complex manufacturing process-involving hundreds of steps that must be executed with great precision. In simplified terms, making devices involves three basic operations: deposition, patterning and etching. These and other processes are repeated many times on a silicon base substrate resulting in the buildup of microscopically thin layers of materials. In the process of building these layers, thousands or millions of transistors are created and interconnected. When the process is complete, a single silicon base substrate will contain hundreds of individual devices that are then diced into separate device entities, tested for their electrical properties, packaged and assembled.
During the forming of these well-defined integrated circuit structures, it has become increasingly important to construct line widths measuring in the sub micron and nanomicron ranges. Advances in circuit packaging generally include reducing the size of components that form these integrated circuit structures. With smaller circuit components, the value of each unit area on a silicon base substrate becomes higher because the ability to use all of the substrate area for circuit components improves. To properly form an integrated circuit with advanced circuit designs that use higher percentages of the substrate area for smaller components, it is critical that defect counts on a semiconductor substrate be reduced below levels, which were previously acceptable for many circuit designs. For example, minute particles of less than 0.2 microns are unacceptable for many of the current advanced circuit designs. This is because the small particles or defects can damage the integrated circuit by shorting out two or more circuit lines or by cutting or otherwise impairing the operation of these circuits.
Thin film deposition techniques occupy an advantageous position among current technologies. The established processes remain efficient for many applications, while newer ones are evolving rapidly based on customer requirements and evolutionary technology. Tools are customized for sophisticated and often difficult applications. This rapid movement involves significant challenges. Manufacturers express an increasing need to deposit films, on larger substrates, that are free from contaminates.
Applied Materials, Inc., a leader in making semiconductor equipment, provides an integrated CVD/PVD (chemical and physical vapor deposition) system. The Liner TxZ Centura designed for the metallization of devices with 0.35-micron and under line widths, combines a CVD titanium nitride chamber with a PVD titanium chamber on a Centura/Endura platform. It enables chip producers to deposit sequential layers of Ti and CVD TiN without worrying about the growth of unwanted oxide between processing steps.
Referring to
The present invention has been accomplished in view of the above mentioned problems. That is therefore a primary object of the present invention to prevent particulate contaminates from being formed and landing on semiconductor substrates during vapor deposition of TiN in a CVD-TXZ chamber.
Another object of the present invention has been to eliminate a spark discharge in the vicinity of the semiconductor substrate.
Still another object of the present invention has been to increase CVD-TiN utilization by reducing down time needed for machine maintenance.
Yet another object of the present invention has been to improve product quality and throughput during vapor deposition of TiN.
These objects have been achieved by a design modification of an conductive strap and isolation rings so that the potential difference is reduced and any cumulative electric charge build-up would pass through the bottom of the isolation rings to the supporting heater surface instead of arching between a gap separating the inner periphery of the annular housing and the outer periphery of the heater platform. The spark discharge generates a cloud of particulate contaminates that land on the substrate surface short circuiting sub-micron conductive circuit lines.
Chipmaking is a complex manufacturing process-involving hundreds of steps that must be executed with great precision. In simplified terms, chipmaking involves three basic operations: deposition, patterning and etching. These and other processes are repeated many times on a silicon base substrate resulting in the buildup of microscopically thin layers of materials. In the process of building these layers, thousands or millions of transistors are created and interconnected. When the process is complete, a single silicon base substrate will contain hundreds of individual chips that are then diced into separate chip entities, tested for their electrical properties, packaged and assembled.
In view of the prior art, it is a principle object of the present invention to provide an improved design of a conductive strap and isolation rings contained within the annular housing. The improvement is put into practice so that a potential difference, within an electric field, is reduced in order that any cumulative charge would pass through the bottom of the isolation rings to the supporting heater surface instead of arching between a gap separating the inner periphery of the annular housing and the outer periphery of the heater platform, thereafter, eliminating the cloud of particulate contaminates that land and short circuit the sub-micron circuit lines formed on the semiconductor substrate.
Analysis of the process has shown that arcing occurs in the gap area separating the heater and periphery of the annular housing. The reason is that the proximity of the periphery of the annular housing 22 to the outer periphery of the heater 21 creates a path of least resistance whenever a large difference of electric potential between the two is too high and the arc current jumps the gap between the annular housing and heater.
Referring now to
In summary, a substrate processing apparatus for processing a semiconductor substrate is disclosed. The apparatus includes a vacuum chamber, and a heater assembly disposed within the vacuum chamber. The heater assembly consists of a heater with a supporting surface and an annular housing supported by the heater. The annular housing has a top surface and a bottom surface and a cylindrical wall extending peripherally below the top surface and the bottom surface. An isolating ring is encircled by the cylindrical wall. The isolating ring is in contact with the bottom surface of the annular housing and the supporting heater surface of the heater. A conductive strap electrically connects the annular housing to the heater through screw holes in place of slots.
These and further constructional and operational characteristics of the invention will be more evident from the detailed description given hereafter with reference to the figures of the accompanying drawings which illustrate preferred embodiments and alternatives by way of non-limiting examples.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
