Apparatus of measuring characteristics of semiconductor devices

Abstract

An apparatus of measuring characteristics of a plurality of semiconductor devices with a plurality of measurement units is disclosed. The apparatus includes a parallel measurement executability determination section and a plurality of measurement function sections. The parallel measurement executability determination section identifies sets of a semiconductor device and a measurement function, which are able to be measured in parallel based on connection information of the semiconductor devices. The plurality of measurement function sections use a first abstractive name which abstractively identifies the plurality of measurement units for the sets of the measurement functions and the semiconductor device which are able to be measured in parallel by the parallel measurement executability determination section.

Description

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing the structure of a semiconductor parametric test system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram showing the structure of software of the semiconductor parametric test system shown in FIG. 1;

FIG. 3 shows a table of an example of a test plan;

FIG. 4 is a list showing an example of a program of measurement function Idoff called in the sequence shown in FIG. 3;

FIG. 5 shows a table of hardware members of a tester identified by port numbers and port names;

FIG. 6 shows a table of types and measurement performances of SMUs contained in the tester;

FIG. 7 shows a table of an example of a hardware use definition that is input to a process together with a test plan;

FIG. 8 shows a table of abstractive names and meanings of measurement units used in the hardware use definition;

FIG. 9 is a schematic diagram showing information that a sequence control section contains;

FIG. 10 shows a table of information contained in a sub sequence status table;

FIG. 11 is a flow chart showing an operation of the sequence control section that identifies a not-executed sub sequence to be inspected for executability;

FIG. 12 is a flow chart showing an operation of a sub sequence process;

FIG. 13 shows a table of a test plan that represents a parallel test attribute;

FIG. 14 shows a sub sequence status table for the sequence shown in FIG. 13;

FIG. 15 shows a table of a test plan that describes parallel test attributes and that is used in the case that although devices are designed to be electrically insulated and they mutually interfere due to other than a device structure such as a probe card;

FIG. 16 shows a sub sequence status table for the test plan shown in FIG. 15;

FIG. 17 shows a table of a test plan describing an attribute that denotes that a sub sequence of a device is not able to be executed when a designated sub sequence of a designated device is executed;

FIG. 18 shows a sub sequence status table for the test plan shown in FIG. 17;

FIG. 19 is a sequence chart showing signal handling in the case that a sub sequence is executed;

FIG. 20 shows a hardware management table that is contained in a hardware management section and that is used to manage individual hardware members of the tester;

FIG. 21 shows a real hardware allocation priority table for abstractive hardware type names in the hardware management section;

FIG. 22 is a schematic diagram showing information that the hardware management section contains;

FIG. 23 is a flow chart showing an operation of a process that the hardware management section performs to allocate real hardware members;

FIG. 24 shows an allocatable abstractive hardware table contained in the hardware management section;

FIG. 25 is a schematic diagram showing information that a tester control section contains;

FIG. 26 is a flow chart showing a process that the tester control section performs to correlate port names of measurement functions with hardware members;

FIG. 27 shows an allocated hardware table;

FIG. 28 shows a port name correlation table;

FIG. 29 shows a table representing the structure of a tester used in the case that the semiconductor parametric test system according to an embodiment of the present invention executes sub sequences in parallel;

FIG. 30 shows a table of assumed execution times of measurement functions in sub sequences;

FIG. 31 shows a table of executed results of sub sequences;

FIG. 32 is a schematic diagram showing the structure of a semiconductor parametric test system according to another embodiment of the present invention; and

FIG. 33 is a sequence chart showing the operation of the semiconductor parametric test system according to the embodiment having the structure shown in FIG. 32.

Claims

1. An apparatus of measuring characteristics of a plurality of semiconductor devices with a plurality of measurement units, the apparatus comprising: parallel measurement executability determination means for identifying sets of a semiconductor device and a measurement function, which are able to be measured in parallel based on connection information of the semiconductor devices; anda plurality of measurement function sections which use a first abstractive name which abstractively identifies the plurality of measurement units for the sets of the measurement function and the semiconductor device which are able to be measured in parallel by the parallel measurement executability determination means.

2. The apparatus as set forth in claim 1, further comprising: measurement unit allocation means, having measurement unit information containing a second abstractive name which abstractively identifies the plurality of measurement units, for allocating an abstractively identified measurement unit for the set of the semiconductor device and the measurement function, which are able to be measured in parallel by the parallel measurement executability determination means, to the measurement function.

3. The apparatus as set forth in claim 2, wherein the measurement unit information correlatively contains the second abstractive name which abstractively identifies the plurality of measurement units and priority levels based on which the plurality of measurement units are allocated to measurement functions, andwherein the measurement unit allocation means allocates the abstractively identified measurement units to the measurement functions in the order of higher priority levels.

4. The apparatus as set forth in claim 3, wherein when there are a plurality of measurement units allocatable to the second abstractive name, the priority levels are assigned lower values in proportion to non-substitutability of the measurement units, andwherein when there are a plurality of the second abstractive names that are able to identify a measurement unit, the priority levels of the second abstractive names are assigned higher values in proportion to non-substitutability of the measurement units.

5. The apparatus as set forth in claim 1, wherein the plurality of measurement function sections operate in parallel.

6. The apparatus as set forth in claim 1, further comprising: parallel test attribute input means for inputting a parallel test attribute,wherein when information which permits a predetermined set of the semiconductor devices to be measured in parallel is input to the parallel attribute input means, the parallel measurement executability determination section determines whether or not the predetermined set is able to be measured in parallel.

7. The apparatus as set forth claim 1, further comprising: parallel test attribute input means for inputting a parallel test attribute,wherein when information which does not permit a predetermined set of the semiconductor devices to be measured in parallel is input to the parallel attribute input means, the parallel measurement executability determination means determines whether or not the other than the predetermined set is able to be measured in parallel.

8. The apparatus as set forth in claim 1, further comprising: parallel test attribute input means for inputting a parallel test attribute,wherein when information which denotes that a predetermined semiconductor device of the semiconductor devices is not able to be measured in parallel is input to the parallel test attribute input means, the parallel measurement executability determination means determines whether or not other than the predetermined semiconductor device is able to be measured in parallel.

9. An apparatus of executing a measurement function for a semiconductor device with a plurality of measurement units and measuring characteristics of the semiconductor device, the apparatus comprising: measurement allocation portion, having measurement unit information containing abstractive names which abstractively identify the measurement units, for allocating abstractively identified measurement units of a set of semiconductor devices and measurement functions to the measurement functions.