FIELD OF THE DISCLOSURE
The present disclosure relates generally to semiconductor devices, and more particularly to SOI devices having area diodes and to methods for making the same.
BACKGROUND OF THE DISCLOSURE
Electrostatic discharge (ESD) protection has emerged as a significant challenge for semiconductor devices. ESD, originating from such sources as mechanical chip carriers, plastic chip storage devices, or human contact, can generate voltages that are many times greater than the design voltages of integrated circuits. For example, the human body can supply an electrostatic discharge of up to 4 kilovolts, which can be devastating to integrated circuits that commonly operate at voltages of less than 5V.
In light of the challenge posed by ESD, many semiconductor circuits are now equipped with ESD dissipation features. However, in a typical semiconductor-on-insulator (SOI) technology, the presence of a buried oxide (BOX) layer places limitations on the structures that can be used for ESD protection. In particular, the presence of the BOX layer in SOI devices complicates the implementation of vertical NPN or diode structures. Moreover, the poor thermal conductivity of the buried oxide causes thermal failure levels to be much lower in SOI devices than in analogous bulk devices.
Accurate temperature sensing has also been a significant issue on power dissipation control in microprocessor SOI applications. The ideality factor of the diode has been recognized as a key parameter in temperature sensing devices. However, conventional lateral diodes in SOI applications exhibit high series resistance and poor thermal conductivity, causing a significant deviation from a diode ideality.
Despite the foregoing problems, diode structures have been built on SOI films that provide some ESD protection and temperature sensing capabilities. One example of such a diode structure is the conventional lateral diode 101 built on an SOI film which is shown in FIG. 1. The diode comprises a buried oxide layer 103 upon which is disposed a device layer 105 that includes cathode 107 and anode 109 implants and an N-well 111. A polysilicon gate 113 is disposed over the N-well 111 and is electrically insulated from the N-well 111 by a gate oxide layer 115. The polysilicon gate 113 is bounded on each side by spacers 117, 119.
While lateral diodes of the type depicted in FIG. 1 provide some ESD protection, the protection they afford is typically lower than that achievable with comparable bulk devices. More recently, however, it has been shown that further improvements in ESD protection can be achieved through the use of vertical diode structures. Such structures have been found to offer improved ESD protection compared to their lateral diode counterparts, due to improved lattice temperature distribution. Vertical diode structures offer the further advantage of occupying less space than their lateral counterparts.
An example of a vertical diode structure is depicted in FIG. 2. The vertical diode 151 depicted therein comprises a substrate 153 within which is defined an N-well 155. Anode 157 and cathode 159 regions are implanted in the N-well 155 and are in electrical contact with anode 161 and cathode 163 electrodes, respectively. A buried oxide (BOX) layer 165 is disposed over the N-well 155 adjacent to the anode 157 and cathode 159 regions. A shallow trench isolation (STI) layer 167 is disposed over the BOX layer 165 in the area next to the anode 157 and cathode 159 regions, and an SOI layer 171 is disposed over the BOX layer 165 elsewhere. An interlayer dielectric (ILD) 173 is disposed over the substrate 153 in the vicinity of the anode 157 and cathode 159 electrodes and over the SOI layer 171 and STI layer 167.
While vertical diode structures of the type depicted in FIG. 2 have some desirable attributes from an ESD protection perspective, they also have some significant disadvantages. In particular, vertical diode structures of the type depicted in FIG. 2 have relatively low packing densities, which is a significant disadvantage in light of the ongoing trend in the semiconductor industry towards further miniaturization. Moreover, since the N-well 155 underlies the STI 167 and BOX 165, it is very difficult to fabricate reproducibly in a conventional CMOS process.
There is thus a need in the art for methods and devices which address the aforementioned infirmities. In particular, there is a need in the art for SOI devices having ESD and/or temperature sensing structures which have higher packing densities with typical CMOS process compatibility, and for methods for making the same. There is further a need in the art for such SOI devices that exhibit thermal failure levels that are comparable to those observed in analogous bulk devices. These and other needs are met by the devices and methodologies described herein.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an illustration of a prior art lateral edge diode;
FIG. 2 is an illustration of a prior art vertical diode;
FIG. 3 is an illustration of an embodiment of area diode made in accordance with the teachings herein;
FIG. 4 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 5 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 6 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 7 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 8 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 9 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 10 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 11 is an illustration of one step in a process for making area diodes in accordance with the teachings herein;
FIG. 12 is an illustration of one step in a process for making area diodes in accordance with the teachings herein; and
FIG. 13 is an illustration of one step in a process for making area diodes in accordance with the teachings herein.
DETAILED DESCRIPTION
In one aspect, a method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor stack is provided which comprises a semiconductor substrate, a first semiconductor layer, and a first dielectric layer disposed between the substrate and the first semiconductor layer. A first trench is formed in the first dielectric layer which exposes a portion of the substrate, and a first implant region is formed in the first trench. Cathode and anode regions are formed in the first implant region.
In another aspect, a method for making a semiconductor device is provided. In accordance with the method, a substrate is provided which has a first semiconductor layer disposed thereon. A first dielectric layer is disposed between the substrate and the first semiconductor layer. A portion of the first dielectric layer is then exposed, and a second dielectric layer is formed over the exposed portion of the first dielectric layer. A trench is created which extends through the first and second dielectric layers and which exposes a portion of the substrate. A second semiconductor layer is then formed over the exposed portion of the substrate, and anode and cathode regions are formed in the second semiconductor layer.
In still another aspect, a semiconductor device is provided which comprises (a) a substrate having a first dielectric layer disposed thereon, (b) a first semiconductor layer disposed over a first region of the first dielectric layer, (c) a second dielectric layer disposed over a second region of the first dielectric layer, and (d) an implant region, disposed on said substrate, which extends through the first dielectric layer and the second dielectric layer and which has anode and cathode regions defined therein.
These and other aspects of the present disclosure are described in greater detail below.
It has now been found that the packing densities of vertical diode SOI devices can be significantly increased by forming the diodes on top of the substrate, and within a trench formed in the buried oxide (BOX) layer. This approach may be facilitated, in some embodiments, by the use of suitable spacer structures. SOI devices can be made by this methodology which have electrostatic discharge (ESD) and/or temperature sensing structures.
FIG. 3 illustrates a first non-limiting embodiment of a diode structure made in accordance with the teachings herein. As shown therein, the diode structure 201 comprises a substrate 203 upon which is disposed a layer of buried oxide (BOX) 205 and a layer of field oxide (FOX) 207. An N-well 209 (which, in other embodiments, could be a P-well) is disposed on the substrate and is bounded by the BOX layer 205 and the FOX layer 207. A cathode region 211 and an anode region 213 are implanted in the N-well region 209, and are in electrical contact with a cathode electrode 215 and an anode electrode 217, respectively. The structure is covered with an interlayer dielectric (ILD) 219. In some embodiments (see FIG. 13), one or more spacer layers may be provided in the vicinity of the electrodes. Such spacer layers are advantageous in that they can prevent the silicidation process which is preferably used in fabricating the diode from creating an electrical short between the cathode region 211 and the anode region 213 or their associated electrodes.
Compared to the SOI vertical diode of FIG. 2, the N-well 209 of the SOI vertical diode of FIG. 3 is significantly closer to the surface of the device, and the cathode 211 and anode 213 regions are also significantly closer to the surface. Consequently, the trenches in the ILD 219 that are used to form the contacts 215, 217 for these regions may be of much smaller size than those used to create the cathode 161 and anode 163 contacts of FIG. 2. This is due to the fact that variances in trench positioning increase with depth, and because the anisotropy of etching processes used to form the trench are typically less than perfect. Consequently, the methodologies described herein can be used to make SOI vertical diodes with improved packing density and diode ideality.
Moreover, the formation of the N-well/contact structures in the vertical diode of FIG. 3 requires the formation of a single large trench in the BOX and FOX layers, while the vertical diode structure of FIG. 2 requires many narrow trenches to define cathodes and anodes. Since the combined variances in trench placement for many narrow trenches is greater than that associated with a single large trench, this factor further increases packaging density for the vertical diode structure of FIG. 3 as compared to the vertical diode structure of FIG. 2.
The vertical diode structure of FIG. 3 is further advantageous over the prior art diode structure depicted in FIG. 2 in that, in the device of FIG. 3, the N-well 209 is formed close to the surface. By contrast, in the prior art diode structure depicted in FIG. 2, the N-well 155 is formed under a very thick stack of STI 167 and BOX 165 layers, where it can interfere with other active devices on the same wafer. The N-well 155 cannot be formed by typical CMOS processes such as implantation and thermal diffusion without degradation of other active devices.
FIGS. 4-13 illustrate one particular, non-limiting embodiment of a method that may be used to make a vertical diode structure of the type disclosed herein. With reference to FIG. 4, a wafer 301 is provided which contains a substrate 303. The substrate 303 may be a P- type or N-type substrate, and has a semiconductor layer 305 disposed thereon. A buried oxide (BOX) layer 307 is disposed between the semiconductor layer 305 and the substrate 303. A wafer of the type depicted in FIG. 4 may be formed from a handle wafer and a donor wafer using methods that are well known to the art.
The semiconductor layer 305 in the wafer depicted in FIG. 4 preferably comprises Si or Ge, and even more preferably comprises pure, single crystal Si or Ge, but may also comprise SiGe, GeC, SiGeC, or SiC. The BOX layer 307 preferably comprises silicon oxide, but may also comprise germanium oxide, silicon nitride or other types of dielectrics. It will be appreciated that the wafer 301 depicted in FIG. 4 may contain various other layers and features as are known to the art, although these additional layers and features have been omitted for simplicity of illustration.
As shown in FIG. 5, a portion of the semiconductor layer 305 is removed through the use of a suitable etching technique. Removal of the portion of the semiconductor layer will typically involve depositing a layer of photoresist over the semiconductor layer 305, patterning the photoresist to form a suitable mask, and treating the exposed portion of the semiconductor layer 305 with aqueous HF or another suitable etchant. The removed portion of the semiconductor layer 305 is then replaced with a field oxide layer 309 using chemical vapor deposition (CVD) or another suitable technique.
FIG. 6 illustrates the formation of a substrate window in the structure of FIG. 5. As shown in FIG. 6, a layer of photoresist 311 is deposited over the structure and is patterned and exposed using suitable photolithographic techniques to define an opening therein which exposes a portion of the field oxide (FOX) layer 309. The exposed portion of the FOX layer 309 and the underlying portion of the BOX layer 307 are subsequently removed by etching, thereby exposing a portion of the substrate 303. This is followed by stripping photoresist 311 from the structure, typically through the use of a suitable solvent.
As shown in FIG. 7, a layer of semiconductor material 313 is then epitaxially grown on the exposed surface of the substrate. The resulting structure may optionally be subjected to chemical mechanical planarization (CMP) at this point to compensate for any non-planarity in the surface as a result of epitaxial growth.
As shown in FIG. 8, a layer of photoresist 315 is then deposited over the structure and is patterned and exposed using suitable photolithographic techniques to define an opening therein which exposes at least a portion of the layer of expitaxially grown semiconductor material 313. The exposed portion of the semiconductor material 313 is then subjected to ion implantation to define an N-well 317 therein. It will be appreciated, of course, that the same general approach may be used to form a P-well, in which case a dopant of reversed polarity would be used. In some variations of the methodology described herein, the N-well 317 may be formed by incorporating a suitable dopant into the semiconductor layer 313 as it is epitaxially grown, which in some cases may remove the need for the subsequent ion implantation step depicted in FIG. 8. In other embodiments, the photomask 311 utilized in the etching step to form the trench may be retained through the subsequent epitaxial growth step. The photomask 311 may then be utilized as an implant mask during the ion implantation step that may be used to define the N-well 317.
As shown in FIG. 8, a P-well 319 has also been defined in the semiconductor layer 305 of FIG. 7. The P-well 319 may be formed using the same general type of masking and implantation steps as described above in reference to the formation of the N-well 317, but using a dopant of reversed polarity. The P-well 319 may be formed before or after the formation of the N-well 317, and will typically require separate masking and implantation steps. In some applications, however, as in applications where the wells 317 and 319 have the same polarity, they may be formed in a single masking and implantation step.
As shown in FIG. 9, a layer of gate dielectric 321 is defined over a portion of the P-well 319. This may be accomplished, for example, by forming a suitable mask over the structure which exposes a portion of the P-well 319, followed by a suitable thermal oxidation or deposition process. A gate 323 is then defined over the gate dielectric 321, as through masking and deposition or by another suitable process. The gate dielectric 321 may comprise various materials, including, but not limited to, silicon oxide, germanium oxide, and various metal oxides. The gate 323 may comprise polysilicon, various conductive metals, or other suitable gate materials as are known to the art.
As shown in FIG. 10, one or more extension layers 325 are then formed in the P-well 319. Preferably, this is achieved through shallow ion implantation used in conjunction with an implantation mask that exposes a portion of the P-well 319 in the vicinity of the gate 323, although other suitable techniques may also be employed.
As shown in FIG. 11, a layer of spacer material 327 is then deposited over the structure, which itself is followed by deposition of a layer of a suitable photoresist 329. The layer of photoresist 329 is then patterned and exposed through the use of suitable photolithographic techniques to form a mask which exposes portions of the layer of spacer material 327. A suitable (preferably dry) etchant is then used to remove the exposed portions of the spacer layer 327, thereby forming one or more spacer structures therein. Such spacer structures are advantageous in that they can prevent the silicidation process which is preferably used in fabricating the diode from creating an electrical short between the subsequently formed cathode region 331 and the anode region 333 (see FIG. 12) or their associated electrodes.
Cathode 331 and anode 333 regions are subsequently implanted in the exposed portions of the N-well 317. Similarly, a source or drain region 335 is typically implanted in the P-well 319 to form the transistor. Implantation processes that may be used to form the anode and cathode regions, and the N-wells and P-wells in the structures depicted herein, are well known to the art and involve the use of suitable dopants which, depending on the polarity of the structure being formed, may include n-type species such as phosphorous or arsenic, or p-type species such as gallium or boron. Also, as previously noted, these implantation steps may be avoided in some cases through the incorporation of a suitable dopant into the materials of these regions as they are being formed. In some embodiments of the methodology described herein, the structure may be subjected to silicidation after the cathode 331, anode 333 and source or drain regions 335 have been defined, which will generally involve depositing a metal over the structure and exposing the structure to a heated atmosphere to form silicide wherever the metal contacts silicon or other semiconductor materials.
As shown in FIG. 13, an Inter-Layer Dielectric (ILD) 339 is then deposited over the structure. The ILD 339 may comprise silicon nitride, boron nitride, an oxide, or other suitable ILD materials as are known to the art. The ILD 339 is subsequently masked and etched to define trenches therein which terminate at the surfaces of the anode region 333, the cathode region 331 and the source or drain region 335. The trenches are then backfilled with tungsten 337 or another suitable electrode material.
The above description of the present invention is illustrative, and is not intended to be limiting. It will thus be appreciated that various additions, substitutions and modifications may be made to the above described embodiments without departing from the scope of the present invention. Accordingly, the scope of the present invention should be construed in reference to the appended claims.
Patent Application
20060284278
