Patent Application
20230340660
As pattern sizes shrink during semiconductor manufacture, alignment of masks with the existing features on a substrate has become a critical impediment to further reduction in feature size. Misalignment of substrate and mask results in edge-placement error, which is the difference between the desired and actual position of a feature on the device. These discrepancies can result in both immediate device failure and time-dependent dielectric breakdown, impacting device reliability. Additionally, in the case of via contact to metal lines, edge placement error can result in increased capacitance between a via and a neighboring metal line, as well as decrease the contact area between the via and the target line, increasing resistance. The resulting RC delay can significantly degrade device performance by slowing the switching speed of the transistors.
One method for avoiding the problem of edge placement error is to create fully self-aligned vias (FSAV) where a dielectric film is grown selectively on the existing dielectric layer, without growth on the metal lines. Such area-selective deposition (ASD) can alleviate these manufacturing challenges by enabling bottom-up material placement without the use of masks. In the case of FSAV, the topography created by an ASD dielectric-on-dielectric (DoD) process affords greater vertical distance between subsequent metal layers, allowing for greater latitude in horizontal misplacement or larger critical-dimension (CD) vias. A number of previously described schemes have involved the deposition of ASD DoD layers, but few have been able to achieve the desired film thickness of 5 to 10 nm while simultaneously meeting other film property and manufacturability targets.
In one embodiment, the disclosure relates to a method for selectively depositing a metal oxide or dielectric layer on a patterned substrate, the method comprising:
The following detailed description of preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawing. For the purposes of illustrating the invention, there is shown in the drawing an embodiment which is presently preferred. It is understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. In the drawing:
Aspects of the disclosure relate to a method for the formation of area-selective deposition dielectric-on-dielectric (ASD DoD) layers by first reacting a patterned substrate with a heteroatom silacyclic compound, and then performing metal oxide atomic layer deposition (ALD) growth using sequential metal alkyl and water pulses or chemical vapor deposition (CVD) growth using concurrent addition of metal alkyl and water to selectively grow the resulting metal oxide or dielectric layer or film on the non-metallic portion of the patterned substrate.
It has been discovered that at sufficiently high temperatures, such as from about 175° C. to about 350° C., preferably about 225° C. to about 275° C., the exposure of a metallic surface to a heteroatom silacyclic compound results in significant inhibition of film growth upon subsequent exposure to metal-oxide forming deposition processes. Specifically, the heteroatom silacyclic compound acts as a blocking group to manipulate the growth of metal oxides, such as zinc oxide, on various patterned substrates. While an inhibition effect on non-metallic substrates is also observed after exposure to heteroatom silacyclic compounds, this effect is greater on the metallic portion of the substrate, resulting in selective growth of the metal oxide film on the non-metallic area of the substrate. Zinc oxide films of over seven nm in thickness have been grown on thermal oxide substrates without growth on copper under identical conditions. Considering as a specific example a PVD copper on silicon patterned substrate, it has been found that at sufficiently high temperatures (such as about 175° C. to about 350° C., particularly about 225° C. to 275° C.), the heteroatom silacyclic compound blocking layer delays the growth of a zinc oxide film on the copper portions of the substrate, thus enabling selective growth on the silicon portions.
The method according to the disclosure involves introducing a patterned substrate having metallic and non-metallic regions into a reaction zone of a deposition chamber and heating the reaction zone to about 175° C. to about 350° C., exposing the patterned substrate to a pulse of a heteroatom silacyclic compound and purging the deposition chamber, and then performing an ALD or CVD on the patterned substrate to form a metal oxide or dielectric layer or film. For the purposes of this disclosure, the terms “layer” and “film” may be understood to be synonymous. In one embodiment, the ALD involves exposing the substrate (now containing a blocking layer) to the following sequence of steps which are repeated as many times as necessary to achieve the desired film thickness: exposing the substrate to a pulse of a metal alkyl compound, purging the deposition chamber, exposing the substrate to a pulse of deionized water, and purging the deposition chamber. The resulting metal oxide or dielectric layer selectively forms on non-metallic regions of the patterned substrate.
In some embodiments, prior to exposing the substrate to the heteroatom silacyclic compound, it is within the scope of the disclosure to pretreat the substrate. The pretreatment may be accomplished by chemical, structural, or plasma pre-treatment methods which are well known in the art. For example, the substrate may be pretreated by washing in ethanol, isopropanol, citric acid, or acetic acid-based formulations, or by exposing the substrate to 60 seconds of N2 remote inductively coupled plasma at 225° C. to 250° C. Other similar substrate pre-treatment processes which are known in the art would also be applicable. Such treatments may improve performance of the resulting films, but the appropriate pretreatment method and conditions may be determined on a case-to-case basis depending on the specific substrate, apparatus, reactants, and reaction conditions.
In some embodiments, after a number of metal alkyl exposure/purge/water exposure/purge sequences (such as about 1 to about 50 sequences) have been completed, the substrate is subjected to a pulse of a plasma treatment, such as for about 10 seconds. For example, a sequence of five exposure/pulse sequences may be performed prior to performing the plasma treatment. This sequence of five (for example) exposure/pulse sequences followed by a plasma pulse may be referred to as a “super cycle.” Such a super cycle may then be repeated as many times as required to form a metal oxide or dielectric film having the desired thickness. In some embodiments, it is also within the scope of the disclosure to perform a plasma treatment step before or after any of the exposure or purging steps.
It is within the scope of the disclosure to prepare metal oxide or dielectric films having thicknesses of 5 to 10 nm, particularly 7 nm to 10 nm, which thicknesses are currently desirable in the microelectronic industry, and further to prepare metal oxide or dielectric films having thicknesses of up to about 50 nm. The desired film or layer thickness may be achieved by repeating the method steps described herein repeatedly.
A variety of metal alkyl compounds may be employed in the method described herein, including, without limitation, Group 12 and Group 13 metal alkyl compounds. Exemplary metal alkyl compounds which may be employed include the presently preferred diethylzinc, trimethylaluminum, and dimethylaluminum isopropoxide, as well as dimethylzinc, trimethylgallium, triethylgallium, triethylaluminum, trimethylindium, dimethylcadmium, and dimethylmercury.
The blocking layer on the patterned substrate is applied by exposing the substrate to a pulse of a heteroatom silacyclic compound, such as a cyclic azasilane, cyclic tellurasilane, or cyclic thiasilane compound.
Appropriate cyclic azasilanes have general formula (1):
In formula (1), R1 is hydrogen or a linear, branched, or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl, or alkylamino group having 1 to about 12 carbon atoms (preferably 1 to about 4 carbon atoms), R2 is a linear, branched, or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl, or alkylamino group having 1 to about 12 carbon atoms (preferably 1 to about 4 carbon atoms), n is an integer of 1 to about 4, and X and Y are each independently a linear, branched, or cyclic, optionally substituted, alkyl, aryl, alkynyl, alkenyl, alkoxy, silyl, or alkylamino group (preferably about 1 to about 4 carbon atoms). It is within the scope of the disclosure for R1, R2, X, and Y to be unsubstituted or substituted with groups such as, without limitation, alkyl (such as methyl, ethyl, or propyl), alkoxysilyl (such as trimethoxysilyl or triethoxysilyl), alkoxy (such as methoxy or alkoxy), and/or halogen (such as chloro, bromo, fluoro, or iodo).
Exemplary R1, R2, X, and Y substituents include, without limitation, hydrogen, methyl, ethyl, n-propyl, i-propyl, n-butyl, s-butyl, t-butyl, pentyl, hexyl, phenyl, cyclohexyl, heptyl, n-octyl, 2-ethylhexyl, nonyl, decyl, dodecyl, octadecyl, methoxy, ethoxy, n-propoxy, i-propoxy, n-butoxy, s-butoxy, t-butoxy, vinyl, allyl, norbornenyl, methylnorbornenyl, ethylnorbornenyl, propylnorbornenyl, trimethylsilyl, trimethoxysilyl, methyl(trimethoxysilyl), ethyl(trimethoxysilyl), propyl(trimethoxysilyl), triethoxysilyl, methyl(triethoxysilyl), ethyl(triethoxysilyl), propyl(triethoxysilyl), amino, methylamino, ethylamino, propylamino, methyl(dimethylamino), ethyl(dimethylamino), propyl(dimethylamino), and chloromethyl.
Preferably, R1 is hydrogen or an alkyl group such as methyl or ethyl, R2 is an optionally substituted alkyl, alkenyl, or alkylamino group having 1 to about 4 carbon atoms, such as 1, 2, 3, or 4 carbon atoms, and X and Y are preferably alkyl or alkoxy groups having 1 to about 4 carbon atoms, such as 1, 2, 3, or 4 carbon atoms.
Exemplary cyclic azasilane compounds which would be effective for forming a blocking layer on the patterned substrate include, without limitation, (N-methyl-aza-2,2,4-trimethyl silacyclopentane, N-(2-aminoethyl)-2,2,4-trimethyl-1-aza-silacyclopentane, N-n-butyl-aza-2,2-dimethoxysilacyclopentane, N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane, (N,N-dimethylaminopropyl)-aza-2-methyl-2-methoxysilacyclopentane, (1-(3-triethoxysilyl)propyl)-2,2-diethoxy-1-aza-silacyclopentane, N-allyl-aza-2,2-dimethoxysilacyclopentane, and N-t-butyl-aza-2,2-diemethoxysilacyclopentane, and have the following structures:
Appropriate cyclic thiasilanes have general formula (2):
In formula (2), R1, n, X, and Y are as described above. Preferably, R1 is hydrogen or an alkyl group such as methyl or ethyl, and X and Y are preferably alkyl or alkoxy groups having 1 to about 4 carbon atoms, such as 1, 2, 3, or 4 carbon atoms.
An exemplary cyclic thiasilane compound which would be effective for forming a blocking layer on the patterned substrate is 2,2,4-trimethyl-1-thia-2-silacyclopentane and has the following structure:
Appropriate cyclic tellurasilanes have general formula (3):
In formula (3), R1, n, X, and Y are as described above. Preferably, R1 is hydrogen or an alkyl group such as methyl or ethyl, and X and Y are preferably alkyl or alkoxy groups having 1 to about 4 carbon atoms, such as 1, 2, 3, or 4 carbon atoms.
An exemplary cyclic tellurasilane compound which would be effective for forming a blocking layer on the patterned substrate is 2,2,4-trimethyl-1-tellura-2-silacyclopentane and has the following structure:
The presently preferred compounds for use in the methods described herein are cyclic azasilanes, and in particular N-methyl-aza-2,2,4-trimethylsilacyclopentane is the preferred compound for forming a blocking layer on the patterned substrate:
The parameters of the purge cycles are not particularly limited, and may be optimized based on the specific reaction conditions, apparatus, and reactants. Generally, any inert gas such as argon or nitrogen may be employed; typical purge cycles are at least about two seconds long. In preferred embodiments, the purges are about 5 seconds (following the metal alkyl pulses and the water pulses) and about 30 seconds following the pulse of the heteroatom silacyclic compound.
The temperatures of the substrate and the reaction zone of the deposition chamber are critical for producing an effective blocking layer of heteroatom silacyclic compound. Specifically, the temperatures of the substrate and of the reaction zone at least during deposition of the metal oxide or dielectric layer are preferably about 175° C. to about 350° C., more preferably about 225° C. to about 275° C. It may be understood that the ranges of substrate temperatures are inclusive of all temperatures within the range, so that temperatures of about 175° C. to about 350° C. include temperatures such as about 200° C., about 225° C., about 250° C., about 275° C., about 300° C., about 325° C., about 300° C., about 325° C., and all temperatures in between.
If the deposition of the blocking layer is performed in the same deposition chamber and under the same reaction conditions as the metal oxide or dielectric layer, the substrate and reaction zone of the deposition temperature may be in this temperature range as well. Optionally, the blocking layer may be applied in the same or different reaction chamber at a different temperature, such as from about 20° C. to about 325° C., inclusive of all temperatures within this range.
The pulse lengths of each reactant may also be optimized based on the specific reaction conditions and apparatus and are generally kept as short as practical. The pulse lengths for the metal alkyl compound and the water may be as short as 0.05 seconds or about 1 second in some embodiments. The pulse lengths of the heteroatom silacyclic compound are relatively short, such as at least about 0.1 second, preferably about 0.1 to about 10 seconds, more preferably about 2 to about 6 seconds, even more preferably about 3 to about 5 seconds, even more preferably about 5 seconds.
It is within the scope of the disclosure to move the reactants, such as the heteroatom silacyclic compound and metal alkyl compound, in a carrier gas. Without limitation, any noble gas, such as argon, or other inert gas, such as nitrogen, would be appropriate. However, it is also within the scope of the disclosure not to employ a carrier gas.
A variety of different types of patterned substrates are appropriate for use in the method described herein, provided that they contain metallic and non-metallic regions. Appropriate substrates include, without limitation, the presently preferred silicon dioxide and copper on silicon. Other possible substrates which would be appropriate include, without limitation, substrates containing non-metallic regions comprising silicon, germanium, silicon-germanium alloy, silicon dioxide, silicon nitride, titanium nitride, tantalum nitride, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, aluminum oxide, hafnium dioxide, titanium dioxide, and/or zinc oxide, and substrates containing metallic regions comprising copper, cobalt, tungsten, ruthenium, and/or molybdenum.
The invention will now be described in connection with the following, non-limiting examples.
Zinc oxide was grown on thermally-grown silicon dioxide cleaned with 60 seconds of N2 remote inductively coupled plasma (2500 W) at 225° C. using an alternating pulse sequence of 0.1 seconds diethylzinc, 5 second purge, 0.1 seconds water, and 5 second purge, repeated 50 times. Film growth was immediate at 2.8 angstroms per cycle. The thickness of the film after 24 cycles was 5.0 nm.
PVD copper on silicon was cleaned by washing for five minutes in ethanol. Zinc oxide was grown on the cleaned copper by exposing the copper substrate to 60 seconds of N2 remote inductively coupled plasma (2500 W) at 225° C. and then further subjecting it to an alternating pulse sequence of 0.1 seconds diethylzinc, 5 second purge, 0.1 seconds water, and 5 second purge, repeated 50 times. Slight film growth of 7 angstroms was observed in the first 24 cycles, after which ALD-like growth began, reaching 2.6 angstroms per cycle by the final cycle.
Thermally-grown silicon dioxide cleaned with 60 seconds of N2 remote inductively coupled plasma (2500 W) at 225° C. and then exposed to N-methyl-aza-2,2,4-trimethylsilacyclopentane for five seconds, followed by a 30 s purge. Subsequently, the substrate was exposed to an alternating pulse sequence of 0.1 seconds diethylzinc, 5 second purge, 0.1 seconds water, and 5 second purge, repeated 50 times. Film growth began on the eleventh cycle and reached 3.0 angstroms per cycle by the final cycle. Film thickness at the forty-fourth cycle was 7.3 nm.
PVD copper on silicon was cleaned by washing for five minutes in ethanol. The copper was then exposed to 60 seconds of N2 remote inductively coupled plasma (2500 W) at 225° C. and then further exposed to N-methyl-aza-2,2,4-trimethylsilacyclopentane for five seconds, followed by a 30 s purge. Subsequently, the substrate was exposed to an alternating pulse sequence of 0.1 seconds diethylzinc, 5 second purge, 0.1 seconds water, and 5 second purge, repeated 50 times. Film growth began on the forty-fourth cycle and remained below 1 angstrom per cycle until the final cycle.
The following Table 1 summarizes the steps performed in Examples 1 and 2; Step 2 is omitted in Comparative Examples 1 and 2. The thickness v. time data for the films prepared in Examples 1 and 2 and Comparative Examples 1 and 2 are shown in
It is observed that without the application of heteroatom silacyclic compound, growth on a non-metallic oxide surface begins immediately, while growth on copper metal is slow for about 30 cycles, before ALD-like deposition of metal oxide initiates. The thickness gap between the growth on the non-metallic and metallic surface is insufficient for most ASD DoD schemes and the slow growth observed on copper during the first thirty cycles would require further process steps to clean or mitigate. In contrast, the application of a heteroatom silacyclic compound before the start of the metal oxide deposition process results in both a larger thickness gap between the two surfaces and no sign of metal oxide growth on copper for over forty cycles. This affords a >7 nm thick ASD DoD layer on the non-metallic surface while retaining a metallic surface without deposited metal oxide or dielectric film. This thickness is sufficient for FSAV schemes.
It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.
This application claims priority to U.S. Provisional Patent Application No. 63/333,286, filed Apr. 21, 2022, the disclosure of which is herein incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63333286 | Apr 2022 | US |
