Patent Application
20230282514
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of a number of three-dimensional designs including, for example, Metal-Oxide-Silicon Field Effect Transistors (MOS-FET), Field Effect Transistors (FET), Fin Field Effect Transistor (FinFET), and Gate-All-Around (GAA) devices.
Integrated circuit (IC) manufacturing is typically divided into front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing. FEOL processes generally encompass those processes related to fabricating functional elements, such as transistors and resistors, in or on a semiconductor substrate. For example, FEOL processes typically include forming isolation features, gate structures, and source and drain features (also referred to as source/drain or S/D features). BEOL processes generally encompass those processes related to fabricating a multilayer interconnect (MLI) feature that interconnects the functional IC elements and structures fabricated during FEOL processing to provide connection to and enable operation of the resulting IC devices.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. The drawings are not to scale, and the relative sizing and placement of structures have been modified for clarity rather than dimensional accuracy. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure.
These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “vertical,” “horizontal,” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the Figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. The apparatus and structures may be otherwise oriented (rotated by, for example, 90°, 180°, or mirrored about a horizontal or vertical axis) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The structures and methods detailed below relate generally to the structures, designs, and manufacturing methods for IC devices include a multilevel interconnect (MLI) structure that allows for reduced spacing between conductive elements including, for example, contacts, a plurality of conductive metal patterns, and vias providing conductive connections between adjacent conductive metal patterns. Although the structures and methods will be discussed in terms of field effect transistor (FET) devices, the structures and methods are not so limited and are suitable for inclusion in manufacturing processes for other classes and configurations of IC devices including, without limitation, bulk semiconductor devices and silicon-on-insulator (SOI) devices, Metal-Oxide-Silicon Field Effect Transistors (MOS-FET) devices, Fin Field Effect Transistor (FinFET) devices, and Gate-All-Around (GAA) devices.
As IC technologies progress towards smaller technology nodes, BEOL processes are experiencing significant challenges. For example, advanced IC technology nodes incorporate more compact MLI features which, in turn, reduces the critical dimensions of interconnects of the MLI features (for example, widths, spacings, and/or heights of vias and/or conductive lines of the interconnection pattern layers). The reduced critical dimensions tend to increase interconnect resistance, which will tend to degrade IC device performance (e.g., by increasing resistance-capacitance (RC) delay), increase the risk of electromigration, and increase the risk of shorts between adjacent conductive elements. Accordingly, the various manufacturing processes used for forming MLI conductive patterns having reduced line widths and reduced line-to-line and/or end-to-end spacing becomes more challenging.
As feature areas continue to shrink, the physical alignment of successive layers and elements and maintaining the electrical isolation of separate elements represents significant challenges. Area-selective deposition (ASD) operations (or processes) provide a way for producing IC devices exhibiting increased metal and via structure densities that are achieved during back-end-of-line (BEOL) processing while simultaneously eliminating one or more photolithography operations and/or etching processes, which reduces manufacturing time, manufacturing cost, and manufacturing error. In some embodiments, an ASD operation provides the selective deposition of one or more conductive material(s) on the exposed conductive material surfaces, e.g., the terminal portions of adjacent conductive lines, contacts, vias, or other conductive elements or materials, while simultaneously suppressing or eliminating deposition of the conductive material(s) on the exposed surface of the dielectric material(s) that separate and electrically isolate the adjacent conductive structures or elements. In some embodiments, an ASD operation provides the selective deposition of one or more insulating material(s) on the exposed insulating surfaces, e.g., exposed portions of dielectric materials (including interlayer dielectric (ILD) and intermetal dielectric (IMD) layers) located between portions of adjacent conductive lines, while simultaneously suppressing or eliminating deposition of the insulating material(s) on the exposed surface of the conductive material(s). In some embodiments, ASD operations are used in different operations to provide the selective deposition of one or more conductive material(s) on the exposed metal surfaces and to provide the selective deposition of one or more insulating material(s) on the exposed dielectric surfaces. The ASD operations provide advantages over non-area selective metal deposition processes (e.g., blanket metal depositions) by confining the metal growth to certain target regions, thereby avoiding the need to remove the unwanted metal and risk of misalignment in the metal etch pattern and/or etch damage or particulate contamination that associated with the non-selective metal deposition based metal processes.
The ASD operations allows the via structures to be positioned on the terminal portions of the conductive lines, i.e., at a zero-offset position relative to the end of the conductive lines, thereby providing increased flexibility for via spacing that corresponding to the same end-to-end (E2E) spacing rules applied to adjacent and coaxial and/or parallel conductive lines. The E2E spacing rules are design specifications to account for inherent errors during manufacturing of semiconductor devices in order to reliably produce a functioning semiconductor device. The zero-offset positioning of the via structures also allows for decreased spacing between the edges of adjacent parallel conductive lines to achieve the same E2E spacing. The ability to manufacture and maintain reduced via structure spacing also provides for increased via/metal density because successive metal patterns are not required to correspond to via patterns that reflect non-zero process tolerance offsets (i.e., a portion of the underlying metal pattern is no longer designed to extend beyond the end of the via) from the E2E spacing utilized in earlier manufacturing processes.
As feature areas shrink to less than 100 nm, the physical alignment and overlay of multiple features and line edges become more challenging. The use of ASD operations provides improved alignment and overlay for nanoscale patterning, thereby providing for improved via and metal pattern densities in the MLI structures with reduced edge placement error (EPE). In some embodiments, this improved via and metal pattern densities results in IC devices having similar functionality, decreased chip area, and improved performance in comparison with other approaches. In some embodiments, simulations indicate that the IC devices manufactured in this manner exhibit at least 4% area gain in block level, meaning that the same IC device is able to be manufactured 4% smaller than other approaches.
In some embodiments, the ASD operation also eliminates processing operations associated with a via patterning operation, a via etch operation, and a via metal deposition operation, thereby reducing the risk of introduction of defects associated with such operations and will tend to increase manufacturing yield and lifetime performance of the IC device. In some embodiments, a via patterning operation is included, but the ASD operation allows for increased dimensional tolerances within the pattern, e.g., terminal portions of adjacent conductive and coaxial lines are exposed in a single opening, thereby decreasing the likelihood of patterning defects by allowing for a larger opening and increased tolerance for placement of the opening relative to underlying conductive pattern layers. In some embodiments, ASD operations are used on multiple levels of vias and metal patterns, thereby eliminating additional patterning operations and reducing the manufacturing steps for producing a functional integrated circuit (IC) device.
In some embodiments, the ASD operation is a combination of a self-assembled monolayer (SAM) passivation operation applied to the non-growth regions of the IC device coupled with an atomic layer deposition (ALD) operation applied to the growth regions of the IC device. This combination and sequence SAM and ALD operations are then repeated for a number of cycles sufficient to deposit a target thickness of material on the growth regions.
In some embodiments, the ASD operation also integrates a thermal atomic layer etching (ALE) operation for removing unwanted nuclei (e.g., metal, or other conductive atoms, or conductive compounds) from the non-growth regions of the IC device before the growth cycle of the ALD process commences. In this manner, the deposition of conductive material(s) on the non-growth region, e.g., the dielectric surface between the end of two coaxial conductive lines, is able to be suppressed or eliminated while during the same operation successive layers of the conductive materials are deposited on the adjacent terminal portions of the conductive lines to form the desired conductive structures, e.g., zero-offset via structures.
As detailed above, in some embodiments, the ASD operation comprises a metal-on-metal (MoM) operation in which successive cycles of the ASD operation deposit a series of layers of metal (or other conductive material(s)) on exposed metal surfaces, e.g., depositing via structures on the terminal portions of conductive lines, while avoiding deposition of the metal or other conductive materials on adjacent dielectric surfaces. In some embodiments, the ASD operation comprises a dielectric-on-dielectric (DoD) operation in which successive cycles of the ASD operation deposit a series of layers of dielectric material(s) on exposed dielectric surfaces, e.g., depositing dielectric material on the exposed surface of a dielectric material separating the terminal portions of adjacent conductive lines, while simultaneously avoiding deposition of the dielectric material(s) on the exposed terminal portions of the conductive lines.
In some embodiments, each of the thickness values for the vias 218, a lower portion of Mx+1 metal pattern 220, and an upper portion of the Mx+1 metal pattern 222 falls within 100-200% of a minimum thickness value target. In some embodiments, each of the thickness values 218, 220, 222 independently fall within a range of 10-20 nm. If the thickness values 218, 220, 222 are less than about 10 nm, the resistance of the resulting structure will increase and will tend to degrade the IC device performance and/or lifetime, in some instances. If the thickness values 218, 220, 222 are greater than about 20 nm, additional ASD processing time will be used to obtain the increased thickness without a commensurate improvement in the performance or lifetime of the resulting IC device, thereby increasing cycle time and reducing IC device output, in some instances.
In some embodiments, each level of the MLI structure manufactured during BEOL operations utilizes MoM ASD operations for forming via and metal pattern structures and thereby improving alignment between sequentially formed BEOL elements and providing for increased via and metal pattern density in comparison with other approaches.
In some embodiments higher tilt angles are used to form large tilt angle implanted drain (LATID) and/or large tilt angle implanted punch-through stopper (LATIPS) structures. In
According to some embodiments, the method of
In some embodiments, the Mx metal pattern, the via pattern, and the Mx+1 pattern each independently comprise a conductive material such as a metal, a metal alloy, or a metal silicide. In some embodiments, the conductive material will include various combinations of materials to enhance the device performance and/or device longevity including, for example, a liner layer, a wetting layer, an adhesion layer, a metal fill layer, and/or one or more other suitable layers. In some embodiments, the primary conductive material will be selected from Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable conductive materials, and combinations and alloys thereof.
In some embodiments, the dielectric materials will be deposited using materials having a high dielectric constant (k value), e.g., κ > 3.9. In some embodiments, the high-k dielectric material includes one or more of HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, SiOxNy, and combinations thereof, or another suitable material. The high-k dielectric materials may be formed by ALD, physical vapor deposition (PVD), chemical vapor deposition CVD, plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, and/or one or more other suitable method(s).
According to some embodiments, the method of
In operation 1404 the exposed portions of the Mx metal pattern are utilized as the base for further processing using a MoM ASD to form a plurality of via structures. Using the ASD process allows the via structures to be precisely aligned with the Mx metal pattern because the growth of the via structures is limited to those exposed portions of the Mx metal pattern. By using the ASD process, the manufacturer avoids using a more traditional damascene process in which a substantial amount of material must be deposited and removed in order to obtain the via pattern.
In operation 1406 the first mask pattern is removed to expose a plurality of via structures that, in some embodiments, extended above the surrounding via mask pattern. Once the via mask pattern is removed, a dielectric layer, e.g., a layer of a low-κ dielectric material, will then be formed on the wafer and then planarized using, for example, etchback or CMP processes, to remove the excess material and provide a substantially more planar surface for subsequent processing.
In operation 1408 a second mask pattern is formed to expose portions of the Mx metal pattern and an intervening region of the planarized ILD layer.
In operation 1410 a DoD ASD process is utilized to raise a dielectric structure that is precisely aligned with exposed portion(s) of the underlying ILD pattern on the wafer. In some embodiments, the height of the dielectric structure will exceed a plane defined by the upper surface of the second mask pattern.
In operation 1412, the second mask pattern is modified or, in some embodiments, removed and another mask layer deposited, to form a third mask pattern. The third mask pattern is configured to expose more of the wafer surface surrounding the dielectric structure and corresponds to a Mx+1 metal pattern.
In operation 1414 the Mx+1 metal layer is formed on the third mask pattern and planarized to form the Mx+1 metal pattern. In some embodiments, the third mask pattern is then removed and an additional ILD material layer is formed on the wafer. In some embodiments, the wafer is then planarized to define a wafer surface comprising the upper surfaces of the Mx+1 metal pattern and the dielectric material insulating the various conductive elements of the Mx+1 metal pattern from each other.
In optional operation 1416 the planarized wafer comprising an aligned Mx metal pattern/via stack and a Mx+1 metal pattern is transferred to additional BEOL operations to complete the manufacture of the IC device.
In operation 1504 the exposed portions of the Mx metal pattern are utilized as the base for further processing using a MoM ASD to form a plurality of via structures. Using the ASD process allows the via structures to be precisely aligned with the Mx metal pattern because the growth of the via structures is limited to those exposed portions of the Mx metal pattern. By using the ASD process, the manufacturer avoids using a more traditional damascene process in which a substantial amount of material must be deposited and removed in order to obtain the via pattern.
In operation 1506 the first mask pattern is removed, an ILD layer is formed on the wafer and the wafer is planarized to provide a wafer surface with top surfaces of the via structures exposed and separated from each other by the ILD.
In operation 1508 a second mask pattern is formed on the wafer to expose the top surfaces of the via structures and portions of the top surface of the ILD layer. A MoM ASD process is then used to form a first portion of the Mx+1 metal pattern extending upwardly from the exposed surfaces of the via structure.
In optional operation 1510 the first Mx+1 metal pattern is used as an implant mask during a tilt angle implant to form an implant exclusion zone that extends between adjacent portions of the Mx+1 metal pattern. During the implant operation the first Mx+1 metal pattern “shadows” the implant exclusion zone from the beam of ions being directed at the wafer surface at a non-zero “tilt” angle. Depending on the implant species, the implant energy, and the implant dosage, in some embodiments surface portions of the ILD layer that are exposed by the second mask pattern and not within the implant exclusion zone will exhibit altered electrical properties and/or become more or less receptive to a subsequent ASD process.
In optional operation 1512 the configuration of the Mx+1 metal pattern is altered using a MoM ASD process to increase the width and/or thickness of the Mx+1 metal pattern through the addition of a second portion of the Mx+1 metal pattern. In some embodiments the ILD surface adjacent the first portion of the Mx+1 metal pattern will have been modified during the tilt angle implant to become more receptive to the application of conductive materials using the ASD process. In some embodiments, the conditions of the ASD process are altered to provide for application of conductive materials to both the conductive and dielectric surfaces exposed by the second mask pattern.
In operation 1514 the second mask pattern is removed and an additional ILD material layer is formed on the wafer. In some embodiments, the wafer is then planarized to define a wafer surface comprising the upper surfaces of the Mx+1 metal pattern and the dielectric material insulating the various conductive elements of the Mx+1 metal pattern from each other.
In optional operation 1516 the planarized wafer comprising an aligned Mx metal pattern/via/Mx+1 metal pattern stack is transferred to additional BEOL operations to complete the manufacture of the IC device.
In operation 1604, the exposed portions of the Mx metal pattern are utilized as the base for further processing using a MoM ASD to form a plurality of via structures. Using the ASD process allows the via structures to be precisely aligned with the Mx metal pattern because the growth of the via structures is limited to those exposed portions of the Mx metal pattern. By using the ASD process, the manufacturer avoids using a more traditional damascene process in which a substantial amount of material must be deposited and removed in order to obtain the via pattern.
Alternatively, in operation 1604′ a dielectric layer is formed on the wafer and a via pattern is opened in the dielectric layer. The conductive material layer from which the vias are formed is then deposited on the via pattern and the wafer is planarized to separate the via pattern structures from the overlying conductive material. In operation 1605′ a cut metal pattern is formed to expose those portions of the via pattern structures that are to be removed during the cut metal etch. An etch process is then used to remove the exposed portions of the via pattern structures.
After completion of operation 1604 or 1605′ operation 1606 is conducted during with the hard and/or soft masks are removed from the wafer, an ILD layer is deposited on the wafer, and the wafer is planarized to expose the upper surfaces of the vias in preparation for the next operation.
In operation 1608 a Mx+1 metal pattern is formed using a MoM ASD process whereby the Mx+1 metal pattern is selectively formed on the exposed upper surfaces of the vias.
Alternatively, in operation 1608′ an ILD layer is deposited, patterned, and etched to form a Mx+1 metal pattern. A Mx+1 metal layer is then deposited on the etched ILD layer and an upper portion is removed to complete the initial Mx+1 metal pattern. In operation 1609′ a cut metal pattern is formed to expose those portions of the Mx+1 metal pattern structures that are to be removed during the cut metal etch. An etch process is then used to remove the exposed portions of the Mx+1 metal pattern to, for example, define a plurality of distinct conductive nets on the wafer.
After completion of operation 1608 or 1609′, in optional operation 1610 the planarized wafer comprising an aligned Mx metal pattern/via/Mx+1 metal pattern stack is transferred to additional BEOL operations to complete the manufacture of the IC device.
The disclosed methods and structures provide an improved solution for BEOL landing issues associated with the formation of a Mx metal pattern 202, a via 204 pattern Vx corresponding and providing electrical connection to the first metal pattern, and a Mx+1 metal pattern 208 corresponding to the via pattern and providing electrical connection, through the vias, to the first metal pattern. In some embodiments, a MoM ASD operation allows for a reduced via 204 Vx minimum pitch and allows for a complete, zero-offset, landing on the terminal portions of the Mx metal pattern 202 while maintaining a minimum or close to minimum allowable E2E spacing between adjacent terminal elements of the Mx+1 metal pattern 208.
In some embodiments, combining the ASD operation with an ion metal plasma (IMP) operation provides a no cut and zero enclosure process for applying the second metal layer Mx+1 to the underlying via pattern Vx. In some embodiments, the combination of a low-κ dielectric layer 203′ (LK) and ASD operations provides for a cut metal Mx+1 pattern that provides for zero-offset enclosure and freedom of Mx+1 length feature. In some embodiments, the ASD operation(s) provide for a reduced series of operations for achieving improved conductive structures when compared to photolithography-based methods and/or self-aligned contact (SAC) based methods.
In some embodiments, EPC system 1700 is a general purpose computing device including a hardware processor 1702 and a non-transitory, computer-readable, storage medium 1704. Computer-readable storage medium 1704, amongst other things, is encoded with, i.e., stores, computer program code (or instructions) 1706, i.e., a set of executable instructions. Execution of computer program code 1706 by hardware processor 1702 represents (at least in part) an EPC tool which implements a portion or all of, e.g., the methods described herein in accordance with one or more (hereinafter, the noted processes and/or methods).
Hardware processor 1702 is electrically coupled to computer-readable storage medium 1704 via a bus 1718. Hardware processor 1702 is also electrically coupled to an I/O interface 1712 by bus 1718. A network interface 1714 is also electrically connected to hardware processor 1702 via bus 1718. Network interface 1714 is connected to a network 1716, so that hardware processor 1702 and computer-readable storage medium 1704 are capable of connecting to external elements via network 1716. Hardware processor 1702 is configured to execute computer program code 1706 encoded in computer-readable storage medium 1704 in order to cause the EPC system 1700 to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, hardware processor 1702 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.
In one or more embodiments, computer-readable storage medium 1704 is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium 1704 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium 1704 includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).
In one or more embodiments, computer-readable storage medium 1704 stores computer program code 1706 configured to cause the EPC system 1700 (where such execution represents (at least in part) the EPC tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium 1704 also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium 1704 stores process control data 1708 including, in some embodiments, control algorithms, process variables and constants, target ranges, set points, programming control data, and code for enabling statistical process control (SPC) and/or model predictive control (MPC) based control of the various processes.
EPC system 1700 includes I/O interface 1712. I/O interface 1712 is coupled to external circuitry. In one or more embodiments, I/O interface 1712 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to hardware processor 1702.
EPC system 1700 also includes network interface 1714 coupled to hardware processor 1702. Network interface 1714 allows EPC system 1700 to communicate with network 1716, to which one or more other computer systems are connected. Network interface 1714 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EPC systems 1700.
EPC system 1700 is configured to send information to and receive information from fabrication tools 1720 that include one or more of ion implant tools, etching tools, deposition tools, coating tools, rinsing tools, cleaning tools, chemical-mechanical planarizing (CMP) tools, testing tools, inspection tools, transport system tools, and thermal processing tools that will perform a predetermined series of manufacturing operations to produce the desired integrated circuit devices. The information includes one or more of operational data, parametric data, test data, and functional data used for controlling, monitoring, and/or evaluating the execution, progress, and/or completion of the specific manufacturing process. The process tool information is stored in and/or retrieved from computer-readable storage medium 1704.
EPC system 1700 is configured to receive information through I/O interface 1712. The information received through I/O interface 1712 includes one or more of instructions, data, programming data, design rules that specify, e.g., layer thicknesses, spacing distances, structure and layer resistivity, and feature sizes, process performance histories, target ranges, set points, and/or other parameters for processing by hardware processor 1702. The information is transferred to hardware processor 1702 via bus 1718. EPC system 1700 is configured to receive information related to a user interface (UI) through I/O interface 1712. The information is stored in computer-readable medium 1704 as user interface (UI) 1710.
In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EPC tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EPC system 1700.
In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.
In
The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house 1820, mask house 1830, and IC Fab 1850 is owned by a single larger company. In some embodiments, two or more of design house 1820, mask house 1830, and IC Fab 1850 coexist in a common facility and use common resources.
Design house (or design team) 1820 generates an IC design layout diagram 1822. IC design layout diagram 1822 includes various geometrical patterns designed for an IC device 1860. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device 1860 to be fabricated. The various layers combine to form various IC features.
For example, a portion of IC design layout diagram 1822 includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an intermetal interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house 1820 implements a proper design procedure to form IC design layout diagram 1822. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram 1822 is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram 1822, in some operations, will be expressed in a GDSII file format or DFII file format.
Whereas the pattern of a modified IC design layout diagram is adjusted by an appropriate method in order to, for example, reduce parasitic capacitance of the integrated circuit as compared to an unmodified IC design layout diagram, the modified IC design layout diagram reflects the results of changing positions of conductive line in the layout diagram, and, in some embodiments, inserting to the IC design layout diagram, features associated with capacitive isolation structures to further reduce parasitic capacitance, as compared to IC structures having the modified IC design layout diagram without features for forming capacitive isolation structures located therein.
Mask house 1830 includes mask data preparation 1832 and mask fabrication 1844. Mask house 1830 uses IC design layout diagram 1822 to manufacture one or more masks 1845 to be used for fabricating the various layers of IC device 1860 according to IC design layout diagram 1822. Mask house 1830 performs mask data preparation 1832, where IC design layout diagram 1822 is translated into a representative data file (“RDF”). Mask data preparation 1832 provides the RDF to mask fabrication 1844. Mask fabrication 1844 includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) 1845 or a semiconductor wafer 1853. The IC design layout diagram 1822 is manipulated by mask data preparation 1832 to comply with particular characteristics of the mask writer and/or requirements of IC Fab 1850. In
In some embodiments, mask data preparation 1832 includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that are known to arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram 1822. In some embodiments, mask data preparation 1832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.
In some embodiments, mask data preparation 1832 includes a mask rule checker (MRC) that checks the IC design layout diagram 1822 that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 1822 to compensate for limitations during mask fabrication 1844, which may undo part of the modifications performed by OPC in order to meet mask creation rules.
In some embodiments, mask data preparation 1832 includes lithography process checking (LPC) that simulates processing that will be implemented by IC Fab 1850 to fabricate IC device 1860. LPC simulates this processing based on IC design layout diagram 1822 to create a simulated manufactured device, such as IC device 1860. In some embodiments, the processing parameters in LPC simulation will include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram 1822.
It should be understood that the above description of mask data preparation 1832 has been simplified for the purposes of clarity. In some embodiments, mask data preparation 1832 includes additional features such as a logic operation (LOP) to modify the IC design layout diagram 1822 according to manufacturing rules. Additionally, the processes applied to IC design layout diagram 1822 during mask data preparation 1832 may be executed in a variety of different orders.
After mask data preparation 1832 and during mask fabrication 1844, a mask 1845 or a group of masks 1845 are fabricated based on the modified IC design layout diagram 1822. In some embodiments, mask fabrication 1844 includes performing one or more lithographic exposures based on IC design layout diagram 1822. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) 1845 based on the modified IC design layout diagram 1822. Mask 1845will be formed using a process selected from various available technologies. In some embodiments, mask 1845 is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask 1845 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask.
In another example, mask 1845 is formed using a phase shift technology. In a phase shift mask (PSM) version of mask 1845, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask will be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 1844 is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer 1853, in an etching process to form various etching regions in semiconductor wafer 1853, and/or in other suitable processes.
IC Fab 1850 includes wafer fabrication 1852. IC Fab 1850 is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab 1850 is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.
Wafer fabrication 1852 includes forming a patterned layer of mask material formed on a semiconductor substrate is made of a mask material that includes one or more layers of photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4, SiON, SiC, SiOC), or combinations thereof. In some embodiments, masks 1845 include a single layer of mask material. In some embodiments, a mask 1845 includes multiple layers of mask materials.
In some embodiments IC Fab 1855 includes wafer fabrication 1857. IC Fab 1855 is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab 1855 is a manufacturing facility provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication) to add one or more metallization layers to wafer 1859, and a third manufacturing facility (not shown) may provide other services for the foundry business such as packaging and labelling.
In some embodiments, the mask material is patterned by exposure to an illumination source. In some embodiments, the illumination source is an electron beam source. In some embodiments, the illumination source is a lamp that emits light. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the illumination source emits a combination of different (UV, visible, and/or infrared) light.
In some embodiments, etching processes include presenting the exposed structures in the functional area(s) to an oxygen-containing atmosphere to oxidize an outer portion of the exposed structures, followed by a chemical trimming process such as plasma-etching or liquid chemical etching, as described above, to remove the oxidized material and leave behind a modified structure. In some embodiments, oxidation followed by chemical trimming is performed to provide greater dimensional selectivity to the exposed material and to reduce a likelihood of accidental material removal during a manufacturing process. In some embodiments, the exposed structures may include the fin structures of Fin Field Effect Transistors (FinFET) with the fins being embedded in a dielectric support medium covering the sides of the fins. In some embodiments, the exposed portions of the fins of the functional area are top surfaces and sides of the fins that are above a top surface of the dielectric support medium, where the top surface of the dielectric support medium has been recessed to a level below the top surface of the fins, but still covering a lower portion of the sides of the fins.
Subsequent to mask patterning operations, areas not covered by the mask are etched to modify a dimension of one or more structures within the exposed area(s). In some embodiments, the etching is performed using plasma etching, reactive ion etching (RIE), or a liquid chemical etch solution, according to some embodiments. The chemistry of the liquid chemical etch solution includes one or more of etchants such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F) potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), TMAH (tetramethylammonium hydroxide), or a combination thereof.
In some embodiments, the etching process is a dry-etch or plasma etch process. Plasma etching of a substrate material is performed using halogen-containing reactive gasses excited by an electromagnetic field to dissociate into ions. Reactive or etchant gases include, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or a combination thereof, although other semiconductor-material etchant gases are also envisioned within the scope of the present disclosure. Ions are accelerated to strike exposed material by alternating electromagnetic fields or by fixed bias according to methods of plasma etching that are known in the art.
In some embodiments, molecular level processing technologies that share the self-limiting surface reaction characteristics utilized in ALD including, for example, Molecular Layer Deposition (MLD) and Self-Assembled Monolayers (SAM). MLD utilizes successive precursor-surface reactions in which a precursor is introduced into a reaction zone above the wafer surface. The precursor adsorbs to the wafer surface where it is confined by physisorption. The precursor then undergoes a quick chemisorption reaction with a number of active surface sites, leading to the self-limiting formation of molecular attachments in specific assemblies or regularly recurring structures. These MLD structures will be formed successfully using lower process temperatures than some traditional deposition techniques.
SAM is a deposition technique that involves the spontaneous adherence of organized organic structures on a wafer surface. This adherence involves adsorption of the organic structures from the vapor or liquid phase utilizing relatively weak interactions with the wafer surface. Initially, the structures are adsorbed on the surface by physisorption through, for instance, van der Waals forces or polar interactions. The self-assembled monolayers will then become confined to the surface by a chemisorption process. In some embodiments, the ability of SAM to grow layers as thin as a single molecule through chemisorption-driven interactions with the wafer surface(s) will be particularly useful in forming thin films including, for example, “near-zero-thickness” activation or barrier layers. SAM will also be particularly useful in area-selective deposition (ASD) (or area-specific deposition) using molecules that exhibit preferential reactions with specific segments of the underlying wafer surface in order to facilitate or obstruct subsequent material growth in the targeted areas. In some embodiments, SAM is used to form a foundation or blueprint region for subsequent area-selective ALD (AS-ALD) or area-selective CVD (AS-CVD).
The ALD, MLD, and SAM processes represent viable options for manufacturing thin layers (in some embodiments, the manufactured layers are only few atoms thick) that exhibit sufficient uniformity, conformality, and/or purity for the intended IC device application. By delivering the constituents of the material systems being manufactured both individually and sequentially into the processing environment, these processes and the precise control of the resulting surface chemical reactions allow for excellent control of processing parameters and the target composition and performance of the resulting film(s).
According to some embodiments methods for manufacturing an integrated circuit device include the operations of depositing a first metal pattern on a semiconductor substrate, depositing a first via on a first portion of a first conductive line of the first metal pattern using an area selective deposition, depositing a second via on a second portion of an adjacent second conductive line of the first metal pattern using the area selective deposition, the first and second vias being formed simultaneously and separated by a first region of dielectric material, wherein the first and second vias are separated by a minimum edge-to-edge spacing, and depositing a first portion of a second metal pattern on the first and second vias using a second area selective deposition to form a first metal pattern/via/second metal stack with no edge offset.
Some embodiments of the methods for manufacturing integrated circuit device also include one or more additional operations including, for example, depositing a first mask pattern that exposes surface portions of the first and second vias, performing a tilt angle implant on the semiconductor substrate, wherein adjacent portions of the second metal pattern define an implant exclusion region between the adjacent portions of the second metal pattern, forming a second portion of the second metal pattern using a third area selective deposition, forming a second portion of the second metal pattern using a non-area selective metal deposition, forming a second portion of the second metal pattern using a non-area selective metal deposition, forming a cut metal pattern to expose a target region of the second metal pattern, and removing the target region from the second metal pattern, forming the first via and the second via with an end-to-end spacing no greater than 150% of a minimum end-to-end spacing permitted by an end-to-end spacing rule for design of the integrated circuit device, forming the first via and the second via with an end-to-end spacing no greater than 20 nm, and/or forming a first mask pattern on the first metal pattern, wherein the first mask pattern exposes the first portion on the first conductive line and the second portion of the second conductive line in a single opening, and forming the first via and the second via to have a substantially trapezoidal edge configuration.
According to some embodiments methods for manufacturing an integrated circuit device include the operations of forming a first conductive line having a first end over a semiconductor substrate, forming a second conductive line having a second end over the semiconductor substrate, wherein the first end and the second end are separated by a dielectric material, forming a mask pattern over the first conductive line and the second conductive line, the mask pattern exposing the first conductive line, the second conductive line and the dielectric material, and performing a first area selective deposition (ASD) of conductive material on only the exposed portions of the first and second conductive lines to form only a first via on the first conductive line adjacent the first end, and a second via on the second conductive line adjacent the second end.
Some embodiments of the methods for manufacturing integrated circuit device also include one or more additional operations including, for example, aligning a first wall of the first via with a first wall of the first end, aligning a first wall of the second via with a first wall of the second end, aligning the first via with the first conductive line and aligning the second via with the second conductive line to form conductive line/via zero enclosure assemblies, depositing a dielectric material over the first and second vias and planarizing the dielectric material to expose upper surfaces of the first and second vias and a portion of the dielectric material separating the first and second vias, forming a second mask pattern that exposes portions of the upper surfaces of the first and second vias and the dielectric material separating the first and second vias, performing a second area selective deposition (ASD) of dielectric material to form a dielectric structure, forming a third mask pattern that exposes the dielectric structure and portions of the upper surfaces of the first and second vias, forming a metal layer over the semiconductor substrate, planarizing the metal layer to remove an upper portion of the metal layer and form a metal pattern over the first and second vias, forming a cut metal pattern over the metal pattern to expose a portion of the metal pattern between the first and second vias and/or removing the exposed portion of the metal pattern from between adjacent first and second vias.
According to some embodiments an integrated circuit device includes structures including a first metal pattern having a first metal sidewall, a first via having a first via sidewall over a first portion of the first metal pattern, a second metal pattern having a second metal sidewall over the first and second vias, wherein the first metal sidewall, the first via sidewall, and the second metal sidewall are aligned to form a zero enclosure conductive stack.
Some embodiments of an integrated circuit device also include one or more additional structures including, for example, a second via adjacent the first via wherein the first and second vias are separated by a distance corresponding to a minimum end-to-end spacing permitted by a spacing rule for design of the integrated circuit device, a second via adjacent the first via wherein the first and second vias are separated by a distance not greater than 20 nm, a third via separated from both the first and second vias by a distance not less than a one pattern/one etch (1P1E) extreme ultraviolet (EUV) pitch permitted by a spacing rule for design of the integrated circuit device, and/or first and second vias having a trapezoidal perimeter profile including a major base, a minor base, and two non-parallel legs, wherein the first and second vias are oriented with the major base of the first via opposite the major base of the second via.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of some embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
The present application claims the priority of U.S. Provisional Application No. 63/316,721, filed Mar. 4, 2022, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63316721 | Mar 2022 | US |
