Patent Application
20050007170
The present application claims priority from Japanese application JP 2003-272549 filed on Jul. 9, 2003, and Japanese application JP 2004-131238 filed on Apr. 27, 2004, the contents of which are hereby incorporated by reference into this application.
The present invention relates to an asynchronous control circuit and a semiconductor integrated circuit device and, for instance, to an effective method for use in circuit control technology accessing asynchronously a 1 port memory circuit from a plurality of ports.
The area of a multi-port SRAM (static type random access memory) becomes very large compared to a 1 port SRAM because each port in the memory cell needs an access transistor, word line and bit line. Then, U.S. Pat. No. 6,625,686 (JP-A 57775/2000) proposed that a synchronous pseudo-multiport SRAM in which the function of an N port memory is artificially achieved by accessing the 1 port SRAM core N times. On the other hand, U.S. Pat. No. 6,078,527 (JP-A 30460/2000) proposed an asynchronous type dual port SRAM in which each of the two ports uses a different clock, and the timing between the clocks was selected to be arbitrary.
As described above, the multi-port SRAM needs the same number of access transistors as number of ports in a memory cell; therefore, its area becomes larger than that of a 1 port SRAM. Additionally, design man-hours are not much different from designing a totally different memory core. On the other hand, in a synchronous pseudo-multiport SRAM disclosed in patent document 1, because it is one in which a common clock is used between ports, it is impossible to achieve asynchronous operation between the ports, such as accessing memory with a clock of a different frequency for each port. In an asynchronous type dual port SRAM disclosed in patent document 2, because a phase-comparison circuit is used to select which of two ports demands early memory access, the number of ports is limited, and it is impossible to achieve asynchronous operation with three, four, or more ports.
It is an object of the present invention to provide an asynchronous control circuit and a semiconductor integrated circuit device containing it. It is another object of the present invention to provide an asynchronous control circuit which is convenient to use and can be built in a signal processing system with flexibility. Also an object of the invention is to provide a semiconductor integrated circuit device comprising a synchronizing circuit which aims at speeding-up and can form a logic output without metastable states. The aforementioned and other objects and new features of the invention will be apparent from the following description and accompanying drawings of the specification.
An outline of the representative items of the inventions disclosed in this patent will be briefly described as follows. That is,
An asynchronous control circuit and memory circuit is installed in a semiconductor integrated circuit, wherein the above-mentioned asynchronous control circuit activates according to at least one access request by acknowledging a plurality of access request signals generated asynchronously from each other and a plurality of input signals corresponding to each of the above-mentioned plurality of access request signals, one access request is selected from one or more access requests in the activation state, the input signal corresponding to it is acknowledged, the proper input signal is transmitted to the above-mentioned memory circuit, and the input signal corresponding to the unexecuted access request is acknowledged after the end of operation corresponding to the proper input signal.
As a synchronizing circuit formed on a semiconductor integrated circuit, it is set so that a pair of output signals of a first latch circuit acknowledging the asynchronous input signal and clock signal have an offset voltage in the metastable state; the offset voltage of the above-mentioned output signal is amplified by an amplifier circuit operated by the delay signal of the above-mentioned clock signal, and the output signal synchronized by the above-mentioned clock signal is obtained.
A small area and asynchronous control operation without regulating the number of ports can be achieved, and the chip performance can be improved. The design data for existing 1 port SRAMs, etc. can be used; thereby, the design man-hours can be reduced. A logic output signal can be formed, which makes it possible to speed-up and have no metastable states.
Here, the address signal (0:i) means i+1 bits from 0−i, and the data signal (0:j) means j+1 bits from 0−j. The above-mentioned clock CK1 or CKn is an access request signal when seen from the memory circuit side, for instance, a chip select signal CS and a chip enable signal CE are essentially regarded as the same as the above-mentioned clock CK in terms of circuit functionality.
In this embodiment, the clocks CK1-CKn are generated asynchronously. That is, they are timing signals of mutually different frequencies and phases, and the port number 1 or n is assumed to be a plural number of 3 or more; 3 or more clocks CK are input almost simultaneously or their phases are slightly different, and it is necessary to make it hazard-free to avoid malfunctions even for the variation of circuit devices within the asynchronous control circuit or deviations in signal propagation delay time, etc. Therefore, it is impossible to use the phase-comparison circuit as disclosed in the aforementioned patent document 2, so that it becomes necessary to develop a new asynchronous control circuit which satisfies the hazard-free requirement as mentioned above.
The example illustrated in
The above-mentioned asynchronous control circuit sends the execution request for memory access to the 1 port SRAM accepting clocks CK1-CKn, supplies a control signal for memory access corresponding to the above-mentioned execution request to the input latch & selector, and supplies one address signal A (0:i) and data D (0:j) selected by the selector to the 1 port SRAM. The 1 port SRAM selects the memory cell according to the above-mentioned address signal A (0:i) acknowledging the above-mentioned execution request, writes the data D (0:j) maintained in the above-mentioned input latch to the memory cell if it is a write operation, outputs the read data Q (0:j) of the selected memory cell to the above-mentioned output latch if it is a read operation, and communicates to the asynchronous control circuit the end of execution signal corresponding to completing the memory access in question. Thus, the asynchronous control circuit and the 1-port SRAM are coupled by a handshake protocol consisting of the execution request for memory access and the end of execution of the memory access corresponding thereto.
The asynchronous control circuit accepts the clock input which includes simultaneous input of more than two ports, and the input latch maintains the input signal, such as address and data, corresponding thereto. When the asynchronous control circuit accepts the aforementioned plurality of clock inputs, it selects one clock from them, and supplies the address, data A (0:i), and data D (0:j) maintained in the input latch to the above-mentioned 1 port SRAM by controlling the above-mentioned selector corresponding to the clock.
Although it is not shown in this figure, during write operation, write data Dn are maintained in the input latch D1 corresponding to the clock CK1, and write data Dm are maintained in the input latch D2 corresponding to the clock CK2.
When the two clocks CK1 and CK2 are input almost simultaneously, not deciding accurately the phase difference between the clocks CK1 and CK2, but selecting the clock CK1 according to a predetermined priority-rank and supplying the clock as an execution request to the clock terminal SRAM-CK of the 1 port SRAM. Port 1 of the input latch corresponding to the above-mentioned clock CK1 is selected by the above-mentioned asynchronous control circuit; the address signal An maintained in the aforementioned input latch A1 is given in the address terminal A1 of the 1 port SRAM, thereby, the selection operation of the memory cell is performed. When a read operation of the above-mentioned address signal An is directed, the 1 port SRAM selects a memory cell corresponding to the above-mentioned address signal An and outputs the read signal Qn to the output latch. After completing the operation of outputting the data Qn to the output latch like this, the end of execution (Done) signal corresponding to the above-mentioned execution request is signaled back to the asynchronous control circuit.
Because of the existence of unexecuted clock CK2, the asynchronous control circuit supplies an execution request to the clock terminal SRAM-CK of the 1 port SRAM corresponding thereto, as well as selects the port 2 of the input latch corresponding to the clock CK2 and supplies the address signal Am maintained in the above-mentioned input latch A2 to the address terminal A of the 1-port SRAM. The selection operation of a memory cell is performed at the 1 port SRAM corresponding to the above-mentioned address signal Am. When a read operation of the above-mentioned address signal Am is directed, the 1 port SRAM selects a memory cell corresponding to the above-mentioned address signal Am and outputs the read signal Qm to the output latch. After completing the operation of outputting the data Qm to the output latch, the end of execution (Done) signal corresponding to the above-mentioned execution request is signaled back to the asynchronous control circuit.
By adopting a pseudo-handshaking protocol, it is not necessary for the 1 port SRAM to provide a function for creating the end of execution signal for the handshaking protocol as shown in aforementioned
The output signals A and B of the above-mentioned flip-flop circuits FF1A and FF1B are transmitted to the combinatorial logic circuit constituting the event generating circuit. The above-mentioned event generating circuit forms an OR signal (A+B) from the output signals A and B of the above-mentioned flip-flop circuits FF1A and FF1B, and consists of NAND gate circuits G1, G2, and G3, although it is not limited thereto. This event generating circuit is transmitted to the register accepting an event and to the 1 port SRAM as the clock CK. The above-mentioned register consists of the SR (SET/RESET)-flip-flop circuit FF3.
Output signals A and B of flip-flop circuits FF1A and FF1B are respectively supplied to the inputs of one side of NAND gate circuits G1 and G2 consisting of the above-mentioned event generation circuit. The reversing output signal of flip-flop circuit FF3 which acknowledges the above-mentioned event is supplied to the inputs of the other side. That is, when the flip-flop circuit FF3 is set, the gate control signal which is supplied to the above-mentioned NAND gates G1 and G2 becomes a low level, and acknowledgement of the input is stopped.
In this embodiment, port A has a higher priority-rank versus port B. That is, the output signal of the above-mentioned event generating circuit is transmitted to the clock terminal ck of the flip-flop circuit FF2 constituting the register, and the output signal reversed by the gate circuit G1, which acknowledges the output signal A of the flip-flop circuit FF1A corresponding to the above-mentioned port A, is transmitted to the data terminal d. As a result, the SET/RESET of the flip-flop circuit FF1A through the gate circuit G1 is decided when an event is generated, and port A is selected if the flip-flop circuit FF1A is in the SET state. On the other hand, if the flip-flop circuit FF1A is in the RESET state, port B is selected. That is, port B is selected only when clock CKA is not input from port A.
The output signal P and the reversing signal of the above-mentioned flip-flop circuit FF2 are supplied to one of the inputs of the NAND gate circuits G4 and G5 consisting of the priority encoder. The output signal E of the flip-flop circuit FF3, which is a register accepting the above-mentioned event, is supplied to the other input of these gate circuits G4 and G5. The output signal P of the above-mentioned flip-flop circuit FF2 is transmitted as a port selection signal CP to an input latch not shown in the figure. For instance, in contrast with the control signal shown in
The output of the above-mentioned gate circuit G4 is reversed by the inverter circuit IV1, and input into the reset terminal R of the above-mentioned flip-flop circuit FF1B. The output signal of the above-mentioned gate circuit G5 is reversed by the inverter circuit IV2, and input into the reset terminal R of the above-mentioned flip-flop circuit FF1A. As mentioned above, when the output signal P of the flip-flop circuit FF2 is low-level, the end of acknowledgement is shown by selecting port A, and the flip-flop circuit FF1A corresponding thereto is reset by the output signal of the above-mentioned gate circuit G5, thereby, the acknowledgement following is enabled. On the other hand, when the output signal P of the flip-flop circuit FF2 is high-level, the end of acknowledgement is shown by selecting the port B, and the flip-flop circuit FF1B corresponding thereto is reset by the output signal of the above-mentioned gate circuit G4, thereby, the acceptance following is enabled.
In this embodiment, the output of the event generating circuit is transmitted as the timing assurance A to the clock terminal CK of the above-mentioned flip-flop circuit FF2 through the delay circuit DL1. This will be explained next, but it is something which assures timing in order to securely fetch the output signal of the gate circuit G1 by the event generating output. Moreover, as the timing assurance B, the output signal E of the above-mentioned flip-flop circuit FF3 is delayed by the delay circuit DL2, and transmitted as the gate control signal of the above-mentioned gate circuits G4 and G5. It will be explained next, but it is something which judges correctly the state of the flip-flop circuit FF2.
This figure shows that the timing assurance A prevents a malfunction where a port A with the higher priority-rank is ignored and becomes 0101 when an access request to the port A with a higher priority-rank is generated and the clock CKA changes into high level during an access request to the above-mentioned B port. That is, the event signal, which is transmitted to the clock terminal CK of the flip-flop circuit FF2, is delayed by the delay circuit DL1 and the set state to the flip-flop circuit FF1A is reflected correctly.
Moreover, it also prevents a malfunction, in which the request to the port B is accepted by the flip-flop circuit FF2 and then, according to a request to the port A, port A awaiting execution is reset from the state ABPE=1111 to the state 0111 by the priority encoder. In other words, in order to reflect correctly the port accepted by the above-mentioned flip-flop circuit FF2 at the output of the priority encoder, the output signal E of the flip-flop circuit FF3 is delayed by the delay circuit DL2, and the timing assurance B is performed, thereby, the latest information accepted by the above-mentioned flip-flop circuit FF2 is correctly reflected in the output of the priority encoder The above-mentioned delay circuits DL1 and DL2 may be any which uses a delay circuit such as an inverter circuit, the gate circuits G3-G5 themselves placed in the transmission path, or one, where the signal delay of the above-mentioned signal transmission path is made to have a delay-time as mentioned above by a relationship with the signal delay which has a competitive nature, taking into consideration the length of connecting wiring and the parasitic capacitance of this wiring.
In this figure, open characters written on shaded backgrounds with underlined states indicate stable states. Open characters written on shaded backgrounds and not underlined states indicate quasi-stable states. This quasi-stable state means operation such as memory access etc. to the selected port, and transition is generated by completion signal Done of the memory access in question. Arrows with thick lines indicate transitions with lacing.
For instance, the initial state ABPE=0000 changes to 1000 when clock CKA is input to port A, to 1100 when clock CKA and CKB are simultaneously input to both ports A and B, and to 0100 when clock CKB is input to port B. The simplest operation is as follows. When clock CKA is input to port A and is selected, memory access is executed to the 1 port SRAM, and there is no access request from the other port B until the operation is complete, and it returns to states 1000->1001->0001->Done->0000 according to the thin line arrow. When the clock CKB is input to port B and is selected, memory access is executed to the 1 port SRAM, and there is no access request from the other port A until the operation is complete, and it becomes stable by states 0100->0110->0111->0011->Done->0010 according to the thin line arrow.
As mentioned above, there are two types of stable states, 0000 and 0010. While the output P of the flip-flop circuit FF2 becomes 1->0 by access from port A in the state where the flip-flop circuit FF2 is being set, when the output E of the flip-flop circuit FF3 becomes high-level, the flip-flop circuit FF1B corresponding to port B is allowed to reset by misjudging that port B is selected by the priority encoder as mentioned above. At this time, if there is an access request from port B, a malfunction is created where it is made invalid. However, because of the timing assurance B, such problem does not arise.
In this embodiment, even when clock CKA or CKB changes in the above-mentioned quasi-stable state and transition state, the state transition is generated as shown in the figure, the state finally becomes stable in either 0000 or 0010, and the port selection operation is executed according to a correctly decided priority-rank. In this embodiment, the state of the flip-flop circuit FF2 is finally judged by the output signal of the flip-flop circuit FF3, and because a port is selected with a higher priority-rank corresponding to this state, one port can be selected correctly without any relation to the number of ports.
The execution port is selected by the priority encoder according to the information fetched into the port register (FF2) as mentioned above, and the request acknowledgment register FF1 corresponding to the execution port is reset. Because the Done signal is asserted and the flip-flop circuit FF3 is reset when the execution of the 1 port SRAM core is complete, if an unexecuted request demand remains, the next request will be executed when the gates of event generating circuits G1 and G2 are opened.
The hazard-free asynchronous control circuit in this embodiment accepts the input of a plurality of clocks CK, selects one of the access requests, and outputs the execution address and data of the port corresponding to the execution request to the 1 port SRAM. When execution is complete, the SRAM core outputs the end of execution signal to the controlled circuit, and maintains the data in the output latch of the port corresponding thereto, and outputs it again with the address and data of the next execution wait. That is, the controlled circuit and the SRAM core are performing a sort of handshake protocol.
However, in a system in which an end of execution signal is output to the controlled circuit when the memory operation of such an SRAM core is complete, it is impossible to use a conventional SRAM core as-is because the SRAM core needs a mechanism which detects the enabling of an executable state and reports it to the controlled circuit. Therefore, as shown in the embodiment illustrated in the aforementioned
The output signals A, B, C, and D of the above-mentioned flip-flop circuits FF1A, FF1B, FF1C, and FF1D are transmitted to the combinatorial logic circuit made up of gate circuits G11-G17 comprising the event generating circuit. The above-mentioned event generating circuit forms the reversed OR circuit (A+B+C+D) of the above-mentioned flip-flop circuits FF1A, FF1B, FF1C, and FF1D. This output signal of the event generating circuit is transmitted to the flip-flop circuit FF3, which is a register acknowledging the event, and to the flip-flop circuits FF2A, FF2B, and FF2C, which are port registers, while it is reversed by the output inverter circuit IV11 and transmitted to the 1 port SRAM as clock CK.
The output signals A, B, C, and D of the flip-flop circuits FF1A, FF1B, FF1C, and FF1D are respectively supplied to one input of NAND gate circuits G11-G14 constituting the above-mentioned event generating circuit, and the reversed output signal of the flip-flop circuit FF3 acknowledging the above-mentioned event is supplied to the another sides. That is, when the flip-flop circuit FF3 is set, the gate control signal supplied to the above-mentioned NAND gate circuits G11, G12, G13, and G14 becomes low-level, and the input acknowledgment is stopped.
In this embodiment, the priority-rank is set in the order of port A, port B, port C, and port D. That is, the output signal of the above-mentioned event generating circuit is transmitted to the clock terminal ck of the flip-flop circuits FF2A, FF2B, and FF2C constituting the port register. The output signal reversed by the gate circuit G11 accepting the output signal A of the flip-flop circuit FF1A corresponding to the above-mentioned port A is transmitted to the data terminal d of the above-mentioned flip-flop circuit FF2A. The output signal reversed by the gate circuit G12 accepting the output signal B of the flip-flop circuit FF1B corresponding to the above-mentioned port B is transmitted to the data terminal d of the above-mentioned flip-flop circuit FF2B. The output signal reversed by the gate circuit G13 accepting the output signal C of the flip-flop circuit FF1C corresponding to the above-mentioned port C is transmitted to the data terminal d of the above-mentioned flip-flop circuit FF2C.
When an event is generated, flip-flop circuits FF1A-FF1C are judged SET/RESET through the gate circuits G11-G13, port A is selected if the flip-flop circuit FF1A is in the SET state, port B is selected if the above-mentioned flip-flop circuit FF1A is in the RESET state and flip-flop circuit FF1B is in the SET state, port C is selected if the above-mentioned flip-flop circuits FF1A and FF1B are in the RESET state and the flip-flop circuit FF1C is in the SET state, port D is selected if the above-mentioned flip-flop circuits FF1A, FF1B, and FF1C are in the RESET state.
That is, even when event is generated, the above-mentioned three flip-flop circuits FF1A, FF1B, and FF1C being in the RESET state means that the flip-flop circuit FF1D is judged to be in the SET state.
In order to select a port according to the above-mentioned priority-rank, the output signal q of the above-mentioned flip-flop circuits FF2A-FF2C and the reversed signal thereof are transmitted to the gate circuits G21-G24 constituting the priority encoder. One output signal from these gate circuits G21-G24 is made a low-level selection state according to the priority-rank. The output signals of these gate circuits G21-G24 are transmitted to the reset terminals of the above-mentioned flip-flop circuits FF1A-FF1D through and corresponding to each of the gate circuits G25-G28 in which the gates are controlled by the output signal of the flip-flop circuit FF3 being the above-mentioned event acknowledgment register. Thereby, of the flip-flop circuits FF1A-FF1D in the input section, the one corresponding to the port is reset, which is selected like the embodiment shown in the aforementioned
The above-mentioned gate circuit G21 or G24 is output through the inverter circuits IV12-IV15 used for output. That is, one output signal out of the four gate circuits G21-G24 corresponding to the above-mentioned priority-rank becomes low-level, is reversed by the above-mentioned inverter circuits IV12-IV15 corresponding thereto, and is output. Thereby, one of the port selection signals CPA-CPD, which is made high-level, selects a selector of the input latch which is not illustrated. In this embodiment, the delay circuits for timing assurance A and timing assurance B shown in the aforementioned
As illustrated in the close-up example in this figure, the output latch consists of a SET/RESET flip-flop circuit in which an enable terminal E consisting of NAND gate circuits G31-G34 is installed. The logic signal of the selected control signal we and the port selection signals cp1-cp4 are transmitted to the enable terminal E, and, during a read operation of the selected port, the output latch corresponding thereto is made effective and the output signal of the sense amplifier is fetched.
Although the 1 port SRAM is not specified, it consists of a 1K word×72-bit synchronization SRAM. Therefore, 72 memory cells of the memory array are selected by the decoder; the stored information of the selected memory cells is amplified by the sense amplifier, and output in 72-bit units to the output latch corresponding to the selected port. The write driver accepts the above-mentioned write data, and the data corresponding to the selected port is written in the memory array.
The asynchronous control circuit of the present invention receives the clocks ck1-ck4 asynchronously input from the four ports, and, when the clocks are simultaneously supplied from a plurality of ports, it selects one port according to the priority-rank and supplies the clock ck, control signal we, and address a to the synchronous SRAM. If it is a write operation, the write data d are also fetched. If it is a read operation, the read signal from the selected memory cell is output by the above-mentioned address a as the data output q. The asynchronous control circuit receives the end of execution signal, done, of the synchronous SRAM, which is formed by the cycle time replica circuit corresponding to the above-mentioned synchronous SRAM, and executes continuously the access by the unexecuted port.
The output enable terminals /oe1-/oe4 are installed and they are made the operation control signal of the output buffer having a three-state output function. Operation of the output buffer circuit is made effective, and the data is output from the corresponding outer terminal /io1-/io4.
The internal circuit shown as the black box consists of the aforementioned asynchronous control circuit, cycle time replica circuit, input latch, selector and 1 port synchronous SRAM, and output latch. The write data input from the outer terminals /io1-/io4 are input as the write data input d1-d4 into the input latch installed in the above-mentioned black box. The address signals a1-a4 are input into the corresponding input latch through the address input buffer. Read/write control signals /rw1-/rw4 are input into the corresponding input latch through the control input buffer. The clock enable terminal /ce1 or /ce4 is installed corresponding to the clock terminal ck1 or ck4; these AND operations are taken by the gate circuits which double as the input buffers, and the clock signals ck1-ck4 transmitted to the asynchronous control circuit in the black box are generated.
Except for the center of the part in which the chips are installed as shown in
The parts except for the above-mentioned ports 1 and 2 and the part generating the address signals a3 and a4 with the above-mentioned address counter is made to have the same configuration as the aforementioned
Three ports 1-3 may be used for the random I/O and the remaining port 4 may be used for the serial I/O. Data can be rewritten at random to the memory array using the three ports, and it can be output from the one port in order. For instance, images and characters can be updated by using the above-mentioned three ports, and display data can be output regularly from the above-mentioned one serial port according to the operation of the display device. In this case, it only has to assume the priority-rank of the above-mentioned serial port to be lower rank when the display operation is slower than the update of images and characters, and, when the priority is put on the display operation, it only has to assume the priority-rank of the above-mentioned serial port to be the highest priority-rank.
The above-mentioned control signals DReady1-DReadyn may be a microprocessor accessing the asynchronous pseudo multi-port memory and the above-mentioned user logic etc. may make the next access possible to be permitted by, for instance, receiving the above-mentioned signal DReady1. In the case where the chance of memory access is equally allocated to 1 or n ports, the above-mentioned signals DReady1-DReadyn are returned to the microprocessor and the user logic from the asynchronous control circuit after waiting for the end of the non-executed memory access with the lowest priority-rank. Or, it may be the one which lets the above-mentioned microprocessor and user logic know that there is effective data for the above-mentioned DReady1 in the output latch. The configuration to allocate the chance of memory access equally to the above-mentioned n port may be achieved by executing the memory access request cyclically n times within the memory cycle in the microprocessor and user logic, etc. which executes memory access.
According to this configuration, an equivalent 3 port SRAM can be achieved using the 2 port SRAM. The asynchronous control circuit of the present invention is not limited by the combination with a 1 port SRAM, but it is one where an asynchronous control circuit is installed in an N port SRAM including a 1 port SRAM, and an asynchronous SRAM with M ports (M>N) can be achieved. In this signal processing system, it may be possible to transfer data between CPU1-CPU2 having mutually different system clocks.
In the aforementioned
Then, in this embodiment, a synchronous circuit is used as the flip-flop circuits FF2 and FF2A-FF2C shown in the aforementioned
The asynchronous input signal is input to data terminal D of latch (or, flip-flop) circuit 10 as the first step. The clock is supplied to clock terminal CLK. In such a latch circuit 10, the metastable state is generated by a certain probability as mentioned above. However, this latch circuit 10 is set to intentionally have a constant offset voltage Voff against the output signal from the non-reversing output Q and reversing output /Q in a metastable state. Additionally, a pair of output terminals Q and /Q of the above-mentioned latch circuit 10 are supplied to a pair of input terminals of the amplifier circuit and are amplified. Although it is not specified, this amplifier operation is initiated by the timing signal where the above-mentioned clock is delayed by the delay circuit 30.
Two CMOS inverter circuits with cross-connected input and output are used for the latch circuit on the first stage. One CMOS inverter circuit consists of an N-channel MOSFET MN1 and P-channel MOSFET MP1. Another CMOS inverter circuit consists of an N-channel MOSFET MN2 and P-channel MOSFET MP2. The power supply voltage vdd is supplied for the sources of the above-mentioned P-channel MOSFETs MP1 and MP2. N-channel MOSFET MN4 is installed between the sources of the N-channel MOSFETs MN1 and MN2 and the ground voltage of the circuit. Then, P-channel MOSFETs MP3 and MP4 are installed for precharge or pull-up between the power supply voltage vdd and a pair of I/O nodes cross-connecting the above-mentioned input and output. N-channel MOSFET MN3, which acknowledges the input signal, is connected in a parallel configuration with the N-channel MOSFET MN1 constituting one of the above-mentioned CMOS inverter circuits. Asynchronous input signal D and clock signal CLK are supplied to the gate of this MOSFET MN3 through NOR gate circuit NOR. And clock signal CLK is supplied to the gates of N-channel MOSFET MN4 and above-mentioned P-channel MOSFETs MP3 and MP4.
When the clock signal CLK is a low-level, because of the P-channel MOSFETs MP3 and MP4, the cross-connected input and output of the two CMOS inverter circuits having the above-mentioned latch configuration are charged-up or pulled-up to a high-level such as the power supply voltage vdd. In this embodiment, in order to give an offset voltage Voff to a pair of output signals in the metastable state, the N-channel MOSFET MN1 of one of the above-mentioned CMOS inverter circuits is made in a smaller size (small conductance), about {fraction (1/10)} that of the N-channel MOSFET NM2 of the other CMOS inverter circuit.
When the asynchronous input signal D is a high-level, the output signal of NOR gate circuit NOR is a low-level, and N-channel MOSFET MN3 is in OFF state.
When the clock signal CLK changes from low-level to high-level, the above-mentioned P-channel MOSFETs MP3 and MP4 become in OFF state and the above-mentioned N-channel MOSFET MM4 becomes in ON state. Because the change of drain voltage of the N-channel MOSFET MN2 is faster than that of the N-channel MOSFET MN1, the N-channel MOSFET MN1 becomes in OFF state and the N-channel MOSFET MN2 becomes in ON state, thereby, the data corresponding to the asynchronous input signal of the above-mentioned low-level can be stored.
When the asynchronous input signal D is a low-level, the output signal of NOR gate circuit NOR is a low-level, and N-channel MOSFET MN3 is in ON state. Thus, when the clock signal CLK changes from low-level to high-level, the above-mentioned P-channel MOSFETs MP3 and MP4 become in OFF state and the above-mentioned N-channel MOSFET MM4 becomes in On state. Thereby, corresponding to the ON state of the above-mentioned N-channel MOSFET MN3, the N-channel MOSFET MN2 becomes in OFF state and the N-channel MOSFET MN1 becomes in ON state, so that the data opposite to the above-mentioned can be stored. In this storage state, the N-channel MOSFET MN3 is made OFF state caused by the low-level of the output signal of the above-mentioned NOR gate circuit NOR, and the data are stored corresponding to the ON/OFF of the above-mentioned N-channel MOSFETs MN1 and MN2.
When asynchronous signal D is input almost simultaneously into the clock signal CLK, there is a possibility that the current flowing to N-channel MOSFET MN1 and MN2 is balanced and becomes metastable state (quasi-stable state) for a while. It is expected that such a metastable state (quasi-stable state) is generated at a certain constant frequency when the frequency of the clock CLK is different from the frequency of the circuit generating the asynchronous input signal. In this embodiment, in the case where the above-mentioned quasi-stable state is generated, the gate voltage of the N-channel MOSFET MN1 must become higher than the gate voltage of the N-channel MOSFET MN2 in order to flow the same current into both MOSFETs, because the dimension of the N-channel MOSFET MN1 is smaller than that of the N-channel MOSFET MN2. This means that a constant offset voltage Voff exists in the output signal consisting of non-reversed output signal (Q) and reversed output signal (/Q) of the latch circuit. Thus, in the latch circuit of the first stage, even if a metastable state is generated, a potential difference corresponding to the size ratio of N-channel MOSFETs MN1 and MN2 can be generated between the output signals of the non-reversed output (positive) signal and reversed output (negative) signal.
The latch circuit of the second stage is an amplifier circuit which senses the above-mentioned offset voltage Voff, and a latch circuit is used to make it high sensitivity and low electric power consumption, although it is not specified. This latch circuit consists of cross-connecting the inputs and outputs of one CMOS inverter circuit, which consists of N-channel MOSFET MN5 and P-channel MOSFET MP7, with another CMOS inverter circuit, which consists of N-channel MOSFET MN6 and P-channel MOSFET MP8. The power supply voltage vdd is supplied to the sources of the above-mentioned P-channel MOSFETs MP7 and MP8. The N-channel MOSFET MN7 is installed between the sources of the N-channel MOSFETs MN5 and MN6 and the ground voltage of the circuit. A pair of input terminals of the above-mentioned latch circuit is connected to a pair of output terminals of the first stage latch circuit and P-channel MOSFETs MP5 and MP6. Then, the signal DCLK, which is delayed by the delay circuit DLY, is supplied to the above-mentioned P-channel MOSFETs MP5 and MP6 and N-channel MOSFET MN7 gate.
Because such latch circuit is used, the clock signal CLK can be operated by the signal DCLK delayed by the delay circuit DLY to fetch the above-mentioned offset voltage Voff.
That is, when the signal DCLK changes from low-level to high-level, the P-channel MOSFETs MP5 and MP6 become off and the aforementioned offset voltage Voff is fetched in the input of the latch circuit of the second stage, even if a metastable state is generated. Because the above-mentioned signal DCLK is high-level, the N-channel MOSFET MN7 becomes in On state. The N-channel MOSFETs MN5 and MN6 of the latch circuit of the second stage are made to be the same dimension, and the P-channel MOSFETs MP7 and MP8 are also made the same dimension. That is, the input offset is designed to be small corresponding to process variations.
This latch circuit of the second stage is operated, for instance, as a dynamic type memory sense amplifier and to amplify the potential difference between nodes N1 and N2 as well.
In a practical circuit, there is an offset distribution in the input voltage of this latch circuit of the second stage because of the aforementioned process variation within the chips. However, the offset voltage Voff in the latch circuit of the first stage, which is an output potential difference when the metastable state is generated, is designed to be larger than the variation in input offset voltage of the latch circuit of the second stage. Therefore, even if a metastable state (quasi-stable state) is generated in the latch circuit of the first stage, the above-mentioned offset voltage Voff is amplified by the latch circuit of the second stage and can be made to settle at one of the logic levels corresponding to a stable output state. The delay time of the above-mentioned delay circuit DLY may be quite a short, period, enough to fetch into the second latch circuit the offset voltage Voff of the metastable state in the latch circuit of the first stage. In other words, since there is no need to wait until the metastable state is solved as shown in the synchronous circuit in the aforementioned
The above-mentioned latch circuits of the first and second stages have operation/non-operation (precharge or reset period) corresponding to clock CLK. Therefore, in the non-operation period, the output latch is installed in order to keep the asynchronous signal (including metastable state) which is fetched just before.
In the output latch, the signals of a pair of nodes N1 and N2 in the above-mentioned latch circuit of the second stage are input into the inverter circuits INV1 and INV2. The output signals of these inverter circuits INV1 and INV2 are transmitted to the gates of N-channel MOSFETs MN8 and MN9 on one side. The output signals of above-mentioned inverter circuits INV1 and INV2 are cross-input into the inverter circuits INV4 and INV3 on the other side, and the reversed-output signals are transmitted to the gates of the P-channel MOSFETs MP9 and MP10. The above-mentioned N-channel MOSFETs MN8 and MP9 and the above-mentioned N-channel MOSFETs MN9 and MP10 are individually connected in series between the power supply voltage vdd and the circuit ground voltage vss, and comprise the tri-state output circuit. The drain output signal connected in common with the above-mentioned MOSFETs MN8 and MP9 and the drain output signal connected in common with the above-mentioned MOSFETs MN9 and MP10 are transmitted to the latch circuit comprising the cross-connected input and output of the inverter circuits INV5 and INV6. One output signal of this latch circuit is transmitted to the output terminal Q which obtains a synchronous signal through the inverter circuit INV7.
In the precharge (reset) period in which the clock signal CLK is low-level, both aforementioned nodes N1 and N2 are precharged to high-level. Therefore, because the output signals of both inverter circuits INV1 and INV2 are made low-level, the N-channel MOSFETs MN8 and MN9 constituting the above-mentioned tri-state output circuit are made off state. Moreover, because the output signals of both inverter circuits INV3 and INV4 are made high-level, the P-channel MOSFETs MP9 and MP10 constituting the above-mentioned tri-state output circuit are made off state. Therefore, because these two tri-state output circuits are both in a high-impedance state when the above-mentioned clock signal CLK is low-level, the latch circuit consisting of the above-mentioned inverter circuits INV5 and INV6 maintains the state before the above-mentioned precharging and then outputs.
When the clock signal CLK is made high-level, the nodes N1 and N2 are fixed at a binary level in the above-mentioned latch circuit of the first and second stages corresponding to asynchronous signal D. For instance, if the node N1 is high-level and the node N2 is low-level, P-channel MOSFET MP9 and N-channel MOSFET MN9 are in On state and P-channel MOSFET MP10 and N-channel MOSFET MN 8 are in OFF state. At that time, the high-level is output from the output circuit consisting of MOSFET MP9 and MN8, and the low-level is output from the output circuit consisting of MOSFET MP10 and MN9, thereby, the latch circuit consisting of inverter circuits INV5 and INV6 fetch the signals corresponding thereto and output a low-level from the output terminal Q. On the other hand, if the node N1 is low-level and the node N2 is high-level, a high level is output from the output terminal Q.
In the case where the conventional flip-flop circuit is used as a synchronous circuit 8, a conflict arises in the logic circuit when a metastable state (quasi-stable state) as previously mentioned is generated in the flip-flop circuit, thereby, the aforementioned malfunction is created. If the two-stage flip-flop circuit is used as shown in aforementioned
Above we have illustrated the invention of the present inventors on the basis of the preferred embodiments. However, it is to be understood that the invention is not intended to be limited to the specific embodiment and variations may be made by one skilled in the art without departing from the scope of the invention. For instance, anything which achieves the aforementioned function may be used for a concrete configuration of the aforementioned event generating circuit and priority encoder. It is not necessary to allocate the chance of memory access equally to n ports. For instance, the memory access may always be executed from the microprocessor and the user logic, etc. with a high priority-rank, and the microprocessor and the user logic, etc. with a low priority-rank may be the one where access is permitted only with an empty state. Anything such as control devices executing display operation and direct memory access control devices, etc. may be used for the device executing memory access besides the above-mentioned microprocessor and user logic, etc.
In the aforementioned embodiment circuit shown in
The effects obtained by the embodiments disclosed in the present invention are briefly explained as follows:
It is possible to realize asynchronous operation as an asynchronous control circuit and to remove the limitation on the number of ports performing, by the following steps of:
A multi-port memory without limitation on the number of ports in an asynchronous operation with a small area can be achieved by the following steps of:
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-272549 | Jul 2003 | JP | national |
| 2004-131238 | Apr 2004 | JP | national |
