Atomically testing and setting or clearing one or more bits stored in a memory location

Abstract

Logic for or atomically testing and setting one or more bits stored in a memory location, in a single operation, disables one or more interrupts, access a number stored in a memory location, copies the number from the memory location to a working register, tests a particular bit of the number copied from the memory location, sets or clears a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations, sets the particular bit of the number copied from the memory location, and copies the number from the working register to the memory location. Logic for atomically testing and clearing one or more bits stored in a memory location, in a single operation, disables one or more interrupts, accesses a number stored in a memory location, copies the number from the memory location to a working register, tests a particular bit of the number copied from the memory location, sets or clears a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations, clears the particular bit of the number copied from the memory location, and copies the number from the working register to the memory location.

Description

TECHNICAL FIELD OF THE INVENTION

[0001] This invention relates generally to processor operations and more particularly to atomically testing and setting or clearing one or more bits stored in a memory location.

BACKGROUND OF THE INVENTION

[0002] One or more bits stored in a memory location may be shared by a number of independent processes that may occasionally interrupt each other. Such bits may be atomically (meaning without interruption) tested and set (meaning changed to one) or cleared (meaning changed to zero). Such testing and setting or clearing of bits may take place, for example, in semaphore or similar operations. Traditionally, atomically testing and setting or clearing one or more bits stored in a memory location has required a number of operations: in a first operation, interrupts are disabled; in a second operation, the memory location is accessed and the number at that location is stored in a register; in a third operation, one or more bits of the number are tested and the test results are stored in one or more status registers; in a fourth operation, the tested bits are set or cleared; in a fifth operation, the number (including the set or cleared bits) is stored in the original memory location; and, in a sixth operation, interrupts are enabled.

SUMMARY OF THE INVENTION

[0003] Particular embodiments of the present invention may reduce or eliminate disadvantages and problems traditionally associated with atomically testing and setting or clearing one or more bits stored in a memory location.

[0004] In one embodiment of the present invention, logic for or atomically testing and setting one or more bits stored in a memory location, in a single operation, disables one or more interrupts, access a number stored in a memory location, copies the number from the memory location to a working register, tests a particular bit of the number copied from the memory location, sets or clears a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations, sets the particular bit of the number copied from the memory location, and copies the number from the working register to the memory location. In a more particular embodiment, the logic described above, in a single operation, accesses a number stored in a register, copies the number from the register to a working register, tests a particular bit of the number copied from the register, sets or clears a bit flag to reflect the state of the particular bit of the number copied from the register for access in one or more subsequent operations, sets the particular bit of the number copied from the register, and copies the number from the working register to the register.

[0005] In another embodiment, logic for atomically testing and clearing one or more bits stored in a memory location, in a single operation, disables one or more interrupts, accesses a number stored in a memory location, copies the number from the memory location to a working register, tests a particular bit of the number copied from the memory location, sets or clears a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations, clears the particular bit of the number copied from the memory location, and copies the number from the working register to the memory location. In a more particular embodiment, the logic described above, in a single operation, accesses a number stored in a register, copies the number from the register to a working register, tests a particular bit of the number copied from the register, sets or clears a bit flag to reflect the state of the particular bit of the number copied from the register for access in one or more subsequent operations, clears the particular bit of the number copied from the register, and copies the number from the working register to the register.

[0006] Particular embodiments of the present invention may provide one or more technical advantages. Particular embodiments may substantially reduce the number of operations required to atomically test and set or clear bits stored in memory locations, which may reduce code size associated with atomically testing and setting or clearing bits stored in memory locations. Particular embodiments may provide one or more operations for atomically testing and setting or clearing bits stored in memory locations and bits stored in registers. Particular embodiments may provide one or more orthogonal operations for atomically testing and setting or clearing bits. Particular embodiments may provide one or more operations for atomically testing and setting or clearing bits stored in memory locations that may be executed in a single cycle (barring memory conflicts) by processor systems that include a Read→Execute→Write “pipeline.” Particular embodiments may increase efficiency in semaphore operations. Certain embodiments may provide all, some, or none of these technical advantages, and certain embodiments may provide one or more other technical advantages which may be readily apparent to those skilled in the art from the figures, descriptions, and claims included herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To provide a more complete understanding of the present invention and the features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which:

[0008] FIG. 1 illustrates an example processor system;

[0009] FIG. 2 illustrates execution of an example TCLR operation; and

[0010] FIG. 3 illustrates execution of an example TSET operation.

DESCRIPTION OF EXAMPLE EMBODIMENTS

[0011] FIG. 1 illustrates an example processor system 10, which may include a digital signal processor (DSP). Although a particular processor system 10 is described and illustrated, the present invention contemplates any suitable processor system 10 including any suitable architecture. Processor system 10 may include program memory 12, data memory 14, and processor 16. Program memory 12 may be used to store program instructions for operations executed by processor 16, and data memory 14 may be used to store data used in operations executed by processor 16. Data (which may include program instructions, data used in operations executed by processor 16, or any other suitable data) may be communicated between processor 16 and program memory 12 and between processor 16 and data memory 14 using data buses 18, which may include any suitable physical medium for such communication. For example, data buses 18 may include one or more wires coupling processor 16 to program memory 12 and data memory 14. The number of bits that may be communicated across a data bus 18 in one clock cycle (which may include a unit of time between two adjacent pulses of a clock signal for processor system 10) may be limited. For example, in a 32-bit environment, a maximum of thirty-two bits may be communicated across each data bus 18 in one clock cycle. Data addresses (which may specify locations for data within program memory 12, data memory 14, elsewhere within processor system 10, or outside processor system 10 and may, where appropriate, include the locations themselves) may be communicated between processor 16 and program memory 12 and between processor 16 and data memory 14 using address buses 20, which may include any suitable physical medium for such communication. For example, address buses 20 may include one or more wires coupling processor 16 with program memory 12 and data memory 14. Similar to data buses 18, the number of bits that may be communicated across an address bus 20 in one clock cycle may be limited.

[0012] Processor 16 may execute mathematical, logical, and any other suitable operations and may, for example only and not by way of limitation, include one or more shifters 22, arithmetic-logic units (ALUs) 24, multipliers 26, data registers 28, instruction caches 30, program sequencers 32, and data address generators 34. Although a particular processor 16 is described and illustrated, the present invention contemplates any suitable processor 16 including any suitable components. Shifter 22 may be used to left- or right-shift data units and perform other suitable tasks. ALU 24 may be used for addition, subtraction, absolute value operations, logical operations (such as, for example, AND, OR, NAND, NOR, and NOT operations), and other suitable tasks. Multiplier 26 may be used for multiplication and other suitable tasks. In a 32-bit environment, shifter 22, ALU 24, and multiplier 26 may each process a maximum of thirty-two bits in one clock cycle. For example, ALU 24 may in one clock cycle add numbers that include at most thirty-two bits. To add numbers that include more than thirty-two bits, the numbers may be divided into parts that each include thirty-two or fewer bits and added in parts.

[0013] Registers 28 may include a number of locations for storing intermediate operation results, flags for program control, and the like. For example, registers 28 may include one or more general data registers, temporary registers, condition code registers (CCRs), status registers (SRs), address registers, and other suitable registers. In a 32-bit environment, each register 28 may be used to store a maximum of thirty-two bits. Instruction cache 30 may be used to store one or more program instructions for recurring operations. For example, program instructions for one or more operations that are part of a loop of operations executed by processor 16 may be stored using instruction cache 30 such that program memory 12 need not be accessed each time a program instruction for one or more of the operations is to be executed. Program sequencer 32 may direct the execution of operations by processor 16 and perform other suitable tasks. Data address generators 34 may communicate addresses to program memory 12 and data memory 14 specifying memory locations within program memory 12 and data memory 14 from which data may be read and to which data may be written. Although particular components of processor 16 are described as performing particular tasks, any suitable components of processor 16, alone or in combination, may perform any suitable tasks. In addition, although the components of processor 16 are described and illustrated as separate components, any suitable component of processor 16 may be wholly or partly incorporated into one or more other components of processor 16.

[0014] One or more bits stored in a memory location (which may include a memory location within program memory 12, data memory 14, elsewhere within processor system 10, or outside processor system 10) may be shared by a number of independent processes that may occasionally interrupt each other. One or more bits stored in a register 28 may similarly be shared by a number of independent processes. Such bits may be atomically (meaning without interruption) tested and set (meaning changed to one) or cleared (meaning changed to zero). Such testing and setting or clearing of bits may take place, for example, in semaphore or similar operations. Traditionally, atomically testing and setting or clearing one or more bits stored in a memory location has required a number of operations: in a first operation, interrupts are disabled; in a second operation, the memory location is accessed and the number at that location is stored in a register 28; in a third operation, one or more bits of the number are tested and the test results are stored in one or more status registers 28; in a fourth operation, the tested bits are set or cleared; in a fifth operation, the number (including the set or cleared bits) is stored in the original memory location; and, in a sixth operation, interrupts are enabled.

[0015] In particular embodiments, a single operation may atomically test and clear one or more bits stored in a memory location or a register 28. In particular embodiments, a single operation may atomically test and set one or more bits stored in a memory location or a register 28. As an example only and not by way of limitation, such operations may be described as follows:

TCLR	MemValue, #N	;	TestBitFlag = [MemValue(#N)]
		;	[MemValue(#N)] = 0
TSET	MemValue, #N	;	TestBitFlag = [MemValue(#N)]
		;	[MemValue(#N)] = 1

[0016] MemValue may include the memory location or register 28 in which the bit to be tested is stored. Herein, reference to a memory location or register 28 may, where appropriate, include the contents of the memory location or register 28 and may, where appropriate, include the location (logical or otherwise) of the memory location or register 28. N may include the position within the memory location or register 28 of the bit to be tested. TestBitFlag may include a bit flag that may be set for the later execution of one or more conditional operations or for any other suitable purpose. TestBitFlag may be stored in a status register 28 or other suitable location within or outside processor system 10. TCLR may, in a single operation, atomically test a bit stored in a memory location or a register 28, set or clear TestBitFlag to reflect the state of the tested bit, and clear the tested bit. Similarly, TSET may, in a single operation, atomically test a bit stored in a memory location or a register 28, set or clear TestBitFlag to reflect the state of the tested bit, and set the tested bit. Such operations may be implemented in hardware, software, or any suitable combination of hardware and software in processor system 10 or any other suitable processor system. In particular embodiments, such operations may be orthogonal.

[0017] FIG. 2 illustrates execution of an example TCLR operation. Execution begins at step 100, where one or more interrupts are disabled. At step 102, the contents of MemValue are copied from MemValue to a working register 28. As described above, MemValue may include the memory location or register 28 in which the bit to be tested is stored. Working register 28 may include any suitable register 28 for storing intermediate operation results. At step 104, bit N of the contents of MemValue is tested. At step 106, if bit N is equal to one, execution of the TCLR operation proceeds to step 108. At step 108, TestBitFlag is accessed and set to reflect the state of bit N. As described above, TestBitFlag may be stored in a status register 28 or other suitable location within or outside processor system 10. At step 106, if bit N is equal to zero, execution of the TCLR operation proceeds to step 110. At step 110, TestBitFlag is accessed and cleared to reflect the state of bit N. At step 112, bit N is cleared. At step 114, the contents of MemValue (including the cleared bit) are copied from working register 28 to MemValue. At step 116, the disable interrupts are enabled, at which point execution of the TCLR operation may end.

[0018] FIG. 3 illustrates execution of an example TSET operation. Execution begins at step 120, where one or more interrupts are disabled. At step 122, the contents of MemValue are copied from MemValue to a working register 28. As described above, Memvalue may include the memory location or register 28 in which the bit to be tested is stored. Working register 28 may include any suitable register for storing intermediate operation results. At step 124, bit N of the contents of MemValue is tested. At step 126, if bit N is equal to one, execution of the TCLR operation proceeds to step 128. At step 128, TestBitFlag is accessed and set to reflect the state of bit N. As described above, TestBitFlag may be stored in a status register 28 or other suitable location within or outside processor system 10. At step 126, if bit N is equal to zero, execution of the TCLR operation proceeds to step 130. At step 130, TestBitFlag is accessed and cleared to reflect the state of bit N. At step 132, bit N is set. At step 134, the contents of Memvalue (including the cleared bit) are copied from working register 28 to MemValue. At step 136, the disable interrupts are enabled, at which point execution of the TCLR operation may end.

[0019] Particular embodiments may substantially reduce the number of operations required to atomically test and set or clear bits stored in memory locations, which may reduce code size associated with atomically testing and setting or clearing bits stored in memory locations. Particular embodiments may provide one or more operations for atomically testing and setting or clearing bits stored in memory locations and bits stored in registers 28. Particular embodiments may provide one or more orthogonal operations for atomically testing and setting or clearing bits. Particular embodiments may provide one or more operations for atomically testing and setting or clearing bits stored in memory locations that may be executed in a single cycle (barring memory conflicts) by processor systems that include a Read→Execute→Write “pipeline.” Particular embodiments may increase efficiency in semaphore operations. Certain embodiments may provide all, some, or none of these technical advantages, and certain embodiments may provide one or more other technical advantages.

[0020] Although the present invention has been described with several embodiments, sundry changes, substitutions, variations, alterations, and modifications may be suggested to one skilled in the art, and it is intended that the invention may encompass all such changes, substitutions, variations, alterations, and modifications falling within the spirit and scope of the appended claims.

Claims

1. Logic for atomically testing and setting one or more bits stored in a memory location, the logic encoded in media and when executed operable to, in a single operation: disable one or more interrupts; access a number stored in a memory location; copy the number from the memory location to a working register; test a particular bit of the number copied from the memory location; set or clear a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations; set the particular bit of the number copied from the memory location; copy the number from the working register to the memory location.

2. The logic of claim 1, operable to, in a single operation: access a number stored in a register; copy the number from the register to a working register; test a particular bit of the number copied from the register; set or clear a bit flag to reflect the state of the particular bit of the number copied from the register for access in one or more subsequent operations; set the particular bit of the number copied from the register; copy the number from the working register to the register.

3. The logic of claim 1, wherein the bit flag is set if the particular bit is equal to one and cleared if the particular bit is equal to zero to reflect the state of the particular bit copied from the memory location.

4. The logic of claim 1, implemented in hardware associated with a processor system.

5. The logic of claim 4, wherein the processor system is a digital signal processor (DSP).

6. The logic of claim 4, wherein: the memory location comprises a location within data memory associated with the processor system; and the bit flag is stored in a status register associated with the processor system.

7. The logic of claim 1, wherein the one or more subsequent operations are conditional operations.

8. The logic of claim 1, used in one or more semaphore operations.

9. Logic for atomically testing and clearing one or more bits stored in a memory location, the logic encoded in media and when executed operable to, in a single operation: disable one or more interrupts; access a number stored in a memory location; copy the number from the memory location to a working register; test a particular bit of the number copied from the memory location; set or clear a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations; clear the particular bit of the number copied from the memory location; copy the number from the working register to the memory location.

10. The logic of claim 9, operable to, in a single operation: access a number stored in a register; copy the number from the register to a working register; test a particular bit of the number copied from the register; set or clear a bit flag to reflect the state of the particular bit of the number copied from the register for access in one or more subsequent operations; clear the particular bit of the number copied from the register; copy the number from the working register to the register.

11. The logic of claim 9, wherein the bit flag is set if the particular bit is equal to one and cleared if the particular bit is equal to zero to reflect the state of the particular bit copied from the memory location.

12. The logic of claim 9, implemented in hardware associated with a processor system.

13. The logic of claim 12, wherein the processor system is a digital signal processor (DSP).

14. The logic of claim 12, wherein: the memory location comprises a location within data memory associated with the processor system; and the bit flag is stored in a status register associated with the processor system.

15. The logic of claim 9, wherein the one or more subsequent operations are conditional operations.

16. The logic of claim 9, used in one or more semaphore operations.

17. A method for atomically testing and setting one or more bits stored in a memory location, the method comprising, in a single operation: disabling one or more interrupts; accessing a number stored in a memory location; copying the number from the memory location to a working register; testing a particular bit of the number copied from the memory location; setting or clearing a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations; setting the particular bit of the number copied from the memory location; copying the number from the working register to the memory location.

18. The method of claim 17, comprising, in a single operation: accessing a number stored in a register; copying the number from the register to a working register; testing a particular bit of the number copied from the register; setting or clearing a bit flag to reflect the state of the particular bit of the number copied from the register for access in one or more subsequent operations; setting the particular bit of the number copied from the register; copying the number from the working register to the register.

19. The method of claim 17, wherein the bit flag is set if the particular bit is equal to one and cleared if the particular bit is equal to zero to reflect the state of the particular bit copied from the memory location.

20. The method of claim 17, executed by hardware associated with a processor system.

21. The method of claim 20, wherein the processor system is a digital signal processor (DSP).

22. The method of claim 20, wherein: the memory location comprises a location within data memory associated with the processor system; and the bit flag is stored in a status register associated with the processor system.

23. The method of claim 17, wherein the one or more subsequent operations are conditional operations.

24. The method of claim 17, used in one or more semaphore operations.

25. A method for atomically testing and clearing one or more bits stored in a memory location, the method comprising, in a single operation: disabling one or more interrupts; accessing a number stored in a memory location; copying the number from the memory location to a working register; testing a particular bit of the number copied from the memory location; setting or clearing a bit flag to reflect the state of the particular bit copied from the memory location for access in one or more subsequent operations; clearing the particular bit of the number copied from the memory location; copying the number from the working register to the memory location.

26. The method of claim 25, comprising, in a single operation: accessing a number stored in a register; copying the number from the register to a working register; testing a particular bit of the number copied from the register; setting or clearing a bit flag to reflect the state of the particular bit of the number copied from the register for access in one or more subsequent operations; clearing the particular bit of the number copied from the register; copying the number from the working register to the register.

27. The method of claim 25, wherein the bit flag is set if the particular bit is equal to one and cleared if the particular bit is equal to zero to reflect the state of the particular bit copied from the memory location.

28. The method of claim 25, executed by hardware associated with a processor system.

29. The method of claim 28, wherein the processor system is a digital signal processor (DSP).

30. The method of claim 28, wherein: the memory location comprises a location within data memory associated with the processor system; and the bit flag is stored in a status register associated with the processor system.

31. The method of claim 25, wherein the one or more subsequent operations are conditional operations.

32. The method of claim 25, used in one or more semaphore operations.