Patent Application
20060160037
1. Field of the Invention
This invention relates to lithographic production of microelectronic devices and, in particular, to the lithographic exposure tools utilized therein to expose circuit patterns and other images on the surface of the wafer used to produce the microelectronic device.
2. Description of Related Art
Lithographic processing generally involves exposing a desired pattern onto a resist layer on a wafer substrate layer using a step-and-scan exposure tool, developing the resist layer to remove the portions exposed (or not exposed), and then further processing the wafer, for example, by etching the underlying layer or depositing additional material, using the developed resist layer. Lithographic imaging is highly dependent on substrate uniformity to create an accurate circuit pattern on the surface of an individual wafer layer to be lithographically processed. A lithographic process can tolerate a small range of topography through the depth of focus (DOF) inherent in the process capability. DOF describes the ability of the lithographic imaging process to maintain image integrity over a range of focal planes. Unanticipated topography variation on the substrate has become a significant problem for many next generation lithography processes using high numerical aperture (NA) imaging. The trend of increasing NA allows increased resolution but this comes at the expense of process DOF.
Modern step-and-scan exposure systems utilize an optical leveling system that maps out topography across the wafer prior to exposure. A series of optical sensors across the exposure slit collect a grid of height data that effectively create a topographical map of the wafer prior to exposure. For example, in IBM's ASML Twinscan exposure tools, a band of seven measurement spots scans each die to build a complete topographic map of the wafer.
This topographic map is then used to control the height (focus) of the scanning slit above the wafer. Ideally, the height offset is held perfectly constant throughout the exposure to ensure that the lithographic image remains in focus. At any point during the exposure, a very narrow slice of a die is being exposed as the reticle and wafer move relative to each other, projecting the lithographic image through a lens in this slit. The exposure tool can adjust to fluctuations in step-height, using the previously obtained topographic map, by a set of simple linear motions. For changes in the height of the wafer in the direction of the scanning slit, the exposure tool can simply raise or lower the wafer stage as needed to compensate and maintain focus position while the slit moves across the die.
In the case where the pre-scan detects significant changes in step height across the exposure slit, there is limited ability to compensate. Since image focus cannot be varied across the slit, the tool must attempt to balance out this error using linear wafer stage movements. For example, the simplest adjustment is to pick a stage position that compromises the height between the two surfaces. This is known as a Z-position adjustment. Additionally, the tool may choose to tilt the wafer stage relative to the exposure slit. This is in fact the limit of today's exposure tools. In doing so, the total error is further minimized, but is clearly not driven to zero. In fact, with significant step heights, many areas across this slit still see significant deviation from best focus. When the process does not have adequate DOF to support these deviations, failures are seen at these points, and this in fact happens frequently on early test sites.
The root cause of the topography variation leading to this is often pattern-density driven. In many cases, the pattern density in the test kerf is quite different than the product chips. Beyond this, product chips may also vary in density. As mask set costs escalate, it is increasingly common for customers to share these costs by coordinating a variety of different chips onto one reticle, sometimes even coordinating with other customers. Since these chips may have quite different design purposes, there is further opportunity for non-uniform pattern density. These pattern density offsets can eventually lead to a step height due to film coating and chemical-mechanical polishing (CMP) over the differing densities. As the wafers process through many successive deposition steps, small differences may eventually become amplified towards latter processing stages where they are often observed to cause product failures.
Such errors are difficult to predict, identify, and correct. Identification of missing patterns attributable to focus errors in many of these levels can be challenging. In many cases, critical failures are not found with conventional inline inspection techniques. Traditional fixes include improving the overall process latitude (often not feasible if step heights are excessive), improving the CMP uniformity, or scrapping the reticle set and re-designing in a way that better balances pattern density. All of these are both costly and time consuming, and in some cases, a practical solution cannot be found.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a system and method for improving lithographic exposure of circuit patterns and other images in the manufacture of microelectronic devices.
It is another object of the present invention to provide a system and method for accurately exposing a circuit patterns or other image on varying topography of a wafer used in the manufacture of microelectronic devices.
A further object of the invention is to provide a system and method for compensating for significant differences in height of a wafer on which a circuit patterns or other image is to be exposed.
It is yet another object of the present invention to provide a system and method for optimizing focus on each portion of a wafer used in the manufacture of microelectronic devices.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects, which will be apparent to those skilled in art, are achieved in the present invention which is directed to a method of exposing a substrate in a lithographic process comprising scanning the substrate to determine topography of the substrate and dividing the substrate into at least two designated areas based on the substrate topography. The method then separately exposes the designated areas by blocking a designated area while scanning an unblocked designated area, with the separate exposures being performed at different focus positions relative to the substrate.
Preferably, the substrate is scanned to determine topography in a first direction over the substrate, and the substrate is exposed in a second direction normal to the first direction. The designated areas may be exposed by, in sequence, blocking a first designated area, exposing a second designate area, blocking the second designated area and exposing the first designated area. The separate exposures may be performed at different, constant focus positions relative to the substrate. The substrate may be divided into more than two designated areas based on the substrate topography, such that the separate exposures are performed at more than two different focus positions relative to the substrate.
The different designated areas on the substrate may define different final product chips. Also, a least one designated area on the substrate may define a test pattern.
The substrate may be scanned to determine topography with the exposure tool, and the exposure may be performed by the exposure tool as it passes over the entire substrate during each designated area exposure. The exposure tool may travel in a first direction over the substrate during topography scanning, and in a second direction normal to the first direction during the designated area exposures.
In another aspect, the present invention provides a method of exposing images on a wafer having varying topography during lithographic production of microelectronic devices by determining topography of a wafer, dividing the wafer into two or more separate regions based on the wafer topography, and determining desired focus distance for exposing a desired image on each of the separate regions of the wafer. The method then includes exposing a desired image on one of the regions of the wafer at the desired focus distance while blocking remaining regions and exposing a desired image on another of the regions of the wafer at the desired focus distance while blocking remaining regions. The desired focus distance may be different for each of the separate wafer regions.
The method may include dividing the wafer into at least two separate regions across a first direction based on the wafer topography, and exposing the desired images on the separate wafer regions by scanning the images in a second direction normal to the first direction. The wafer regions may be exposed to the desired image by a scanner above the wafer, and during each exposure of the wafer regions the distance between the scanner and wafer may be changed. The method may further include determining optimum number of wafer regions to balance number of exposures with desired focus distances.
In yet another aspect, the present invention provides a method of exposing images on a wafer having varying topography during lithographic production of microelectronic devices comprising the steps of:
a) establishing a threshold of variation in topography for maintaining focus of an image to be exposed on a wafer;
b) determining variation in topography of the wafer;
c) comparing the wafer topography variation to the topography variation threshold;
d) if the wafer topography variation exceeds the topography variation threshold, dividing the wafer into at least two separate regions based on the wafer topography;
e) determining variation in topography of each separate region of the wafer;
f) comparing the wafer topography variation in each separate region to the topography variation threshold;
g) if the wafer topography variation exceeds the topography variation threshold in any region, dividing that region of the wafer into at least two additional separate regions based on the wafer topography;
h) optionally repeating steps (e)-(g) until variation in topography in all regions of the wafer is no greater than the topography variation threshold; and
i) exposing a desired image on each of the wafer regions at a desired focus distance.
The method preferably includes exposing a desired image on at least one of the regions of the wafer at the desired focus distance while blocking at least some remaining regions.
A further aspect of the present invention relates to a system for exposing images on a wafer having varying topography during lithographic production of microelectronic devices comprising a support for the wafer, sensors for determining topography of the wafer, and a computer program to determine division of the wafer into at least two separate regions based on the wafer topography. The system further includes a scanner above the wafer for exposing a desired image on the regions of the wafer at a desired focus distance from the wafer and a cover between the wafer and scanner for blocking remaining wafer regions while the scanner is exposing a desired image on one of the wafer regions. Preferably there is included a computer program to establish desired focus distance of the scanner from each of the wafer regions based only on the topography of each wafer region.
The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
In describing the preferred embodiment of the present invention, reference will be made herein to
The present invention divides or fractures portions of the wafer, also know as chiplets, into different scanning regions based on topographical data, and then incorporates potential chiplet fracturing in the reticle design and provides the exposure system with detailed information regarding these potential fracture points. With this information, the exposure tool can monitor and compensate the step height differences induced by variations in different areas of the wafer, e.g., from one customer part to another, or between test macros and product chips. In cases where significant topography variation is detected and exceeds the predetermined process DOF, the method of the present invention breaks the die down based on the predetermined fracture points and uses the exposure tool scanner to expose each chiplet separately at an optimal focus condition for that particular chiplet. Although this fracturing process may slow tool throughput, it is preferably utilized only on an as-needed basis by comparing the pre-mapped topography in each die against the process depth of focus. Through this methodology, the tool can intelligently balance tool throughput versus yield.
The step heights caused by pattern density or any other source may be detected by a prescreening method in the exposure tool as described above. Alternatively, any other suitable measurement technique may be used to gain this information prior to exposure such as AFM mapping of the wafer or independent optical surface mapping tools.
The present invention may be used to separately scan either full individual chiplet or test macro areas on the wafer, or portions or increments thereof. In the case of the latter, for alignment purposes, preferably one should make the separate exposure passes on increments of full chiplets or test macro regions that are specifically designed for use with the present invention. It is difficult to expose part of a chiplet at one level setting in one pass and follow with the other half of the same chiplet at a different level setting if microscale circuit continuity is to be maintained across the chiplet. Therefore, a further aspect of the method of the present invention is teaching the tool how the reticle creating the image is configured, so that the exposure tool understands what degrees of freedom it has to optimize the exposure passes. Specifically, each area that is a candidate for fracturing preferably incorporates alignment marks and overlay marks to evaluate overlay performance from the various passes. The layout for both complete chiplets is defined, along with additional definitions for sub-chiplets that may optionally be fractured. For example, exposure layer “AA” may be defined conventionally for the full chiplet. Then, exposure layers AA.1, AA.2, AA.x would define the boundaries of fracturable chiplets within layer AA.
Since exposure pass separation can slow down wafer throughput at the scanner, it is preferable that the layout of the chiplets, test macros, and other portions of the wafer within the overall chip be understood, so that an evaluation can be made on a per wafer or per lot basis to determine whether multiple exposure passes are necessary to ensure good process yield. By taking measurements just prior to exposure, in conjunction with engineering input for the depth of focus or other relevant process capability parameters for each exposure operation, the method of the present invention provides for intelligent evaluation to optimize the throughput-yield tradeoffs. For example, a process depth of focus (DOF) is typically measured in lithography. This parameter is a measure of how much focus plane variation may be tolerated while keeping the projected image within specifications. A target threshold may be established in the recipe setup file based on this DOF or some fraction thereof such that if the wafer surface variation exceeds this parameter, exposure pass fracturing is performed. This is illustrated in the flowchart shown in
The method of the present invention of exposing images on a wafer having varying topography during lithographic production of microelectronic devices may be implemented by a computer program or software incorporating the process steps and instructions described above in otherwise conventional program code and stored on a lithographic step-and-scan exposure tool or otherwise conventional program storage device. The program code as well as the topographical data may be stored in the tool computer on a program storage device, such as a semiconductor chip, a read-only memory, magnetic media such as a diskette or computer hard drive, or optical media such as a CD or DVD ROM. The tool's computer system includes a microprocessor for reading and executing the stored program code in the manner described above to receive the wafer topographical data, determine division of the wafer into at least two separate regions based on the wafer topography, and then establish the desired optimum focus height or distance of the scanner above each of the wafer regions.
As indicated in the flow chart of
If the process DOF cannot absorb the planarity offset between chiplets A and B, or between the test macros and the chiplet A, the wafer is fractured or divided three ways, between the test macros, chiplet A and chiplet B. In this case, the test macros are exposed during the scanning at focus height A, while chiplets A and B are blocked. Separately, chiplets A are exposed during the scanning at focus height C, while the test macros and chiplets B are blocked, and chiplets B are exposed during the scanning at focus height D, while the test macros and chiplets A are blocked. Each of the test macros, chiplets A and chiplets B are exposed by the scanner at their respective best focus height values in a total of three passes per wafer or die.
Thus, the present invention provides a system and method for accurately exposing a circuit patterns or other image on varying topography of a wafer used in the manufacture of microelectronic devices which compensates for significant differences in height of a wafer on which a circuit patterns or other image is to be exposed, and optimizes focus on each portion of a wafer.
While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
Thus, having described the invention, what is claimed is:
