Patent Application
20050078500
The present invention is directed to electronic devices and, more particularly, to repairable electronic devices that include redundant regions for replacing defective regions of the device, such as the cells of a semiconductor memory device.
Semiconductor memory devices, such as dynamic random access memory devices (DRAMs), typically include a semiconductor memory cell array formed of a plurality of memory cells arranged in rows and columns and include a plurality of bit lines as well as a plurality of word lines that intersect the bit lines. Each memory cell of the array is located at the intersection of a respective word line and a respective bit line and includes a capacitor for storing data and a transistor for switching, such as a planar or vertical MOS transistor. The word line is connected to the gate of the switching transistor, and the bit line is connected to the source or drain of the switching transistor. When the transistor of the memory cell is switched on by a signal on the word line, a data signal is transferred from the capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the capacitor of the memory cell.
As the capacity of semiconductor memory devices increases, the likelihood that a device includes one or more defective memory cells also increases, thereby adversely affecting the yield of the semiconductor memory device manufacturing processes. To address this problem, redundant memory cells are provided which can replace memory cells that are found to be defective during device testing. Typically, one or more spare rows, known as row redundancy, and/or one or more spare columns, known as column redundancy, are included in the memory cell array. The spare rows and/or columns have programmable decoders that can be programmed to respond to the address of the defective row and/or column, known as the fail address, while at the same time disabling the selection of the defective cell. To program the address of a defective memory cell into the programmable decoder, one or more fuses are programmed to represent the respective bits of the fail address by blowing selected ones of the fuses. One of a 0 or 1 value is defined as a fuse in a blown or open state, and the other of the 0 and 1 values is defined as a fuse in an unblown or shorted state.
When an address of a defective memory cell is received, the redundant memory cell is selected so that part or all of the word line or bit line that is connected to the redundant memory cell is substituted for the corresponding portion of a word line or bit line of entire word line or bit line that contains the defective memory cell. As a result, the repaired memory device chip cannot be readily distinguished, at least electrically, from a defect-free chip.
Though semiconductor device elements have become increasingly smaller as the minimum feature size of the device elements has decreased, the total area of the device chip may not significantly decrease because of the presence of other elements on the chip whose size cannot be reduced. As an example, the spacing of the programmable fuse elements described above cannot be reduced below a minimum value, typically 1 μm, because of the laser cutting used to “blow” the fuse elements. A minimum spot size is needed for the incident laser beam to deliver sufficient energy to blow the fuse. Though beams having smaller spot sizes are possible by reducing the wavelength of the beam, the energy of the beam is also reduced and may not be sufficient to ensure cutting of the fuse. Moreover, as the spot size approaches the wavelength of the beam, the beam is prone to diffraction so that the beam cannot be focused on the fuse element.
Another device element whose size and/or spacing cannot readily be reduced below a minimum size is the bonding pad. When wire bonds are used, the width of the bonding wires and the size of the solder connections cannot be shrunk without risking breakage of the bonding wires, inadequate solder for the connection or misaligned bonding connections. When the bonding pads directly contact the lead frame, such as for a flip chip device, a minimum spacing between leads is also required.
It is nevertheless desirable to reduce the total area of the chip despite the limitations of fuse size and spacing and bonding pad size and spacing.
The present invention provides a reduction of the total size of the chip by locating the fuses and/or the bonding pads on the backside of the chip and by providing interconnects between circuit elements located on the front side of the chip and the elements located on the backside of the chip.
In accordance with an aspect of the invention, an electronic device is formed in a substrate. A plurality of circuit elements are formed in a first surface of the substrate. The plurality of circuit elements include at least one active circuit element and at least one redundant circuit element. At least one programmable fuse element is formed in a second surface of the substrate. The programmable fuse element stores, when the active circuit element is defective, an indication thereof. At least one interconnect connects the plurality of circuit elements and the fuse element.
According to another aspect of the invention, a memory device is formed in a substrate. Circuit elements are formed in a first surface of a substrate and include active memory cells and redundant memory cells. Programmable fuse elements are formed in a second surface of a substrate and store, when at least one of the active memory cells is defective, an address thereof. A plurality of interconnects connects the plurality of circuit elements and the programmable fuse elements.
According to a further aspect of the invention, an electronic device is formed in a substrate. Circuit elements are formed in a first surface of a substrate. At least one bonding pad is formed in a second surface of a substrate. At least one interconnect connects the plurality of active circuit elements and the bonding pad.
The foregoing aspects, features and advantages of the present invention will be further appreciated when considered with reference to the following description of the preferred embodiments and accompanying drawings.
The DRAM 110 writes data to or reads data from respective memory cells of the memory cell array 105 as a function of received row and column addresses. Specifically, a control circuit (not shown) receives, via an address bus (not shown), the row and column address of at least one cell of the memory cell array 105 that is to be accessed. The control circuit then delivers the row address to a row decoder section 102 that drives a selected word line based on a row address signal and delivers the column address to a column decoder section 103 that drives a selected bit line as a function of a column address signal.
A plurality of fuses 104 is programmed to represent the respective bits of the fail addresses by defining one of a 0 or 1 value as a fuse in a blown or open state, and the other of the 0 and 1 values as a fuse in an unblown or shorted state. When the row decoder section 102 receives a row address or the column decoder section 103 receives a column address that the stored fail address information indicates is defective, the row decoder section 102 or the column decoder section 103 instead activates one or more portions of the redundant bit lines or redundant word lines in place of the defective bit lines or defective word lines.
The known DRAM chip 100 has the disadvantage that the active elements, such as the memory cell array 105, the row decoder section 102 or the column decoder section 103 may be reduced in size as smaller feature sizes are introduced which each new device generation, but the size of the fuse elements 104 cannot be reduced. Because laser cutting is used to “blow” the fuse elements, a minimum spacing is required between the fuse elements because of the finite spot size of the laser beam. Though the spot size of the beam may be reduced, the energy that is applied to the fuse element is also reduced, thereby increasing the possibility that a fuse element is not blown.
Additionally, to store all the fail address values, several-thousand fuse elements may be required on each chip and take up a significant portion of the surface area of the chip that therefore cannot be reduced in size.
The present invention provides a DRAM chip or other device chip in which the fuse elements are provided on the backside of the chip.
The openings through the chip may be generated by any of a number of techniques known in the art, such as chemical etching, laser-assisted etching, electron beam milling or focused ion beam etching. The interconnections through the openings may also be provided using methods known in the art, such as are used for printed circuit boards.
The information stored in the fuse elements 300 is read by sequentially activating each of the input lines 302 and then reading the output generated at one of the output lines 304. As an example, to read the values stored in the uppermost row of fuses 300, an input line connected to the front surface of the chip through the opening 240 is activated, then an input line connected to the opening 242 is activated, an input line connected to the opening 244 is next activated, and thereafter an input line connected to the opening 246 is activated. As each of the input lines 302 is activated, an output is read at the line connected to opening 222. Similarly, the values stored in the second row of fuses are read from the outputs of the line connected to the opening 224, the values stored in the third row of fuses are read from the line connected to the opening 226, the values stored in the fourth row of fuses are read using the line connected to the opening 228, etc. Various circuitry known in the art may be incorporated on the front surface of the chip and connected to these openings to control the reading operation.
Advantageously, the invention allows for reductions in chip size without reducing the size or spacing of the fuse elements or the size or spacing of the bonding pads. As a result, a greater number of chips may be formed on a single wafer without sacrificing processing reproducibility or device reliability.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
