1. Field of the Invention
The present invention relates generally to interconnection devices, and particularly to interconnection devices for mounting high-speed or high-frequency optical-electronic multi-layered assemblies to circuit boards.
2. Technical Background
Rapid advances in technology have accelerated the need for packaging devices which can accommodate, among other factors, connection requirements, higher operating frequencies, such as around 40 GHz, and increases in the numbers of inputs and outputs on integrated circuits (ICs) for optical and electronic circuits. Conventional packaging devices include ball grid arrays (BGA), wire bonding, tape automated bonding (TAB), quad flat packs (QFP) and controlled collapse chip connections (C4 or flip chip). BGA packages tend to be particularly popular because they are easier to surface mount on a printed circuit board than fine pitch peripheral lead packages, such as QFPs. This is because the outer leads of BGA packages are distributed on the lower surface of the package in a matrix, rather than being restricted to the package perimeter and thus being easier to damage. Moreover, since BGA packages do not include peripheral leads, BGA packages take up less room on a printed circuit board, and may be closely spaced. For example, conventional BGA matrices are arranged in linear columns and rows or diagonal lines. This close spacing also allows for shorter interconnect lengths between packages, which results in improved electrical performance.
Conventional packaging technologies, including BGA packages, however, fail to address the specific needs of high frequency integrated optical-electronic assemblies, particularly with respect to providing low loss, reproducible electrical interconnections at the circuit board level for mounting high frequency optical-electronic assemblies. Specifically, known packaging techniques fail to provide the interconnections which would allow high frequency electrical processing, such as signal generation, signal reception, and digital processing or optical processing, such as light modulation, to be combined in a compact space, as in a single circuit board.
Deficiencies can exist with respect to performance in the optical-electronic circuits, particularly at very high frequencies if such interconnections are not properly accommodated. This is because slight variations in signal path impedance may dramatically impact transmission performance. Furthermore, the high frequency interconnection needs to be inexpensive and manufacturable, allowing its use in the commercial market place.
Therefore, there is a need for a low loss, economical device for connecting assemblies on substrate boards which would allow high frequency electrical and optical processing to be combined in a single circuit board.
One aspect of the invention is a pseudo-coaxial vertical transition which includes a substrate. A bump array is disposed in a substantially concentric bump pattern upon the substrate for simulating a pseudo-coaxial vertical electromagnetic wave propagation. The bump array is formed from a centrally disposed bump having a predetermined bump diameter, and a plurality of at least five ground bumps substantially equi-distant and circularly disposed about the centrally disposed bump. The predetermined bump diameter and a bump spacing of the centrally disposed bump are determined in relation to the plurality of ground bumps and a dielectric constant of air for providing a characteristic impedance.
In another aspect, the present invention includes the coupling of the pseudo-coaxial vertical transition to a planar transmission line.
Additional features and advantages of the invention will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the invention as described herein, including the detailed description which follows, the claims, as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description present embodiments of the invention, and are intended to provide an overview or framework for understanding the nature and character of the invention as it is claimed. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate various embodiments of the invention, and together with the description serve to explain the principles and operations of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. One embodiment of the pseudo-coaxial vertical transition of the present invention is shown in
Referring to
“Pseudo-coaxial” for the purposes of this document means that the bumps 32 and 36 are placed in a configuration that resembles a coaxial configuration, whereby the ground bumps 36 are placed in a somewhat ring fashion around the signal or centrally disposed bump 32. “Vertical transition” for the purposes of this document means that the signal flow moves vertically through a flip chip or other substrate or PCB assembly via the bumps 32 and 36. The signal flow may also occur horizontally through various planar transmission lines, forming a “horizontal transition.”
The substrate 16 can be made from any suitable type of materials. Exemplary types of the substrate 16 included a printed circuit board (PCB) or a low temperature co-fired ceramic (LTCC) substrate, which can be a single layer or more practically, a laminated multilayer with DC and AC circuits and transmission lines disposed in various layers.
The bump array simulates a coaxial configuration with a plurality of electrically conductive structures. The electrically conductive structures can be solder balls, conductive resins or polymers.
Circuit lines, including a signal line 18 and ground lines 22, are formed upon the substrate 16, such as on a printed circuit board, in a conventional manner, to provide a characteristic impedance 50 ohms for a transmission line, usable in high speed, high frequency, radio-frequency (RF) or other types of microwave circuits.
The plurality of at least five ground bumps 36 radiate from the centrally disposed bump 32 at about the same radius DAIR/2 for providing the characteristic impedance of about 50 ohms for matching with the transmission line of the substrate 16 and providing a natural ground shield because of the pseudo-coaxial configuration. Hence, in the simple illustrated embodiment of a portion of the microwave circuit, a single signal line 24 is represented functionally to extend vertically through the substrate 16. The solder-ball 32 is positioned between the signal line 24 and the signal line 18 formed upon the printed circuit board 16. The centrally disposed bump or solder-ball 32 forms a vertical signal path permitting conduction of a radio frequency (RF) signal between the signal line 18 and the signal line 24.
To simulate a continuous circle or ring of the outer perimeter of the coaxial configuration, the plurality of ground balls 36 comprises at least five balls substantially circularly, equi-distant, and peripherally spaced around the centrally disposed ball 32. Preferably, the more ground balls 36 there are, the better approximation to a co-axial ring. A plurality, here eight, of ground lines 34, is functionally illustrated in
Bump or solder-balls 36 are positioned between the ground lines 34 and the ground lines 22 formed on the substrate or circuit board 16. The bumps or solder-balls 36 electrically interconnect the ground lines 34 with the ground lines 22. In manners analogous to the radially-separated positions at which the ground lines 34 are formed relative to the signal line 18, the ground bumps or solder-balls 36 are also radially-separated from the signal bump or solder-ball 32. In like fashion, therefore, to the manner by which the ground lines 34 substantially surround the signal line 18, the ground bumps or solder-balls 36 substantially surround the signal bump or solder-ball 32. Thereby, the ground bumps or solder-balls 36 form a shield about the signal bump or solder-ball 32.
During operation of the pseudo-coaxial vertical transition 10 in a circuit device in which a radio frequency (RF) signal is conducted along the signal line 18, through the centrally disposed signal bump or solder-ball 32, and along the signal line 24, electromagnetic energy is generated as a byproduct of such conduction. Because of the shield formed by the positioning of the ground lines 34 to substantially surround the signal line 18 and of the ground bumps or solder-balls 36 to substantially surround the signal bump or solder-ball 32, the electromagnetic energy is shielded by such ground lines and ground bumps or solder-balls 36. The electromagnetic energy is attenuated and interference which might otherwise occur as a result of the emanation of the electromagnetic energy is substantially reduced. Electromagnetic energy generated elsewhere is analogously attenuated and interferes less with conduction of the radio frequency signal.
Referring to
As in
An exemplary radio frequency circuit device of which an embodiment of the present invention forms a portion is thus shown. Embodiments of the present invention may similarly form portions of other circuit devices of other constructions.
The exemplary circuit device includes multiple layers of isolating dielectric materials, here preferably formed of ceramic materials, such as in a multi-layered stack of low temperature co-fired ceramic substrate. The layer 12 is cascaded upon the layer 14. A plurality of circuit elements (not shown) which together form at least portions of an electrical circuit are formed on one or more face surfaces of the layers 12 and 14.
The layer 14, together with the layer 12 cascaded thereupon, is surface-mounted upon a printed circuit board 16 as the first substrate including the signal line 18 and ground lines 22.
In the illustrated embodiment, a single signal line 24 is represented functionally to extend vertically through the layer 14 between a top face surface 26 of the layer 14 and a bottom face surface 28 thereof. A signal line 24 is formed of a via 42 extending through the layer 14.
A solder-ball 32 is positioned between the signal line 24 and the signal line 18 formed upon the printed circuit board 16. The solder-ball 32 forms a signal path permitting conduction of a radio frequency signal between the signal line 18 and the signal line 24.
A plurality, here eight, of ground lines 34, is also functionally illustrated. The lines 34 also extend between the top and bottom face surfaces 26 and 28 of the layer 14 through the vias 44 and coupling with each of the eight solder balls 36. Solder-balls 36 are positioned between the ground lines 34 of the layer 14 and the ground lines 22 formed on the circuit board 16. The solder-balls 36 electrically interconnect the ground lines 34 with the ground lines 22.
No additional traces of an electrically-conductive material, such as a solder material need to surround the ground balls 36, because at least five balls and preferably eight will be sufficient to provide the coaxial ground.
A coating of electrically-conductive material is selectively formed upon the top face surface 26 of the layer 14 of the isolating dielectric material at the output of each of the vias 42 and 44. The coating is applied, for example, by a thick-film plating process. The coating includes a centrally-positioned conductive portion for coating the central or signal via 42 and applied at a location at which the signal line 24 opens at the top face surface 26. Analogously, a plurality of circumferentially-positioned coatings of electrically-conductive material are applied to the ground vias 44 and are formed upon the top face surface 26 at the locations of the top face surface at which the ground lines 34 open at the top face surface. The coated portions of the ground vias 44 are each radially-separated from the coated portion of the signal or central via 42 at a common distance from the coated portion of the signal or central via 42, thereby to be circumferentially-positioned about the coated portion of the signal or central via 42. Thereby, the coated portions of the ground vias 44 substantially surround the coated portion of the central or signal via 42. Hence, each ball 32 or 36 of the ball array is axially and vertically aligned with each via 42 or 44 of the plurality of electrically conductive vias.
While not illustrated in
Multiple numbers of layers, similar to the layers 12 and 14, can be cascaded in manners analogous to the layers 12 and 14. For example, a multi-layered stack of low temperature co-fired ceramic substrates can be laminated together as a unit to form the body portion. Signal paths can similarly be formed to extend through such additional layers of isolating dielectric material.
As in
Referring to
A signal line 18 and ground lines 22 are formed upon the printed circuit board 16. Vias forming a signal line 24 and ground lines 34 are formed to extend through the circuit layer 14, as described previously with respect to the circuit device shown in
The circuit device 300 further includes a centrally-positioned coated portion of the central via 42 and circumferentially-positioned coated portions of the ground vias 44 formed between the layers 12 and 14. The coated portions of the central via 42 and ground vias 44 electrically interconnect the signal line 24 and the ground lines 34, respectively, with corresponding, and here similarly numbered, lines extending through the circuit layer 12.
The coated portions of the central via 42 and the ground vias 44 are formed to be laminated, soldered, or otherwise electrically connected between the other cascaded layers of the circuit device 300. As illustrated, the coated portions of the vias 42 and 44 are interconnected between the circuit layers 12 and 66, between the circuit layers 66 and 68, and between the circuit layers 68 and 72. The circuit layers 66, 68, and 72 also include signal and ground lines 24 and 34 extending therethrough.
Referring to
Referring to
The diameter of the coated portion of the central via 42 has a diameter, d. The radial enclosure formed of the coated portions of the ground vias 44 is defined by a Diameter, D. Appropriate selection of the respective diameters, D and d, permits the characteristic impedance of the combined structure, here forming a connection between the vias 42 and 44 of adjacently-positioned layers. In similar fashion, the solder balls 32 and 36 form a connector assembly connecting lines 24 and 34 to the lines formed on the printed circuit board 16 of
The coated portion of the central via 42 and the radially-extending enclosure of the ground vias 44 are coaxially formed. Because of such a coaxial nature, the assembly, defined of the just-noted manners, exhibits a characteristic impedance defined by the following equation:
Z0=(60/√εr)ln(D/d)
As the equation indicates, the characteristic impedance, Z0, of the connector assembly can be formed to be of any desired value by proper selection of the values of the respective diameters. For instance, if portions of the circuit device of which the connector assembly, however defined, is of a characteristic impedance of 50 ohms, suitable selection of the respective diameters permits the characteristic impedance of the connector assembly also to exhibit a characteristic impedance of 50 ohms. By matching the characteristic impedance, signal loss of the radio frequency signal conducted along a signal line extending through the circuit device is minimized.
Referring to
This top view of the CPW 600 is included in an exemplary embodiment of a flip chip or any other type of multi-layered interconnection assembly. The CPW 600 includes the central conductor 610 which can be linear or have a portion to form a radial transmission line on which is disposed the signal bump or centrally disposed via 42. As in other CPW's, the CPW 600 includes exposed substrate 330 having a gap surrounding the radial transmission line 610. Multiple ground bumps or vias 44 and 644 are arranged around the signal bump or via 42 so as to effect a pseudo-coaxial vertical transmission.
According to the teachings of the present invention, the ground via 644 underneath the signal conductor 610 is not exposed through the signal conductor 610 but is terminated, at a suitable distance, for example twice the gap distance 330, in the dielectric layer beneath the metallic layer of the signal conductor 610. Hence, the interconnection assembly for a co-planar waveguide (CWG) forming a high frequency transmission line has at least one ground substrate via 644 recessed below the signal conductor 610 of the CWG 600 to maintain the circular pattern of the ground vias 44 and 644.
Even though
Referring to
Referring to
The high frequency multilayer circuit structure is formed in such a way that the first to third layer green sheets 111 to 113 are laminated sequentially. Then, the lower ground conductor 702 is formed beneath the first layer green sheet 111, and the upper ground conductors 700 and the CPW signal line conductor 104 are formed on the third layer green sheet 113. Preferably, the CPW signal line conductor 104 is located within a gap between the two upper ground conductors 700.
The vias 44 are formed across the first to third layer green sheets 111 to 113, and are filled or plated with a conductive material. A diameter of each of the vias 106, 44, 42 is preferably about 100 to 200 μm.
However, according to the teachings of the present invention, at least one ground substrate via 106 is recessed below the signal conductor 104 and the lower ground conductor 702 of the CWGG to again maintain the radial pattern of the ground vias 44 and 106. Furthermore, the lower ground conductor 702 has an aperture or otherwise cut-away exposed dielectric area 706 for allowing the central or signal via 42 to be formed across the first to third layer green sheets 111 to 113, and to be filled or plated with a conductive material, without shorting to the ground conductor 702. Hence, the high frequency transmission line is a co-planar waveguide with ground (CWGG) having at least one ground substrate via 106 recessed below the signal conductor 104 and the lower ground conductor 702 of the CWGG, wherein the lower ground conductor has an aperture 706 for allowing the centrally disposed via 42 to protrude to the signal conductor 104.
Referring to
Referring to
The high frequency multilayer circuit structure is formed in such a way that the first to third layer green sheets 111 to 113 are laminated sequentially. Then, the lower ground conductor 702 is formed beneath the first layer green sheet 111, and the micro-strip signal line conductor 104 are formed on the third layer green sheet 113. Preferably, the micro-strip signal line conductor 104 is located at a gap distance above the lower ground conductors 702.
The centrally disposed or signal via 42 is formed across the first to third layer green sheets 111 to 113, and are filled or plated with a conductive material. A diameter of each of the vias 106, and 42 is preferably about 100 to 200 μm.
However, according to the teachings of the present invention, all of the ground substrate vias 106 are recessed below the signal conductor 104 and opens into the lower ground conductor 702 of the micro-strip to again maintain the radial pattern of the ground vias 106. Furthermore, the lower ground conductor 702 has an aperture or otherwise cut-away exposed dielectric area 706 for allowing the central or signal via 42 to be formed across the first to third layer green sheets 111 to 113 to interconnect with the signal conductor 104, and to be filled or plated with a conductive material, without shorting to the ground conductor 702.
Referring to
Referring to
Hence, referring to all of the
To allow design flexibility, circuit routability or the heat dissipation without an additional component of a thermoelectric cooler (TEC), the bumps 32 and 36 and metal through-holes (vias—such as a solid post) 42 and 44 carry signals and ground currents, as well as heat, from a die (not shown) that is mounted on the top surface of layer 12. For example, the die is a high-speed power amplifier or a laser, without a temperature cooler, dissipating excessive heat that would have to be separated from control signals and optical circuits, such as a semiconductor optical amplifier, disposed on the printed circuit board 16 below. The vias 42 and 44 act as electrical and thermal vias. This is important because the device mounted on top heat up in operation, and the preferred package does not have a cooler in it to reduce size and cost. The vias 42 and 44 thus provide a thermal path from the die (that would be mounted on the top side of the LTCC substrate 12, for example) to the bottom of the package (or to wherever the vias 42 and 44 terminate), as in the bumps 32 and 36 disposed on the printed circuit board or substrate 16.
A coaxial-like interconnection is thus formed from a plurality of solder balls configured in an almost circular or ring-like pattern. In prior designs, the solder balls were configured in a 3×3 square array with eight balls or in an attempted circular array with an extra circular trace, with four balls on the printed circuit board. However, because the four balls were still in two linear lines of a much larger matrix, whether diagonal or straight, the pattern formed is still not sufficiently approximating a circle but produced losses as in a square formed from the four corners of the square where each of the balls were selected from the larger matrix.
In contrast, the technology of opto-electronic circuitry is advancing, and hence, the inventors of the present invention overcame the constraining linear matrices of traditional electrical printed circuit boards with a true circular pattern on the bottom substrate or printed circuit board 16. Hence, the coaxial interconnection solder ball grid array includes a single centrally disposed solder ball 32 for interconnecting with a centrally disposed conductor 18 of a coaxial or any other transmission line and a plurality of solder balls 36 surrounding the single centrally disposed solder ball 32, each connected with a coaxial ground shield of the coaxial line 22. The center conductor of the coaxial interconnect is formed via the center ball 32 in a circular pattern of ground balls 36, around the center ball 32 on a substrate 16. Grounding is made by the outer perimeter of balls 36.
The balls' diameters and pitch or spacing has been designed such that these interconnects can be used at high frequencies. These balls 32 and 36 can be varied in size and pitch as long as they maintain 50 ohms. The ball coax can be connected to various microstrip, CPW, and other planar transmission lines and circuit board designs, depending on the application. Hence, a simple way to utilize a circular ball grid array for high speed interconnects by not constraining the printed circuit board or other substrate to have solder balls or solder ball pads arranged in a linear fashion. The resultant integration method allows for a high speed connection to various components within a material structure without changing mediums and with minimal loss.
Hence, according to the teachings of the present invention, a circular patterned BGA (ball grid array)—ceramic substrate coax design is taught that provides improved high speed/frequency performance. For example, in the simulated evaluation of the present invention, for eight ground balls, there were no resonances at 24 GHz and 35 GHz found to increase loss in the inventive circular ground ball/via pattern.
In accordance with the teachings of the present invention, a circular coaxial-style pattern that is normal to the plane of the substrate or PCB material 16 is formed using a combination of plated through or filled vias 42 and 44 and conductive balls (BGA) 32 and 36 that terminate on the top or bottom of the vias 42 and 44 and the interfacing surface of the PCB or substrate 16. The center conductor 18 of the coaxial interconnect is formed with the center ball 32 centered in the circular pattern of the ground balls 36 on the substrate 16. Hence, the ground is formed by the outer perimeter of balls 36.
A main advantage of this invention is that the ball coax concept addresses the cost and size constraints related to conventional “V” or “K” style miniature RF/microwave package connectors and the interface cables and connectors associated with system level interconnects which forces the package to be of a certain size to side-connect with these conventional connectors. In contrast, the inventive BGA-ceramic substrate coax interconnect allows for surface mountable quality high speed interconnections.
The improved structure would be used to unitize the electrical interconnect to a single physical interface. This would permit the final unit to be fully surface mountable.
The present invention teaches how to build controlled impedance interconnects based on predetermined pitch, diameter, and other dimensional parameters of the ball arrays 32 and 36 and substrate via structures 42 and 44. The interconnect uses a “ground fence” design in both the substrate 16 and ball array 32 and 36 to form the outer or ground conductor. Inner conductor balls 32 and vias 42 would also be sized for the desired characteristic impedance. Transitions between the via structures 42 and 44 and external ball 32 and 36 and surface micro-strip, CPW, and other planar transmission line structures are also taught.
The initial High Frequency 3D Electromagnetic Simulation Software (HFSS™) simulations for a Low Temperature Co-fired Ceramic (LTCC) substrate—BGA coaxial interface of the improved structure were started with an LTCC substrate having a specified dielectric constant, an inner conductor ball 32 having a diameter dball of 600 μm, and eight outer “ground fence” balls 36 having a diameter dball of 600 μm, and via diameters d of 200 μm. The axial line of the balls 32 and 36 with the appropriate size, spacing or pitch, line up with the axial line of the vias 42 and 44 coming out of the LTCC layer or other substrate 14.
According to the teachings of the present invention, as partially represented in
The size of the balls can be increased as necessary by simply increasing the radial dimension of the vias in the LTCC. There is, however, a limit. One cannot expect to propagate frequencies in the desired 40 GHz band if one makes the diameter of the “coaxial line” too large. This is due to mode limits of a coaxial waveguide—the frequency bandwidth is inversely proportional to the diameter of the coaxial waveguide or transmission line. With microwave connectors, such as SMA, K and V connectors, the higher the frequency, the smaller the diameter of the coaxial connector; thus, setting the limit on high speed/high frequency lines.
The invention will be further clarified by the following examples.
Referring to
Referring to
Referring to
Referring to
Referring to FIG.
When comparing a four or eight square ground ball structure to the S-parameters of the invented circular structure, exemplified with eight ground balls, there is an improvement in the forward and reflected responses. The eight ground balls of the “square” ground coax has about more than 5 dB of return loss (S11) worse than the inventive eight circular ground ball design, and the insertion loss dB(S21) is about twice as lossy as the inventive eight circular ground ball design. It should be noted that both responses are good enough to work; however, the inventive circular design has improved performance. Also, the “square” ground coax has additional resonances at 24 GHz and 35 GHz that are not present in the inventive circular ground ball/via pattern. Thus, an improved ball coax design results from an eight ground ball circular design.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention. Thus it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.