Claims
- 1. A Combined interface consisting of a low reactance dielectric insert (with the describe pin positions) that is electrically connected to a PCB that consist of third, forth, fifth and sixth RJ45 input terminals arranged in an ordered array, the third and fifth as well as the forth and sixth terminals are positively compensated, and the fifth and sixth as well as the third and forth terminals are negatively compensated, all for the proposed of electrically coupling each of the input terminals to the respective output terminals.
- 2. A Combined interface consisting of a low reactance dielectric insert (with the describe pin positions) that is electrically connected to a PCB that consist of third, forth, fifth and sixth RJ45 input terminals arranged in an ordered array, the third and fifth as well as the forth and sixth terminals are positively compensated, and the fifth and sixth terminals are negatively compensated, all for the proposed of electrically coupling each of the input terminals to the respective output terminals.
- 3. A Combined interface consisting of a low reactance dielectric insert (with the describe pin positions) that is electrically connected to a PCB that consist of third, forth, fifth and sixth RJ45 input terminals arranged in an ordered array, the third and fifth as well as the forth and sixth terminals are positively compensated, and the third and forth terminals are negatively compensated, all for the proposed of electrically coupling each of the input terminals to the respective output terminals.
RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 60/193,563, filed on Mar. 31, 2000, which is incorporated by reference herewith.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60193563 |
Mar 2000 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09825471 |
Apr 2001 |
US |
Child |
10308398 |
Dec 2002 |
US |