Bipolar transistors with depleted emitter

Abstract

This invention disclosed a novel method of fully depleted emitter so that the built-in potential between emitter and the base becomes lower and the charge storage between the emitter and base becomes small. This concept also applies to the diodes or rectifiers. With depleted junction, this result in very fast switching of the diodes and transistors. Another novel structure utilizes the strip base structure to achieve lower on resistance of the bipolar transistor. The emitter region of the strip base can be a normal emitter or depleted emitter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a comparison the charge diagram of normal n−p junction in FIG. 1A versus depleted n−p junction shown in FIG. 1B.

FIG. 2 shows a comparison of the charge diagram of normal n−p junction and depleted n−p junction, FIG. 2A, the potential differences, FIG. 2B, and the energy diagram of the normal and depleted n−p junction, FIG. 2C.

FIG. 3 shows diagram of Js vs Js′ and t vs t′ for normal n−p junction versus the depleted n−p junction.

FIG. 4 shows a vertical bipolar transistor of prior art.

FIG. 5 shows a vertical bipolar transistor with depleted emitter.

FIG. 6 shows a lateral bipolar transistor with depleted emitter.

FIG. 7 shows a vertical bipolar transistor with depleted emitter and base strips.

FIG. 8 shows an IGBT cell diagram of depleted emitter of the bipolar transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiment One

FIG. 1A is a normal charge diagram of an abrupt n−p junction. The total area of qNd×xd1 at n region is equal to qNa×xa1 at p region. Where Nd is the doping concentration of the n region and xa1 is the charge distance of the n region. Where Na is the doping concentration of p region and xa2 is the charge distance of the p region. As the distance xd2 of n region becomes smaller by disclosed methods of the terminators, the total area of qNd×xd2 is smaller than qNd×xd1 with same doping level of Nd as shown in FIG. 1B. In order to balance the total charge, qNa×xa2 is the equal to qNd×xd2. Thus the built-in potential of FIG. 1B is smaller than the built-in potential of FIG. 1A. In order to get good ohmic contact, a very thin layer and heavily doped n type layer is placed at xd2 called the terminator. Otherwise a Schottky contact with reverse diode is connected to the n−p junction. The purpose of this terminator at xd2 is to terminate the n region and also to form the ohmic contact to the metallization. The same theory is also applied to p−n junction. The built-in potential of a normal n−p junction is ranging from less than 0.8 ev to over 0.9 ev for silicon material depending on the doping concentrations of the n−p junction. The depleted n−p junction has the built-in potential from below 0.9 ev to below 0.4 ev. The difference of the built-in potentials of the normal n−p junction to the depleted n−p junction is from lower than 0.01 ev to more than 0.40 ev.

FIG. 2A illuminates the doping concentration diagram of the abrupt n−p junction with normal n−p junction in solid lines versus the depleted n−p junction in dotted lines. As the n side of the n−p junction is terminated earlier by a terminator, the p side charge region will also terminated earlier in order to seek the charge balance. FIG. 2A shows a clear view of FIGS. 1A and 1B. The built-in potential is in the area shown in FIG. 2B. The vertical axis is the electric field and the maximum electric field located at x=0. The normal n−p junction has the built-in potential shown in the solid line triangle area and the depleted n−p junction is shown in dotted line triangle area. FIG. 2C shows the energy diagram of the n−p junction in equilibrium condition, the Fermi energy is shown in a flat dotted line and the conduction band of n type region is connected to the conduction band of p type region via the charge region in both sides of the junction and valence band is connected from the p type region to the valence band of p type region also via the charge region. The key concept to terminate the lightly doped region is to use very thin and heavily doped layer called a terminator to provide the ohmic contact to the metallization layer. This terminator is made by a thin layer of heavily doped region to connected to the fully depleted n type region by using low temperature diffusion or implant or via a very thin layer of poly film with heavily doping by low temperature diffusion without go through the depleted n region. Otherwise a Schottky contact with different polarity to the metallization layer that can not achieve the requirement for a good p−n junction.

FIG. 3 shows the diagram of Js′/Js and t/t′ versus the difference of built-in potential in terms of ev for silicon material. The doping concentration of this Figure is Nd=2E19 cm-3 and Na=1E16 cm-3 for silicon material is used in this Figure as an example, the saturation current density is calculated as Js=8.93E-12 A/cm2. When the n region (emitter) is terminated earlier in fully depleted mode, the depleted mode saturation current Js′ can be approximately shown as Js′=Js exp(q/kT(Vbi-Vbi′)) where Js is the saturation current density of the normal n−p junction of Nd=2E19 cm-3 and Na=1E16 cm-3, Vbi of 0.906 ev is calculated as the built-in potential of the normal n−p junction at room temperature and Vbi′ is the built-in potential of the depleted n−p junction as shown in FIG. 2B. In FIG. 3 t is the effective lifetime of the normal n−p junction and t′ is the effective lifetime of the depleted n−p junction. The x axis of FIG. 3 is the difference of the built-in potential of the normal n−p junction to the built-in potential of the depleted n−p junction. As x axis moves to right, the fully depleted n−p junction has smaller built-in potential, the space charge region is smaller, the effective life time becomes much smaller thus the bipolar transistor speed becomes faster. The saturation current density becomes larger when the built-in potential is smaller as shown in the equation and this diagram. Thus the depleted n−p junction can approach to Schottky rectifier's performance.

Embodiment Two

FIG. 4 shows a standard vertical bipolar transistor in the prior art. Layer 101 is a heavily doped substrate. Layer 100 is a lightly doped epitaxial layer with the same polarity as the substrate. Later 102 is the layer of opposite polarity of the epitaxial layer as the base of the bipolar transistor. Layer 103 is a heavily doped layer with the opposite polarity as the layer 102 and with the same polarity as the layer 100. Layer 104 is a heavily doped with the same polarity as the layer 102. This layer 104 serves as the ohmic contact to the base layer 102 and the metal layer 107 as the base terminal. Later 105 is the oxide layer to be formed either by thermal oxidation or CVD or both. Layer 106 is the metallization for the emitter contact. Layer 106 and layer 107 can be form either by Aluminum layer for wire bond or the NiAu layers on the top of Aluminum layer for the solder joint or other metallization layers. Layer 108 is a metallization layer that can be formed either by TiNiAg films, CrAu films or nickel plating. This layer 108 is used for the collector terminal to be soldered onto the package.

FIG. 5 is the same as the FIG. 4 except the layer 103A is a depleted region with the polarity opposite to the layer 102 as described in FIGS. 1, 2 and 3. This layer 103A can be higher, slightly high or even lower doping concentration with the opposite polarity to the layer 102. Layer 103A is very thin so that the depletion layer is fully depleted and in this condition the built-in voltage between emitter and the base is less than the full built-in potential as described in FIG. 2A. A terminator of very low implant energy and moderate dose to provide heavy surface concentration is implanted on the top of layer 103A to the emitter region. The implant dose for the region 103A is from 1.0E11 to 1.0E14 with the energy from less than 100V to over 10 KV. The terminator of 103A requires the implant dose from 1.0E12 to 1.0E15 with the implant energy from less than 100V to over 1000V. The terminator can also use low temperature diffusion with the same polarity of 103A from 700 deg C. to over 1100 deg C. with time from over two hours to less than 30 seconds. The implant anneal temperature can be performed from 1150 deg C. to 600 deg C from less than 10 sec to 30 min. The terminator can also use a thin layer of poly silicon film on the top of 103A and completed by diffusion of low temperature or implant by low and moderate dose and energy described above. The thermal process of the terminator must not drive the doping to go through the layer 103A to become normal n+p junction. Due to fully depleted layer of 103A, the charge storage is thus reduced compared with n+p junction. With the reduced emitter to base charge, the transistor is thus faster compared with standard emitter to base junction as illustrated in FIGS. 2 and 3. The same theory also applies top type emitter to n type base junction.

Embodiment Three

FIG. 6 is a lateral bipolar transistor with depleted emitter region 103A. Layer 101 is a heavily doped with the different polarity with the substrate 102A and same polarity as the epi layer 100. The buried layer 101 is formed by diffusion before the epitaxial layer 100 deposition. The epitaxial layer 100 is the same polarity of the substrate 102A. The structure 101A is formed by deep diffusion of the same polarity as the epi layer 100. Layer 104 is a heavily doped layer with the same polarity as the layer 102 for the ohmic contact to the base region. The metallization of 106 and 107 is generally an Aluminum layer. The region 106 is the emitter, 107 is the base and 108 is the collector. This layer 103A can be higher, slightly high or even lower doping concentration with the opposite polarity to the layer 102. Layer 103A is very thin so that the depletion layer is fully depleted and in this condition the built-in voltage between emitter and the base is less than the full built-in potential as described in FIGS. 1A and 1B. A terminator of very low implant energy and moderate dose to provide heavy surface concentration is implanted on the top of layer 103A to the emitter region. The implant dose for the region 103A is from 1.0E11 to 1.0E14 with the energy from less than 100V to over 10 KV. The terminator of 103A requires the implant dose from 1.0E12 to 1.0E15 with the implant energy from less than 100V to over 1000V. The terminator can also use low temperature diffusion from 700 deg C. to over 1100 deg C. with time from over two hours to less than 30 seconds. The implant anneal temperature can be performed from 1150 deg C. to 600 deg C. from less than 10 sec to 30 min. The terminator can also use a thin layer of poly silicon film on the top of 103A and completed by diffusion of low temperature or implant by low and moderate dose and energy. The thermal process of the terminator must not drive the doping to go through the layer 103A to become normal n+p junction. Due to fully depleted layer of 103A, the charge storage is thus reduced compared with n+p junction. With the reduced emitter to base charge and capacitance, the transistor is thus faster compared with standard emitter to base junction as illustrated in FIGS. 2 and 3. The same theory also applies to p type emitter to n type base junction.

FIG. 7 is a novel structure of the bipolar transistor on the side view. The emitter region 103A is a fully depleted or incomplete region as shown in FIG. 2 and 3. The base layer 102 is a strip structure with the gap x small enough that the depletion layer of 102 in the epi region 100 is extended to cover this gap. When the base voltage is zero or negative voltage against the emitter and collector, this structure is looking like a standard bipolar transistor. When the base voltage is forward biased to the emitter and the base, the transistor is looking like the JFET. This thus reduced the conduction resistance compared with the bipolar transistor. Since the reduction of the emitter to base capacitance and charge, this structure is faster than the comparable bipolar transistors. The layer 102C is heavily doped region with the same polarity as the layer 102 for the ohmic contact to the base metal. Layer 107 is the base contact and 106 is used for the emitter contact. The metallization of 106 and 107 can be done by Aluminum layer for wire bond or with NiAu plating on the top of Aluminum for soldering bond. Layer 108 is the bottom metallization layer for the collector terminal. This metallization is generally to be done by TiNiAg, CrAu or by simple nickel plating. Again, the layer 103A can be higher, slightly high or even lower doping concentration with the opposite polarity to the layer 102. Layer 103A a depleted layer of emitter region and in this condition the built-in voltage between emitter and the base is less than the full built-in potential as described in FIG. 2A. A terminator of very low implant energy and moderate dose to provide heavy surface concentration is implanted on the top of layer 103A to the emitter region. The implant dose for the region 103A is from 1.0E11 to 1.0E14 with the energy from less than 100V to over 10 KV. The terminator of 103A requires the implant dose from 1.0E12 to 1.0E15 with the implant energy from less than 100V to over 1000V. The terminator can also use low temperature diffusion from 700 deg C. to over 1100 deg C. with time from over two hours to less than 30 seconds. The implant anneal temperature can be performed from 1150 deg C. to 600 deg C. from less than 10 sec to 30 min. The terminator can also use a thin layer of poly silicon film on the top of 103A and completed by diffusion of low temperature or implant by low and moderate dose and energy. The thermal process of the terminator must not drive the doping to go through the layer 103A to become normal n+p junction. Due to fully depleted layer of 103A, the charge storage is thus reduced compared with n+p junction. With the reduced emitter to base charge, the transistor is thus faster compared with standard emitter to base junction as illustrated in FIGS. 2 and 3. The same theory also applies to p type emitter to n type base junction.

Embodiment Four

FIG. 8 shows an IGBT cell structure with depleted emitter for the fast response. For example, the substrate 101 is a heavily doped p type material as the collector. Epitaxial layer 100 is served as the base which is in opposite polarity of the substrate 101. The gate region 105 can be a doped poly layer or a silicide layer. The gate oxide 106 can be formed by thermal oxidation and layer 106A is a CVD oxide to serve an insulation layer around the gate 105. Layer 102A is a depleted region with opposite polarity of the base region. The built-in potential of 102A to base 100 has lower built-in potential compared with the normal p−n junction. Thus the fast bipolar transistor speed can be reached. The layer 102 connected to layer 102A is a normal doped p region to serve as the base for the conduction channel of the MOSFET between the 103, n+, layer to the n type base or drift region. A thin and heavily doped terminator is place between 102A and the emitter metallization 107. The terminator is described in FIGS. 5, 6, and 7. The metallization layer 107 is usually a thick Aluminum layer for the wire bond or a layer of NiAu on top of Aluminum layer for the soldering. The metallization layer 108 can be TiNiAg, CrAu, or Ni plating for the soldering of the device to the package.

Claims

1. For any n−p or p−n junction, diode, or rectifier with depleted region in one side of the junction that results in lower built-in potential of the junction. The lowered built-in potential is ranging from 0.01 ev to over 0.40 ev for silicon material.

2. The depleted region can be in the heavily or lighter doping side of the junction.

3. The terminator at the depleted region to provide the good ohmic contact and the elimination of Schottky effect is done by a) A very thin and heavily doped region of the same polarity of the depleted side of the junction has the doping concentration to over 1E18 cm-3 and the thickness is from less than 10 nm to over 100 nm. This layer can be formed either by the implantation or by the diffusion. This layer must not overtake the doped depleted region, orb) Low temperature diffusion with short diffusion time with the same polarity is performed on the top of depleted layer region. The diffusion source can be either by ion implantation, gas or liquid source. The temperature of the diffusion is from 650 deg C. to 1150 deg C. and the time is from 2 hours to less than 10 seconds. This diffusion process must not overtake the depleted region, orc) Use of low temperature diffusion with short diffusion time with opposite polarity to directly form the depleted junction to the base material. The diffusion source can be either by ion implantation, gas or liquid source. The temperature is ranging from 650 deg C. to 1150 deg C. and the time is from 2 hours to less than 10 seconds. A thin layer of poly silicon can also be used as the buffer layer in this case, ord) Use of a thin layer of polysilicon film as a buffer layer on the top of depleted region following by implant or diffusion. Low temperature diffusion with short diffusion time with the same polarity is performed on the top of depleted layer region. The diffusion source can be either by ion implantation, gas or liquid source. The temperature of the diffusion is from 650 deg C. to 1150 deg C. and the time is from 2 hours to less than 10 seconds. This diffusion process must not overtake the depleted region.

4. The use of depleted layer with the terminator disclosed in claim 3 at the emitter area of a bipolar transistor. This is called depleted emitter. The built-in potential difference of the emitter to the base region compared with the depleted emitter to the base region is from less than 0.01 ev to over 0.4 ev. Same condition is applied to p−n emitter to base junction.

5. Claim 4 applies to all kinds of bipolar transistors including vertical structure, lateral structure, discrete bipolar transistors as well as the bipolar transistor with depleted emitter in integrated circuits.

6. Claim 4 also applies to IGBTs.

7. Strip shape of base region with small distance between the strips so that the depletion region from the base filled up all the distance between base distance and the base strips are normally off when the base bias is zero. The distance and the doping concentration between the gap determines the threshold voltage of the parasitic JFET region. The emitter region in this claim can be a normal emitter or depleted emitter.

8. claims 1 to 7 also apply to other semiconductors such as Ge, GaAs, SiC, and others materials such as SiGe. The built-in potential difference of the depleted junction and the normal junction will be varied with different materials.