Claims
- 1. A digital multiplier for multiplying together two digit-serial operands, one a multiplicand W bits in length and the other a multiplier, each digit in said operands being n bits in length, n being a plural integer that is a submultiple of W, said digital multiplier comprising:
- an array of multiplier cells arranged in n rows and W columns;
- a respective row bus associated with each row of cells in a manner particularly set forth hereinafter in this claim, said row busses being identified by consecutive ordinal numbers first through n.sup.th ;
- a respective column bus associated with each column of cells in a manner particularly set forth hereinafter in this claim, said column busses being identified by consecutive ordinal numbers first through W.sup.th ;
- a respective single-bit by single-bit digital multiplying circuit included in each said multiplier cell for multiplying together the bits on the row bus and the column bus associated with that multiplier cell to generate a respective single-bit product, said multiplying together of bits on said row bus and said column bus by each said digital multiplying circuit establishing the association of those two busses with said multiplier cell in which that said digital multiplying circuit is included;
- a respective adder included in each of said multiplier cells, having a respective first input port connected to said digital multiplying circuit included in the same multiplier cell to receive its respective single-bit product, having a respective second input port, and having respective first and second output ports for supplying a carry bit portion and a sum bit portion respectively of the two-bit full sum of the addends received at its input ports, each said adder included in any said multiplier cell located in a column other than said first column having a respective third input port;
- a respective connection of the first output port of each said adder in any said multiplier cell in any said row other than the n.sup.th row to the second input port of the adder included in the multiplier cell located in the succeeding row and in the same column; and
- a respective connection of the second output port of each said adder in any said multiplier cell in any said row other than said n.sup.th row and in any said column other than said W.sup.th column to the third input port of the adder included in the multiplier cell located in the succeeding row and the succeeding column, said digital multiplier being arranged for digit-serial operation and further comprising:
- a digit-serial-in/parallel-out register, receptive of said digit-serial multiplicand a digit at a time during each of a first series of clock intervals for storing all the bits of said multiplicand and applying them in order of decreasing significance to the first through W.sup.th column busses respectively;
- means for applying, during each of a second series of clock intervals, following said first series of clock intervals, the bits of a successive digit of said digit-serial multiplier in order of increasing significance to the first through n.sup.th row busses respectively;
- means for respectively applying, during each clock interval in said second series except the first, the carry appearing the previous clock interval at the first output ports of the adders in the n.sup.th row of multiplier cells to the second input ports of adders in the first row of multiplier cells and in corresponding columns of the array of multiplier cells;
- means for respectively applying during each clock interval in said second series after the first, the sum bits appearing in the previous clock interval at the second output ports of the adders in the entire n.sup.th row of multiplier cells, except the adder in the W.sup.th column, to the third input ports of adders in the first row of multiplier cells and in columns of the array of multiplier cells with next higher ordinal number;
- means for applying zeroes to the second and third input ports of the adders in said first row of multiplier cells during said first series of clock intervals, and during the first clock interval in said second series of clock intervals;
- means for providing a minor product output signal in digit-serial form from the second output ports of the adders in the W.sup.th column of multiplier cells; and
- means for providing a major product output signal in digit-serial form; which means includes:
- a first parallel-in/digit-serial-out register having W successive stages loaded in parallel with carry bits from the first output ports of adders in successive columns of said n.sup.th row of multiplier cells during the last of said second series of clock intervals;
- means for shifting the contents of said first parallel-in/digit-serial-out register one stage towards an output port thereof during each succeeding clock interval of a third series of clock intervals following said second series of clock intervals;
- a second parallel-in/digit-serial-out register having n successive stages loaded in parallel with sum bits from the second output ports of adders in successive columns of said n.sup.th row of multiplier cells during the last of said second series of clock intervals;
- means for shifting the contents of said second parallel-in/digit-serial-out register one stage towards an output port thereof during each succeeding clock interval of said third series of clock intervals;
- means for delaying the shifted carry portions one clock interval respective to the shifted sum portions; and
- a digit-serial adder for adding the delayed shifted carry bits to the shifted sum bits to generate said major product output signal in digit-serial form.
- 2. A digit-serial multiplier as set forth in claim 1 included in an arrangement for performing successive multiplications, wherein the first series of clock intervals for each multiplication except the initial one overlaps at least the finishing portion of the second series of clock intervals for the preceding multiplication.
- 3. A digit-serial multiplier as set forth in claim 2 wherein the third series of clock intervals for each multiplication except the final one overlaps at least the beginning portion of the second series of clock intervals for the succeeding multiplication.
- 4. A digit-serial multiplier as set forth in claim 1 included in an arrangement for doing successive multiplications, wherein the first series of clock intervals for each multiplication except the initial one overlaps at least the finishing portion of the second series of clock intervals for the preceding multiplication, and wherein the third series of clock intervals for each multiplication except the final one overlaps at least the beginning portion of the second series of clock intervals for the succeeding multiplication.
- 5. A parallel-in digit-serial-out register for words of W bits supplied as m successive digits of n-bits each, m and n being positive plural integers, and W being the integer equal to m times n, said parallel-in digit serial-out register comprising:
- an n-bit-wide output port for delivering digit-serial output signals each digit of which has n bits therein;
- a respective pipeline for each bit of said digit-serial output signals preceding said output port, said pipelines identified by consecutive ordinal numbers first through n.sup.th ;
- a plurality W in number of input ports for receiving in parallel the bits of a digit-serial word, said input ports identified by consecutive ordinal numbers first through W.sup.th in order of the significance of the bit respectively applied thereto;
- a plurality W in number of multiplexers consecutively ordinally numbered zeroeth through (W-1).sup.th having respective first input connections to the input port similarly ordinally numbered, having respective second input connections, and having respective output connections, each said multiplexer having between the second input connection and the output connection thereof a respective selective path which is included in the pipeline having the same ordinal number modulo n that that one of said multiplexers has, the multiplexers thus included in each pipeline being arranged in order of ordinal number between the beginning end and the output port end of that pipeline;
- a number W of latches, m latches of which are included in each pipelined with one of the m latches being included at one end of said pipeline and the other of the m latches respectively connecting the output connection of each said multiplexer included in that pipeline to the second input connection of the following said multiplexer included in that pipeline;
- means for clocking in parallel once a clock interval said latches in said number W thereof;
- means for controlling said multiplexers to discontinue the selective paths therewithin only during selected clock intervals separated by at least (m-1) intervening clock intervals, and to provide instead during said selected clock intervals selective paths from the first input connections of said multiplexers to their output connections respectively; and
- means for arranging said multiplexers to be in respective iterations of an iterative monolithic integrated-circuit structure, including
- a braiding of said pipelines from latch to latch.
- 6. A monolithic integrated circuit including a first and a second of said parallel-in/digit-serial-out registers as set forth in claim 5 in combination with:
- a digit-serial adder having a first input port to which the output port of said first parallel-in/digit-serial-out registers connects, having a second input port to which the output port of said second parallel-in/digit-serial-out register connects, and having an output port.
- 7. A combination as set forth in claim 6 wherein each of the pipelines of said first parallel-in/digit-serial-out register has said one of the m latches therein at its beginning end and wherein each of the pipelines of said second parallel-in/digit-serial-out register has said one of the m latches therein at its output port end.
- 8. A combination as set forth in claim 7 on the same monolithic integrated circuit with a W-column-by-n-row array of multiplier cells, each of the multiplier cells in the last row of the array providing sum bits to the first through W.sup.th input ports of said first parallel-in/digit-serial-out register and providing carry bits to the first through W.sup.th input ports of said second parallel-in/digit-serial-out register.
- 9. A digit multiplier for multiplying together two digit-serial operands, one a multiplicand W bits in length and the other a multiplier mn bits in length, each digit in said operands being n bits in length, m being a positive integer and n being a positive plural integer that is a submultiple of W, said digital multiplier comprising:
- a plurality n times W in number of multiplying circuits each having respective first and second single-bit-wide input ports and having a respective single-bit-wide output port, said plurality of multiplying circuits being grouped into n groups respectively identified by consecutive ordinal row numbers first through n.sup.th, each of which groups consists of a respective number W of multiplying circuits respectively identified by consecutive ordinal column numbers first through W.sup.th, whereby a respective one of said multiplying circuits is uniquely identified by each pair of row and column numbers;
- a plurality, n in number, of row busses respectively identified by consecutive ordinal row numbers first through n.sup.th, each row bus connecting to the first input ports of those of said multiplying circuits in the one of said n groups identified by the same ordinal row number as that row bus;
- a plurality, W in number, of column busses respectively identified by consecutive ordinal column numbers first through W.sup.th, each column bus connecting to the second input ports of those of said multiplying circuits identified by the same ordinal column number as that column bus;
- a plurality, n times W in number, of adders being grouped into n groups, respectively identified by consecutive ordinal row numbers first through n.sup.th, each of which groups consists of a respective number W of adders respectively identified by consecutive ordinal column numbers first through W.sup.th, whereby a respective one of said adders is uniquely identified by each pair of row and column numbers, each said adder having a respective first input port to which connects the output port of said multiplying circuit identified by the same pair of row and column numbers, each said adder having a respective second input port, each said adder except each identified by first column number having a respective third input port, each said adder having first and second output ports for supplying a carry bit portion and a sum bit portion respectively of a two-bit full sum of bits received at its input ports, the first output port of each said adder identified by a row number other than n.sup.th connecting to the second input port of said adder identified by the same column number and a row number one higher, the second output port of each said adder identified both by a row number other than n.sup.th and by a column number other than W.sup.th connecting to the third input of said adder identified by the next higher row and column numbers;
- means for providing a minor product output signal in digit-serial form from the second output ports of said adders identified by W.sup.th column number; and
- means for providing a major product output signal in digit-serial form; which means includes:
- a first parallel-in/digit-serial-out register having W successive stages loaded in parallel during the last of said second series of clock intervals with carry bits from the first output ports of said adders identified by said n.sup.th row number and by each of said column numbers;
- means for shifting the contents of said first parallel-in/digit-serial-out register one stage towards an output port thereof during each succeeding clock interval of a third series of clock intervals following said second series of clock intervals;
- a second parallel-in/digit-serial-out register having n successive stages loaded in parallel during the last of said second series of clock intervals with sum bits from the second output ports of said adders identified by said n.sup.th row number and by each of said column numbers;
- means for shifting the contents of said second parallel-in/digit-serial-out register one stage towards an output port thereof during each succeeding clock interval of said third series of clock intervals;
- means for delaying the shifted carry portions one clock interval respective to the shifted sum portions; and
- a digit-serial adder for adding the delayed shifted carry bits to the shifted sum bits to generate said major product output signal in digit-serial form.
- 10. A digit-serial multiplier as set forth in claim 9 included in an arrangement for performing successive multiplications, wherein the first series of clock intervals for each multiplication except the initial one overlaps at least the finishing portion of the second series of clock intervals for the preceding multiplication.
- 11. A digit-serial multiplier as set forth in claim 10 wherein the third series of clock intervals for each multiplication except the final one overlaps at least the beginning portion of the second series of clock intervals for the succeeding multiplication.
- 12. A digit-serial multiplier as set forth in claim 9 included in an arrangement for doing successive multiplications, wherein the first series of clock intervals for each multiplication except the initial one overlaps at least the finishing portion of the second series of clock intervals for the preceding multiplication, and wherein the third series of clock intervals for each multiplication except the final one overlaps at least the beginning portion of the second series of clock intervals for the succeeding multiplication.
- 13. A digit-serial multiplier as set forth in claim 9 wherein each said multiplying circuit is a respective AND gate.
- 14. A method of performing digit-serial multiplication of a multiplicand signal by a multiplier signal, by iteratively using a combinational array multiplier composed of (1) a plurality of multiplier cells connected in an n successive row by W successive columns array, for generating a minor product n bits at a time from the column of said array receiving the least significant bit of said multiplicand signal, and for generating W uncombined sum bits and W uncombined carry bits of different weights defining a major product which are supplied from the row of said array receiving the most significant bit of said multiplier signal, each multiplier cell including a respective digital multiplier and subsequent adder, and (2) means for generating a major product by combining the uncombined sum and carry bits of different weights defining it, as supplied from the row of said array receiving the most significant bit of said multiplier signal, n being a plural positive integer and W being a positive multiple thereof, said method comprising the steps of:
- applying the W bits of a multiplicand signal in parallel to respective ones of said columns of multiplier cells in said combinational array multiplier, thereby to supply multiplicand bits to the digital multipliers in said multiplier cells;
- applying the mn bits of a multiplier signal, in m successive digits of n bits applied in parallel to respective ones of said rows of multiplier cells in said combinational multiplier, thereby to supply multiplier bits to the digital multipliers in said multiplier cells, m being a positive plural integer;
- applying during the first (m-1) digits of said multiplier signal the uncombined bits of said major product with appropriate bit place shifts as carries to said adders in the row of said array receiving the least significant bit of said multiplier signal, thereby continuing multiplication to extend said minor product to m digits of n bits width; and
- after the m.sup.th digit of said multiplier signal, generating said major product by combining the uncombined sum and carry bits of different weights defining it, as supplied from the row of said array receiving the most significant bit of said multiplier signal.
Parent Case Info
This is a continuation-in-part of U.S. Pat. application No. 231,937, filed August 15, 1988, and now abandoned.
US Referenced Citations (3)
Non-Patent Literature Citations (2)
Entry |
J. P. Hayes, Computer Architecture and Organization, 2nd Ed., .COPYRGT.1988, 1978, McGraw Hill, Inc., pp. 246-248. |
J. E. Robertson, "Two's Complement Multiplication in Binary Parallel Digital Computers", IRE Transactions on Electronic Computers, vol. EC-4, Sep. 1955, pp. 118-119. |
Continuation in Parts (1)
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Number |
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231937 |
Aug 1988 |
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