Patent Application
20190279990
The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a two-port static random access memory bitcell and methods for forming a two-port static random access memory bitcell.
Static random access memory (SRAM) may be used, for example, to temporarily store data in a computer system. When continuously powered, SRAM retains its memory state without the need for data refresh operations. An SRAM device includes an array of bitcells and each bitcell retains a single bit of data during operation. Each SRAM bitcell may include a pair of cross-coupled inverters and a pair of access transistors connecting the inverters to complementary bit lines. The two access transistors are controlled by word lines, which are used to select each individual SRAM cell for read or write operations.
A two-port SRAM is implemented with an additional pair of transistors that allows multiple read or write operations to occur at, or nearly at, the same time. In a typical 2CPP-wide two-port SRAM bitcell, the additional access transistor and pull-down transistor of the read port are both placed at one side of the bitcell. This layout for the access transistor and pull-down transistor contributes to increasing the cell height and, thereby, increases the aspect ratio of the two-port SRAM. The increase in the aspect ratio impacts the performance and the yield due to the increase in the word line resistance. Consequently, the size of a block in the circuit design may be limited by restricting the maximum number of bits/wordline.
In an embodiment, a structure is provided for a bitcell of a two-port static random-access memory. The structure includes a storage element including a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) vertical-transport field-effect transistor (VTFET) with a fin that is aligned in a first row with the fin of the first PU VTFET, a second pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, and a second pull-down (PD) vertical-transport field-effect transistor (VTFET) with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port access (RPG) vertical-transport field-effect transistor (VTFET) with a fin and a read port pull-down (RPD) vertical-transport field-effect transistor (VTFET) with a fin that is aligned in a third row with the fin of the RPG VTFET.
In an embodiment, a method of forming a structure for a bitcell of a two-port static random-access memory is provided. The method includes forming a first pull-up (PU) vertical-transport field-effect transistor (VTFET) and a first pull-down (PD) vertical-transport field-effect transistor (VTFET) of a storage element that include respective first fins aligned in a first row, and forming a second pull-up (PU) vertical-transport field-effect transistor and a second pull-down (PD) vertical-transport field-effect transistor (VTFET) of the storage element that include respective second fins aligned in a second row. The method further includes forming a read port access (RPG) vertical-transport field-effect transistor (VTFET) and a read port pull-down (RPD) vertical-transport field-effect transistor (VTFET) of a read port that include respective third fins aligned in a third row.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
With reference to
Shallow trench isolation regions 24 formed in the substrate 22 operate to electrically isolate the different bottom source/drain regions 18, 20 from each other. The shallow trench isolation regions 24 may be formed with a lithography and etching process to define trenches in the substrate 22, and filling the trenches with a dielectric material, such as an oxide of silicon (e.g., silicon dioxide (SiO2)) or other electrical insulator, deposited by chemical vapor deposition (CVD).
The fins 10-17 may be formed from semiconductor material, such as the semiconductor material of the substrate 22, patterned using photolithography and etching processes, such as a sidewall imaging transfer (SIT) process or self-aligned double patterning (SADP), and cut into given lengths in the layout. The fins 10-17 are used to construct different single-fin vertical-transport field-effect transistors (VTFETs) of a two-port static random access memory (SRAM) as described hereinbelow. Fins 10 and 11 are aligned in a row with fin 16. Fin 10 may be used to form a pull-down (PD) VTFET, fin 11 may be used to form a pass-gate (PG) VTFET for read or write operations, and fin 16 may be used to form a pull-up (PU) VTFET. Fins 12 and 13 are aligned in a row with fin 17. Fin 12 may be used to form a pass-gate (PG) VTFET for read or write operations, fin 13 may be used to form a pull-down (PD) VTFET, and fin 17 may be used to form a pull-up (PU) VTFET. Fin 14 is aligned in a row with fin 15. Fin 14 may be used to form a read port access (RPG) VTFET and fin 15 may be used to form a read port pull-down (RPD) VTFET. In an embodiment, a two-port SRAM formed using the fins 10-17 may have a three contacted (poly) pitch (3CPP) structure relating to the arrangement of the subsequently-formed gates in association with the fins 10-17. The different rows of fins 10, 11, 16, fins 12, 13, 17, and fins 14, 15 are arranged parallel to each other in the 3CPP structure.
In connection with the formation of n-type vertical-transport field-effect transistors, the bottom source/drain regions 18 may be include an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P) and/or arsenic (As)) that provides n-type electrical conductivity. In connection with the formation of p-type vertical-transport field-effect transistors, the bottom source/drain regions 20 may include a p-type dopant from Group III of the Periodic Table (e.g., boron (B), aluminum (Al), gallium (Ga), and/or indium (In)) that provides p-type electrical conductivity.
With reference to
A gate stack 30 is arranged over the bottom spacer layer 26 and may surround all sides of each of the fins 10-17 in a gate-all-around (GAA) arrangement. The gate stack 30 may include one or more conformal barrier metal layers and/or work function metal layers, such as layers composed of titanium aluminum carbide (TiAlC) and/or titanium nitride (TiN), and a metal gate fill layer composed of a conductor, such as tungsten (W). The layers of gate stack 30 may be serially deposited by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD), over the fins 10-17 and may be etched back by chamfering to a given thickness. A gate dielectric layer (not shown) is arranged between the gate stack 30 and the fins 10-17 and bottom spacer layer 26. The gate dielectric layer may be composed of a high-k dielectric material, such as a hafnium-based dielectric material like hafnium oxide (HfO2) deposited by atomic layer deposition (ALD).
Sections of a top spacer layer 28 are arranged about the fins 10-17 and over the gate stack 30. The top spacer layer 28 may be composed of a dielectric material, such as silicon nitride (Si3N4), that is deposited by a directional deposition technique, such as high-density plasma (HDP) deposition or gas cluster ion beam (GCIB) deposition. The fins 10-17 extend in the vertical direction through the thickness of the top spacer layer 28 and may project a given distance above the top spacer layer 28.
With reference to
The etch mask 31 is a composite etch mask in which the light-sensitive material is exposed to provide a pattern that, after developing, includes sections 32, 34 of the light-sensitive material covering underlying sections of the gate stack 30. The sections 32, following etching, are used to provide gate extensions contacting the gates from which they respectively extend and gate extensions that provide cross-couplings between the gates of each PU VTFET and PD VTFET pair. The section 34 of the etch mask 31 covers an underlying section of the gate stack 30 that, following etching, is used to provide a connection between the gate of the RPD VTFET associated with fin 15 and the gate of the adjacent PU VTFET associated with fin 17. The discrete sections 32 and 34 of the etch mask 31 are disconnected and spaced from each other.
Before developing, the etch mask 31 is modified to add another component in which the light-sensitive material is exposed to provide a pattern that, after developing, introduces cuts 42 as a set of parallel openings in the etch mask 31. The cuts 42 introduce longitudinal cuts into the gate stack 30 that disconnect the gates of most of the VTFETs, as well as disconnect the gates of the two-port SRAM bitcell from the gates of surrounding two-port SRAM bitcells. An exception to the disconnection of the gates of the VTFETs is that one of the cuts 42 of the etch mask 31 is interrupted across the section 34 of the etch mask 31 so as to preserve the integrity of the section 34 between the gate of the RPD VTFET associated with fin 15 and the gate of the adjacent PU VTFET associated with fin 17 in the middle row.
The etch mask 31 is overlaid on the sections of the top spacer layer 28 respectively associated with the fins 10-17. These sections of the top spacer layer 28 mask underlying equal-size sections of the gate stack 30 respectively associated with the fins 10-17, which form the gates of the VTFETs and are protected and preserved during the etching process that patterns the gate stack 30.
With reference to
The patterned gate stack 30 includes a gate 50 that is wrapped about and surrounds the fin 10 that is used to form a pull-down (PD) vertical-transport field-effect transistor (VTFET) 60, a gate 51 that is wrapped about and surrounds the fin 11 may be used to form a pass-gate (PG) VTFET 61, and a gate 56 that is wrapped about and surrounds the fin 16 may be used to form a pull-up (PU) VTFET 66. The patterned gate stack 30 further includes a gate 52 that is wrapped about and surrounds the fin 12 used to form a pass-gate (PG) VTFET 62, a gate 53 that is wrapped about and surrounds the fin 13 used to form a pull-down (PD) VTFET 63, and gate 57 that is wrapped about and surrounds the fin 17 may be used to form a pull-up (PU) VTFET 67. The patterned gate stack 30 further includes a gate 54 that is wrapped about and surrounds the fin 14 used to form read port access (RPG) VTFET 64, and a gate 55 that is wrapped about and surrounds the fin 15 may be used to form a read port pull-down (RPD) VTFET 65. In an embodiment, a two-port SRAM formed using the fins 10-17 may have a three contacted (poly) pitch (3CPP) structure relating to the arrangement of the subsequently-formed gates in association with the fins 10-17. The gates 50-57 are covered by the respective sections of the top spacer layer 28. The gate 57 of the PU VTFET 67 is integral with the section 38 of the gate stack 30, and the gate 55 of the RPD VTFET 65 is also integral with the section 38 of the gate stack 30 such that the gate 55, the gate 57, and the section 38 are a single monolithic piece of the gate stack 30.
With reference to
With reference to
The storage element of the two-port SRAM 80 includes the PD VTFET 60, the PU VTFET 66 that forms an inverter with the PD VTFET 60, the PD VTFET 63, and the PU VTFET 67 that forms an inverter with the PD VTFET 63. These inverters are cross-coupled using the abutting bottom source/drain regions 18, 20 of the VTFETS 60, 66 and the gates 53, 57 of the VTFETs 63, 67, and using the abutting bottom source/drain regions 18, 20 of the VTFETS 63, 67 and the gates 50, 56 of the VTFETs 60, 66. A write word line (WWL) is connected with the gate 51 of the PG VTFET 61 and with the gate 52 of the PG VTFET 62. A true bit line (BLT) is connected with the top source/drain region 70 of the PG VTFET 63, which is the drain region of the PG VTFET 63 in the representative embodiment. A complementary bit line (BLC) is connected with the top source/drain region 70 of the PG VTFET 61, which is the drain region of the PG VTFET 61 in the representative embodiment. The top source/drain region 72 of the PU VTFET 66 and the top source/drain region 72 of the PU VTFETs 67, which are source regions in the representative embodiment, are connect with a positive supply voltage (VDD) line. The top source/drain region 70 of the PD VTFET 60 and the top source/drain region 70 of the PD VTFET 63, which are source regions in the representative embodiment, are connected with a ground power supply (VSS) line. The connections are diagrammatically indicated in
The read port of the two-port SRAM 80 includes the RPG VTFET 64 and the RPD VTFET 65. A read word line (RWL) is connected with the gate 54 of the RPG VTFET 64. A read bit line (RBL) represents a data access line that is connected with the top source/drain region 70 of the RPG VTFET 64, which is the drain of the RPG VTFET 64 in the representative embodiment. The top source/drain region 70 of the RPD VTFET 65, which is a source region in the representative embodiment, is tied to the ground power supply (VSS) line. The RPG VTFET 64 and the RPD VTFET 65 of the read port share the same bottom source/drain region 18 in common such that their drain regions are coupled together to provide an internal node connection.
The abutment of the bottom source/drain region 18 of the PD VTFET 60 with the bottom source/drain region 20 of the PU VTFET 66 along a vertical interface couples their respective drains together in the representative embodiment. Similarly, the abutment of the bottom source/drain region 18 of the PD VTFET 63 with the bottom source/drain region 20 of the PU VTFET 67 along a vertical interface couples their respective drains together in the representative embodiment.
The sections 36 of the patterned gate stack 30 respectively represent a gate extension to the gate 51 of the PG VTFET 61, a gate extension to the gate 52 of the PG VTFET 62, and a gate extension to the gate 54 of the RPG VTFET 64. One of the sections 38 of the patterned gate stack 30 couples the gate 56 of the PU VTFET 66 with the gate 50 of the PD VTFET 60. The other section 38 of the patterned gate stack 30 couples the gate 57 of the PU VTFET 67 with the gate 53 of the PD VTFET 63. The section 40 of the patterned gate stack 30 couples the gate 55 of the RPD VTFET 65 with the gate 57 of the PU VTFET 67.
The PU VTFET 66 is arranged at a side or end of the row that includes the fins 10, 11, and fin 16. The PU VTFET 67 is arranged at a side or end of the row that includes the fins 12, 13, and fin 17, and is arranged at an opposite end of the rows from the PU VTFET 66.
With reference to
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
