Patent Application
20070223296
There are also WLs 70 and 72 on the opposite side of the sense amplifier 50 that intersect with BLs 16 and 18. At the intersection there are memory array cells 80 and 82. The sense amplifier 50 is shared by the memory arrays on both sides. There is a multiplexer circuit 90 and equalizer circuit 95 that control the connection and isolation of the sense amplifier 50 with the memory array on the other side. For purposes of this description, the left side memory array is the “t” side and the right side is the “b” side.
The primary purpose of multiplexer circuits 30 and 90 is to isolate the BLs of the unselected memory array during a sense operation (of the selected memory array) and to allow the sense amplifier internal nodes to be precharged via the BL and /BL nodes. The multiplexer is also used to connect the sense amplifier internal nodes to the bitlines of the selected array for reading from and writing to the memory cell. Multiplexer circuit 30 is controlled by multiplexer control signal MUXb and multiplexer circuit 90 is controlled by multiplexer control signal MUXt. The equalization circuits 40 and 95 are controlled by equalization control signals EQLb and EQLt, respectively. The operation is as follows.
In normal operation when a memory array is unselected, the equalizer circuits 40 and 95 are on, precharging BL and /BL and both multiplexer control signals (MUXt and MUXb) are set to a voltage that is high enough to turn on the multiplexer transistors such that the internal sense amplifier nodes (SA and /SA) are brought to the same potential as BL nodes BL and /BL. When a memory cell is selected in an array on one side of the sense amplifier 50 the equalization circuit transistors on that side are turned off while the multiplexer control signal on that side is boosted to a high enough voltage to permit fast reading and writing of data between the internal sense amplifier nodes (SA and /SA) and the BLs (BL and /BL) and the selected array cell. At the same time the multiplexer control signal for the unselected array is turned off to isolate the unselected array for the duration of the memory access while the equalization circuit of the unselected array remains on. The WL to the selected memory cell is then brought to a voltage that is high enough to turn on the cell access transistor and effectively connect the memory cell capacitor to a bitline (BL or /BL) and after a sufficient time the sense amplifier 50 is turned on to amplify the resulting voltage difference of BL and /BL to a full digital data signal. At the completion of an array access operation the WL is reset back to the unselected potential, the sense amplifier 50 is turned off, and the multiplexer control signals (MUXb and MUXt) and the equalization control signals (EQLb and EQLt) are returned to the precharging condition.
The multiplexer circuits 30 and 90 devices are normally used to isolate BL nodes from internal sense amplifier nodes during sensing but they can also be used to isolate BL nodes from internal sense amplifier nodes at other times for other purposes such as for isolating BL nodes from internal sense amplifier nodes for reducing array leakage due to defects.
In a DRAM device such as that shown in
Control logic circuitry in a control portion of the DRAM chip supplies isolate control signals to all the memory arrays to control the state of the multiplexer circuits and to isolate BLs from internal sense amplifier nodes for the purpose of blocking defect leakage current during periods that the array is not accessed.
At the beginning and end of each self-refresh cycle, the isolate control signals bISOOFFMUXt and bISOOFFMUXb are dis-asserted and asserted to turn on and off, respectively, the corresponding multiplexer circuit at the beginning and end of each self-refresh cycle for all memory array segments. The isolate control signals bISOOFFMUXt and bISOOFFMUXb must be dis-asserted and asserted because block select control signals BLKSEL and BLKSELi to the multiplexer control circuits do not override the isolate control function. When isolate control signal bISOOFFMUXt is asserted, a voltage is imposed on the transistor 36 that forces MUXt to go low. When the need arises to sense the voltage in memory cells on a side of the sense amplifier in which the multiplexer circuits were isolating, it is necessary to switch them back to an “on” state to allow the sense amplifier to sense voltage difference between BL and /BL. The bISOOFFMUXt is dis-asserted by transitioning to a logic high level and the MUXt is controlled by the BLKSEL and BLKSELi signals. At the end of the access cycle, the multiplexer circuit is turned off to isolate the sense amplifier from the BL by re-asserting bISOOFFMUXt causing MUXt to go low.
There are several disadvantages with this scheme. First, the same isolate control signals are supplied to control the multiplexers in all of the memory array blocks even when only a particular memory array block is accessed. By globalizing this function, more signal lines need to be switched than is necessary. This uses a relatively large amount of switching current that offsets any reduction in the defect leakage current. Also, time must be allocated for entry to and exit from the leakage limiting mode of operation. The additional time requirement degrades array performance and limits the useful application of the globalized isolate control to be applied only during industry standard self-refresh mode.
Briefly, a semiconductor memory device and method are provided in which leakage current of the memory device is reduced. A sense amplifier is isolated from a memory array that has an anomalous bitline leakage when the memory array is not selected.
Referring first to
The multiplexer control circuits RMUXt 110 and RMUXb 120 control the corresponding multiplexer circuits 90 and 30, respectively, such that the isolation control signals control only non-selected multiplexer output state. That is, the block select signals BLKSEL and BLKSELi automatically override the isolate control signal state and bring the output of the multiplexer to the proper selected state, regardless of its starting state. In addition, dis-assertion of the block select signals BLKSEL and BLKSELi returns control of the multiplexers back to the isolate control signals during non-select time intervals, that is, when the memory array is not being accessed. In one embodiment, the BLKSEL and BLKSELi signals may be generated in the WL activation control logic section 400 along a periphery of an array in the memory device. The block select signals are dependent on which block of the array is to be accessed based on incoming address information. In one embodiment, this is where the logic resides that generates the signals that turn on and off a WL and to control the sense amplifiers that are in a column along the edge of array segments.
The multiplexer control techniques according to the embodiments of the present invention block the bitline short-circuit type of defect leakage current flowing through sense amplifier devices when the memory array having the defect is an unselected state, thereby reducing the current consumption of the memory device. In addition, the isolate control signal does not have to be dis-asserted during array accesses. In one embodiment, the isolate control signals can be DC-fuse configured to operate in normal standby and self-refresh modes without access penalty. Previous multiplexer control schemes only isolate the BLs from the sense amplifier to block leakage current from bitline shorts during self-refresh. More generally, the BL isolation control techniques according to the embodiments described herein may be used to isolate a memory array that has an anomalous bitline leakage that may be due to low resistive path defects (e.g., short-circuits), excessive junction leakage, or other causes. These techniques reduce current in a standby state of the memory device, but more generally they reduce the current consumption of the memory device whenever the memory array or memory bank containing the defect is unselected.
The intelligence to keep track of which memory array segments have an anomalous bitline leakage is contained in manufacturing programs and databases. The memory device is interrogated by test equipment and the test results are stored in computer system files and processed off-line by various analysis programs. These programs create a database file that is accessed when a wafer arrives at a fuse programming tool. The database file tells the fuse programming tool on which memory devices and which array segments on the memory device the isolation feature is to be activated.
In one embodiment, the transistor network 112 comprises N-type field effect transistors (NFETs) N20 and N30, and P-type FETs (PFETs) P40 and P50. The signal at the drain of PFET P40 is the multiplexer control signal MUXt.
In one embodiment, the digital logic network 114 comprises inverters 120 and 130 that produce signals bBLKSEL and bBLKSELi from block signal signals BLKSEL and BLKSELi, respectively. In addition, in one embodiment the digital logic network 114 further comprises NAND gates NG20-NG80. An inverter 140 couples the output of NAND gate NG40 to the gate of NFET N30 in the transistor network 112. The output of NAND gate NG80 is coupled to the gate of NFET N20.
According to the embodiments of the invention, the block select signals BLKSEL and BLKSELi can override the isolate control signals to control the multiplexer state regardless of the previous multiplexer state and the status of the isolate control signals. The multiplexer circuits 30 and 90 are controlled such that the isolation control signals affect only the multiplexers for the non-selected memory arrays. After the block select signals are dis-asserted, the multiplexer control circuit returns the multiplexer circuit to the state defined by the isolate control signal state or to VINT if the isolate control signal is not asserted. Otherwise, the MUXt signal returns to ground if the isolate control signal is asserted. Therefore, instead of using the logic in the ‘spine’ or central logic control region of the chip to generate the control signals which determine when to isolate and not isolate BLs for the purpose of reducing leakage current, the isolate control logic for the multiplexer circuits is embedded in the sense amplifier control logic section of the device and is therefore block selective. Moreover, the multiplexer control circuit automatically overrides the isolate control signal state for all types of array accesses and does not need to make a distinction between a normal selected state and a self-refresh selected state. Consequently, if there is a BL-WL short-circuit (causing a BL leakage current in the sense amplifier) resulting from a defect in a particular memory array, that memory array can also be isolated from the sense amplifier (as opposed to being allowed to remain weakly connected to it).
Turning to
The bank select signal BNKSEL goes high for a particular bank to activate that bank in the memory device depending on the address to be accessed. Once the address is stable, the BLKSEL (or BLKSELi) signal goes high for a particular block within the selected bank, thereby activating the corresponding multiplexer control circuit for the selected block (also referred to as a selected array segment). Just prior to activating the multiplexer, the equalizer circuit for the side of the sense amplifier that is accessed (sensed), EQLb, turns off while the EQLt remains at a high level to keep the unselected array precharged.
When BLKSEL transitions to a high state, bBLKSEL transitions to a low state, thereby forcing the output of NAND gate NG50 to a high state. Since nodes N5t and bBLKSELi are already at a high state, the output of NAND gate NG50 going high forces the output of NAND gate NG70 and the output of NAND gate NG40 at node N4t to a low state. A low input to NAND gate NG80 forces node N2t high turning PFET P50 off and turning NFET N20 on. A low input to inverter 140 forces node N3t high turning PFET P40 off and turning NFET N30 on. The output signal MUXt is pulled to a low logic level to turn multiplexer circuit 90 off thereby isolating BLs from sense amplifiers on the “t” side of the sense amplifiers. Conversely, multiplexer control circuit 120 for the multiplexer circuit 30 on the opposite “b” side of the sense amplifier outputs control signal MUXb which is pulled to a VPP voltage level strongly connecting the BL's to the sense amplifiers on the “b” side of the sense amplifier.
When BLKSELi transitions to a high state, bBLKSELi transitions to a low state and forces nodes N1t, N4t, and the output of NAND gate NG50 to a high state. Node N3t transitions to a low state turning off NFET N30. Node N2t transitions to a low state turning off NFET N20 and turning on PFET P50. The output MUXt is pulled to a VPP voltage level strongly connecting the BLs to the sense amplifiers on this side of the sense amplifiers. When either BLKSEL or BLKSELi is dis-asserted the reverse occurs and MUXt/b returns to a VINT level through the on states of NFET N20 and PFET P40.
The following describes operation of the multiplexer control circuit 110 under conditions in which the memory device has a BL-WL short-circuit type defect in the array on the “b” side according to an embodiment of the invention. In the embodiment shown in
BLKLATCH is low, bISOOFFMUXb is active low, BLKSEL and BLKSELi are low, the multiplexer control signal MUXb is at a ground potential connected through NFET N30 and the multiplexer control signal MUXt is at VPP or a high level. Nodes N5t and N5b are at a logic high level. The signals bBLKSEL and bISOOFFMUXt are both high maintaining the output of NAND gate NG50 in a low state. The multiplexer control signal that is low, in this example MUXb for the “b” side, disables the multiplexer circuit 30 thereby disconnecting the memory array with the defect from the sense amplifier. This serves to block or isolate the sense amplifier from the memory array side in which the short-circuit type defect is located. Thus, the multiplexer circuit on the side where the short is occurring isolates the sense amplifier 50 from the short whenever that side of the memory array is not selected to access data.
The multiplexer control circuit 110 is activated by asserting BLKSEL or BLKSELi to an active high state, which occurs after the BNKSEL signal has gone high. In this example, when BLKSEL transitions to a high state, bBLKSEL transitions to a low state and forces nodes N1t, N4t, and the output of NAND gate NG50 to a high state. Consequently, node N3t transitions to a low state turning off NFET N30. Node N2t transitions to a low state turning off NFET N20 and turning on PFET P40. When PFET P40 is turned on, the output signal MUXb is pulled to VPP voltage level thereby strongly connecting the BLs to the sense amplifiers 50 on the “b” side. Conversely, the multiplexer control signal MUXt goes low to isolate the “t” side from the sense amplifier 50 as shown in
On the other hand (though not shown in
A further advantage of this embodiment is that the BLKLATCH signal can be used in self-refresh mode to prevent the multiplexer control circuits RMUXt and RMUXb from switching between selected and unselected states. This allows a reduction in switching current during periods of self-refresh cycles when array address sequencing is not random and can be designed to proceed linearly through the address range of an array segment before crossing the boundary to the next array segment. The BLKLATCH can remain on while refreshing within the array segment and can turn off when switching between array segments to provide the reduction in switching current.
The system and methods described herein may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative and not meant to be limiting.
