Patent Application
20130068297
This invention relates to the field of solar cell device fabrication technology, in particularly to a black silicon solar cell and its fabrication method.
Facing to the environmental problems such as greenhouse effect, acid rain and other problems caused by current energy source crisis and mass cost of chemic fuel, it's urgent to develop and utilize new energy source efficiently worldwide. Solar energy is a kind of reproducible energy which is obtained easily and green. It will become the main body of the worldwide energy supply before long. A solar cell, which is regarded as clean and efficient green continuable energy source, will provide broader prospect for the efficient use of solar energy. So the research of improving the photoelectric conversion efficiency must be of significance in application and has prospects of development.
Currently, due to the high manufacturing cost, the solar cell can not replace traditional energy source, thereby, lowering the manufacturing cost of solar cell becomes the biggest problem in the industry. And the manufacturing cost has close relation with efficiency of the solar cell. Because of the high refractive index of silicon, the reflection loss can reach more than 40%, which means that due to the high reflectivity of silicon-based cell, the photoelectric conversion efficiency is lowered greatly.
Black silicon which usually means silicon surface or silicon-based film (including surface or film of silicon compound) with high absorptivity is a revolutionarily new material in electronic industry. Compared to normal silicon material, black silicon has strong light absorption ability. If the black silicon is applied to optical sensor or solar cell, the efficiency of light sensing can be improved to a hundred times. And the conversion efficiency of solar cell can be markedly improved.
Eric Mazur and other people in American Harvard university have fabricated black silicon material by femtosecond laser method, thus have fabricated black silicon solar cell which has a photoelectric conversion efficiency of 8.8%˜13.9%. However, the cost of fabricating black silicon material by femtosecond laser method is higher, which certainly increases the fabrication cost of black silicon solar cell, and is disadvantage in fabrication.
To lower the fabrication cost of black silicon solar cell, the present invention provides a black silicon solar cell and its fabrication method.
The black silicon solar cell is comprised of metal back electrode, crystalline silicon, black silicon layer, passivation layer and metal gate electrode. The metal back electrode is located on the back of the crystal silicon, the black silicon layer is located on the crystal silicon, the passivation layer is located on the black silicon layer, and the metal gate electrode is located on the passivation layer.
The crystal silicon is monocrystalline silicon or polysilicon, the metal back electrode is made of aluminum, cuprum, silver, gold or platinum, and the metal gate electrode is made of aluminum, cuprum, silver, gold or platinum.
The thickness of the metal back electrode is 10-15 microns. The thickness of the monocrystalline silicon or polysilicon is 100-300 microns. The thickness of the black silicon layer is 0.1-10 microns. The thickness of the passivation layer is 50-200 nanometers. The thickness of the metal gate electrode is 2-10 microns. The gate width of which is 30-150 micro, and the distance is 2-3 millimeters.
The fabrication method of the black silicon solar cell includes:
pretreating the silicon wafer;
fabricating the black silicon layer on the surface of the pretreated silicon wafer by using plasma immersion ion implantation technology;
fabricating emitter on the black silicon layer, and carrying out passivation treatment to the emitter to form the passivation layer;
fabricating the metal back electrode and metal gate electrode on the back of the monocrystalline silicon wafer and the passivation layer respectively.
The step of pretreating the silicon wafer includes:
immersing the silicon wafer into the hydrofluoric acid solution, and then washing it with deionized water;
immersing the silicon wafer which has been washed with deionized water into sodium hydroxide solution to remove damaged layer of the silicon layer;
washing the silicon wafer whose damaged layer has been removed, and drying it with nitrogen gas.
In the plasma immersion ion implantation technology, the step of fabricating black silicon layer on the surface of the pretreated silicon wafer includes:
placing the silicon wafer in the implantation chamber of the plasma immersion ion implantation device;
adjusting craft parameters of said plasma immersion ion implantation device into the range of value set beforehand;
the plasma immersion ion implantation device generates plasma, and the reacting ions in the plasma are implanted into said silicon wafer;
the reactive ions react with the silicon wafer, and the black silicon layer is formed.
The step of placing the silicon wafer in the implantation chamber of the plasma immersion ion implantation device further includes: connecting said silicon wafer with a power supply electric which can apply bias voltage; said art parameters include base pressure and work pressure of the implantation chamber, and component and volume ratio of mixed gas implanted into the implantation chamber; the range of the base pressure is 10−5˜10−3 pa, and the range of the work pressure is 0.1 pa˜50 pa;
said mixed gas is comprised of gas with etching function and gas with passivation function, and said gas with etching function includes SF6, CF4, CHF3, C4F8, NF3, SiF4, C2F6, HF, BF3, PF3, Cl2, HCl, SiH2Cl2, SiCl4, BC3 or HBr, and said gas with passivation function includes: O2, N2O or N2, and the range of the volume ratio of said gas with etching function and said gas with passivation function is 0.01˜100.
The step of fabricating emitter on said black silicon layer includes:
placing the silicon wafer into quartz container of a tubular of diffusion furnace;
bringing phosphorus oxychloride into said quartz container with nitrogen gas at a high temperature;
the phosphorus oxychloride reacts with the silicon wafer, and phosphorus atoms are formed;
the atoms penetrating and diffusing to the inside of said silicon wafer, thus PN junction is formed.
Steps between the step of fabricating emitter on the black silicon layer and the step of passivation treatment to the emitter include:
placing the silicon wafer into hydrofluoric acid solution to be immersed;
performing etching to the silicon wafer after been immersed to remove its edge.
The passivation treatment is the surface oxidation vegetating SiO2 passivation treatment, or PECVD vegetating SiNx or SiO2 passivation treatment.
Compared to conventional art, the present invention has the following advantages:
In the following detailed description of the present invention, reference is made to the accompanying drawings and embodiment.
Referring to
The metal back electrode 1 is located on the back of the crystal silicon 2, and the metal back electrode can be made of aluminum (Al), copper (Cu), silver (Ag), gold (Au) or platinum (Pt) and other metals, and also can be made of multiple kinds of metal material mixed together, such as alloy material or copper sheet silvered on surface, and the crystal silicon 2 can be p-type monocrystalline silicon, p-type polysilicon, n-type monocrystalline silicon or n-type polysilicon, and also can be all kinds of above crystal which has been washed and processed with damage removal pre-treatment.
The black layer 3 is located on the crystal silicon 2. It can be black silicon which is formed from crystal (including monocrystalline and multi-crystal) processed with plasma immersion ion implantation technology, and also can be black silicon which is formed from crystal (including monocrystalline and multi-crystal) processed with etching technology. The etching technology includes dry etching and wet etching, and the dry etching includes reactive ions etching (RIE), induction ions coupling plasma (ICP) etching, high-pressure plasma etching and other etching. Doping type of the black silicon layer corresponds to that of the crystal silicon, such as: if the crystal silicon is p-type, the black silicon layer is n-type; and if the crystal silicon is n-type, the black silicon layer is p-type.
The passivation layer 4 is located on the black silicon 3. It can be formed with surface oxidation vegetating SiO2 passivation treatment on the black silicon layer, and it also can be formed with PECVD vegetating SiNx or SiO2 passivation treatment on the black silicon layer.
The metal gate electrode 5 is located on the passivation layer 4, which can be made of metal aluminum (Al), copper (Cu), silver (Ag), gold (Au) or platinum (Pt) and other metals, and also can be made of multiple kinds of metal material mixed together, such as alloy material or copper gold-filled on surface.
Wherein, thickness of the metal back electrode 1 is 1 to 100 microns, preferably 10 to 15 microns; thickness of the crystal silicon 2 is 10 to 1000 microns, preferably 100 to 300 microns; thickness of the black silicon layer 3 is 0.01 to 50 microns, preferably 0.1 to 10 microns; thickness of the passivation layer 4 is 1 to 500 nanometers, preferably 50 to 200 microns; thickness of the metal gate 5 is 1 to 50 microns, preferably 2 to 10 microns, and width of the gate electrode is 10 to 1000 microns, preferably 30 to 150 microns, and the distance of which is 1 to 10 millimeters, preferably 2 to 3 millimeters.
The black silicon solar cell supplied by the present embodiment has simple structure, in which the black silicon layer is taken as absorbing layer, thus average absorbing rate is improved. As shown in
Refer to
Step 101: Applying washing and damage removal pre-treatment to the monocrystalline silicon wafer;
First, immersing the silicon wafer into hydrofluoric acid solution for 1-10 minutes to be washed with deionized water, and then immersing the silicon wafer into sodium hydroxide solution which has a concentration of 1%˜30% and a temperature of 50-80° C. for 1-10 minutes, to remove damaged layer of the silicon layer; and at last, washing the monocrystalline silicon wafer with deionized water, and drying it with nitrogen gas;
Step 102: fabricating black silicon layer on the surface of the pretreated silicon wafer with plasma immersion ion implantation technology.
In the present embodiment, the device implement plasma immersion ion implantation, usually called plasma immersion ion implantation machine, generally includes implantation chamber and plasma source. A sample stage on which samples are put is placed in the implantation chamber, and plasma source is placed opposite to the sample stage.
Plasma source includes vacuum system, which can vacuum the chamber to reach the pre-set base pressure range; gas supply system, which can implant gas the chamber required, and can adjust the parameter of the gas according to certain rules, such as gas flow, vacuum speed, gas composition ratio and concentration and other parameters, as well as make pressure of the chamber to preset work pressure range after gas implanted into the chamber; and plasma power source, which can be RF power source, microwave power source or DC power source. These sources can supply power with pulse form, and the frequency of all the power can be fixed frequency or variable frequency. Besides, the device also includes power source which can apply bias voltage. The power source which can apply bias voltage is connected electrically with the sample stage. The type of the power source which can apply bias voltage is similar to that of the plasma power source, which can be RF power source, microwave power source or DC power source, and these sources can supply power with pulse form. These sources can be combined randomly, and thus the sample stage can be applied with bias voltage comprised of multiple kinds of bias voltage.
In the present embodiment, plasma immersion ion implantation craft is: placing the single silicon wafer in the implantation chamber; adjusting craft parameters of said plasma immersion ion implantation device into the range of value set beforehand; plasma immersion ion implantation device generates plasma, and the reacting ions in the plasma are implanted into said silicon wafer, the reactive ions react with said silicon wafer, and the black silicon layer is formed.
The craft parameters to be adjusted include: base pressure and work pressure, gas flow, vacuum speed, gas composition ratio and concentration, output power and frequency of the plasma source, bias voltage applied by the power source which can apply bias voltage and pulse width, duty cycle and frequency if pulse form is taken.
The base pressure range of the implantation chamber can be 10−7 pa to 1000 pa, preferably 10−5 pa to 10 pa, more preferably 10−5 pa to 10−3 pa; and the work pressure range of the implantation chamber is 10−3 pa to 1000 pa, preferably 0.01 pa to 100 pa, more preferably 0.1 pa to 50 pa.
The implantation gas can be mixed gas comprised of gas with etching function and gas with passivation function, and said gas with etching function includes SF6, CF4, CHF3, C4F8, NF3, SiF4, C2F6, HF, BF3, PF3, Cl2, HCl, SiH2Cl2, SiCl4, BCl3 or HBr, and said gas with passivation function includes: O2, N2O or N2, preferably comprised of multiple kinds of gas with etching function and multiple kind of gas with passivation function, and more preferably comprised of one kind of gas with etching function and one kind of gas with passivation function, such as mixed gas comprised of SF6 and O2 or CF4 and N2. If it meets the condition that the mixed gas comprised of gas with etching function and gas with passivation function, and the volume ratio of the gas with etching function and the gas with passivation function is 0.01 to 100, the mixing type can be random. Preferably, the volume ratio of the gas with etching function and the gas with passivation function is 0.1 to 80, and more preferably 1 to 20. The flow of the mixed gas is 1 to 1000 sccm, preferably 10 to 100 sccm, and more preferably 20 to 80 sccm.
Output power of the plasma power source is 1 to 100000 W, preferably 10 to 50000 w, and more preferably 300 to 5000 W. The bias voltage applied is −100000 to 100000V, preferably −50000 to 50000V, and more preferably −10000 to 0V, and pulse width of which is 1 us to 1 us, preferably 1 us to 0.1 s, more preferably 1 us to 1 ms; and duty cycle of which is 1% to 99%, preferably 10% to 90%, and more preferably 20% to 80%. Frequency of the plasma power source is DC to 10 GHz, preferably 1 MHz to 5 GHz, and more preferably 13.56 MHz to 5 GHz. Frequency of the power source which can supply bias voltage is DC to 10 GHz.
In present embodiment, mixed gas utilized is comprised of SF6 and O2. Surface density of the monocrystalline silicon wafer is decreased due to the treatment on the monocrystalline silicon wafer surface, and thus the quality of the surface of the monocrystalline silicon wafer is effectively improved and the silicon wafer surface recombination is reduced.
Step 103: Fabricating emitter on black silicon layer.
Placing said silicon wafer into quartz container of a tubular of diffusion furnace, bringing phosphorus oxychloride into the quartz container with nitrogen gas at a temperature of 850 to 900° C., the phosphorus oxychloride reacts with the silicon wafer, and phosphorus atoms are formed. After a certain time, the atoms penetrate and diffuse to the inside of said silicon wafer, and thus the interface between N-type semiconductor and P-type semiconductor (i.e. PN junction) is formed.
Step 104: Removing phosphosilicate glass on the surface of the monocrystalline silicon wafer with chemical etching method.
Placing the monocrystalline silicon wafer into hydrofluoric acid solution to generate soluble complex hexafluorosilicate by chemical reaction, and a layer of phosphosilicate glass formed on the monocrystalline silicon wafer after junction made by diffusing is removed.
Step 105: Etching the single silicon wafer to remove its edge.
With CF4 gas, reactive gas is activated to generate active particles by high-frequency glow discharge reaction. These particles diffuse to position of the monocrystalline silicon wafer required to be etched, where react with material to be etched to generate volatile substances which is removed.
Step 106: Passivating the emitter to form passivation layer.
In practical application, surface oxidation vegetate SiO2 passivation treatment can be applied, and PECVD vegetating SiNx or SiO2 passivation treatment also can be applied. The surface oxidation vegetating SiO2 passivation treatment is applied in present embodiment, which includes the following steps: Placing the monocrystalline silicon wafer in a dry oxygen atmosphere to be oxidated at a temperature of 800 to 1000° C. for 20 to 40 minutes, and then place it in a nitrogen gas atmosphere to be annealed at the same temperature for 5 to 20 minutes.
Step 107: Fabricating metal Al back electrode on the back of monocrystalline silicon wafer.
High purity aluminum is utilized as the evaporation source, and aluminum metal with a thickness of 10 to 15 microns is deposited on the back of the monocrystalline silicon wafer. And then, in a protecting atmosphere, annealing is carried on for 20-40 minutes at a temperature of 350 to 450° C. to form an ohmic contact metal Al back electrode. In the present step, 350 to 450° C. annealing is carried on instead of high temperature sintering process, which can avoid damage to the monocrystalline silicon wafer caused by stress induced by high-temperature sintering process and help to reduce the thickness of monocrystalline silicon wafers.
Step 108: Fabricating Ag gate electrode on the passivation layer.
By silk screen printing method, that is, silver paste is printed on the surface of the passivation layer by special printer and template, Ag gate electrode is formed. The thickness of the gate electrode is 2-10 microns. The width of the gate electrode is 30-150 microns, and the distance is 2-3 millimeters.
In the present fabricating method embodiment, polysilicon can be used instead of monocrystalline silicon, and the present invention can also be realized.
The fabricating method of the black silicon solar cell supplied by the present embodiment is simple, unique and easy to master, and it has the advantage that it is convenient to manipulate and reliable to repeat, and thus it has clear industrial prospect.
The purpose, technical program and beneficial effects of the present invention are described in detail through the embodiment said above. It should be noted that the above description is only the preferred embodiment, but not intended to limit the present invention. Any modification, equivalent replacement, improvement of the present invention should be deemed to fall into the protection scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201010181010.1 | May 2010 | CN | national |
| 201010244858.4 | Aug 2010 | CN | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/CN10/75750 | 8/5/2010 | WO | 00 | 11/25/2012 |
