Patent Application
20240356550
The present application claims priority under 35 U.S.C. § 119 (a) to Korean application number 10-2023-0053381, filed on Apr. 24, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.
Various embodiments generally relate to integrated circuit technology, and more specifically, to a buffer circuit and a clock generating circuit, a semiconductor apparatus and a semiconductor system utilizing the buffer circuit.
Electronic devices contain numerous electronic components, and among them, a computer system may include many semiconductor apparatuses. The semiconductor apparatuses that make up the computer system may communicate with each other by transmitting and receiving clock signals and data. The semiconductor apparatuses may transmit and/or receive a system clock signal with other semiconductor apparatuses and may be synchronized to the system clock signal to transmit and receive data. As the operating frequency of the computer system increases, the frequency of a signal used between the semiconductor apparatuses or internally within the respective semiconductor apparatuses is increasing while the amplitude of the signal is decreasing. The semiconductor apparatuses may be equipped with buffer circuits to process the high-frequency signals. The operational performance of the buffer circuits may be a critical factor in determining the operational speed and the reliability of the semiconductor apparatuses.
In an embodiment, a buffer circuit may include a driving control circuit and a driving circuit. The driving control circuit may be configured to receive an input signal, configured to change a voltage level of a first node to a voltage level lower by a first voltage level lower than a high boundary voltage level of the input signal and configured to change a voltage level of a second node to a voltage level higher by a second voltage level higher than a low boundary voltage level of the input signal. The driving circuit may be configured to pull-up drive an output node based on the voltage level of the first node and configured to pull-down drive the output node based on the voltage level of the second node.
In an embodiment, a buffer circuit may include a driving control circuit and a driving circuit. The driving control circuit may be configured to receive an input signal swinging between a high boundary voltage level and a low boundary voltage level and configured to convert the swing range of the input signal to generate a pull-up control signal swinging within a first swing range and a pull-down control signal swinging within a second swing range. The driving circuit may be configured to pull-up drive an output node based on the pull-up control signal and configured to pull-down drive the output node based on the pull-down control signal.
In an embodiment, a buffer circuit may include a driving control circuit and a driving circuit. The driving control circuit may be configured to receive an input signal and configured to generate, when a first control signal is enabled, a pull-up control signal having a voltage level lower than a high boundary voltage level of the input signal and a pull-down control signal having a voltage level higher than a low boundary voltage level of the input signal. The driving circuit may be configured to pull-up drive an output node based on the pull-up control signal and configured to pull-down drive the output node based on the pull-down control signal.
In an embodiment, a buffer circuit may include a first driving control circuit, a first driving circuit, a second driving control circuit and a second driving circuit. The first driving control circuit may be configured to change, when a first control signal is enabled, a voltage level of a first input signal to generate a first pull-up control signal and a first pull-down control signal. The first driving circuit may be configured to pull-up drive a first output signal based on the first pull-up control signal and configured to pull-down drive the first output signal based on the first pull-down control signal. The second driving control circuit may be configured to change, when the first control signal is enabled, a voltage level of a second input signal to generate a second pull-up control signal and a second pull-down control signal. The second driving circuit may be configured to pull-up drive a second output signal based on the second pull-up control signal and configured to pull-down drive the second output signal based on the second pull-down control signal.
In an embodiment, a buffer circuit may include a first driving control circuit, a second driving control circuit and a driving circuit. The first driving control circuit may be configured to receive a first input signal and configured to change, based on a first selection signal, a voltage level of the first input signal to generate a pull-up control signal and a pull-down control signal. The second driving control circuit may be configured to receive a second input signal and configured to change, based on a second selection signal, a voltage level of the second input signal to generate the pull-up control signal and the pull-down control signal. The driving circuit may be configured to pull-up drive an output signal based on the pull-up control signal and configured to pull-down drive the output signal based on the pull-down control signal.
In an embodiment, a buffer circuit may include a first N-channel MOS transistor, a first P-channel MOS transistor, a second P-channel MOS transistor and a second N-channel MOS transistor. The first N-channel MOS transistor may be configured to receive a first control signal through a gate thereof and configured to receive an input signal through one of source and drain thereof and connected to a first node through the other of the source and the drain thereof. The first P-channel MOS transistor may be configured to receive a complementary signal of the first control signal through a gate thereof and configured to receive the input signal through one of source and drain thereof and connected to a second node through the other of the source and the drain thereof. The second P-channel MOS transistor may be configured to pull-up drive an output node based on a voltage level of the first node. The second N-channel MOS transistor may be configured to pull-down drive the output node based on a voltage level of the second node.
The buffer circuit 100 may include a driving control circuit 110 and a driving circuit 120. The driving control circuit 110 may receive the input signal IN and may change the voltage level of the input signal IN to generate a pull-up control signal PU and a pull-down control signal PD. The driving control circuit 110 may output the pull-up control signal PU through a first node ND1 and the pull-down control signal PD through a second node ND2. The buffer circuit 100 may reduce the swing range of the input signal IN and may generate the pull-up control signal PU and the pull-down control signal PD, which have the reduced swing range. The driving control circuit 110 may generate the pull-up control signal PU having a lower voltage level than the high boundary voltage level of the input signal IN. The driving control circuit 110 may generate the pull-down control signal PD having a higher voltage level than the low boundary voltage level of the input signal IN. The driving control circuit 110 may change the voltage level of the first node ND1 to a voltage level lower by a first voltage level than the high boundary voltage level of the input signal IN. The driving control circuit 110 may change the voltage level of the second node ND2 to a voltage level higher by a second voltage level than the low boundary voltage level of the input signal IN. The first voltage level may be the same as or different from the second voltage level. The first voltage level may vary as far as the driving circuit 120 is able to determine, as a high logic level, the voltage level of the first node ND1 lower by the first voltage level than the high boundary voltage level. The second voltage level may vary as far as the driving circuit 120 is able to determine, as a low logic level, the voltage level of the second node ND2 higher by the second voltage level than the low boundary voltage level. The driving control circuit 110 may change the swing range of the input signal IN to generate the pull-up control signal PU having a first swing range and the pull-down control signal PD having a second swing range. Each of the first swing range and the second swing range may be smaller than the swing range of the input signal IN. The first swing range may be between a voltage level, which is lower by the first voltage level than the high boundary voltage level, and the low boundary voltage level. The second swing range may be between the high boundary voltage level and a voltage level, which is higher by the second voltage level than the low boundary voltage level.
The driving control circuit 110 may further receive a first control signal CON1. The first control signal CON1 may be to activate or deactivate the buffer circuit 100. Based on the first control signal CON1, the driving control circuit 110 may generate the pull-up control signal PU and the pull-down control signal PD from the input signal IN. When the first control signal CON1 is enabled, the driving control circuit 110 may change the voltage level of the first node ND1 to a voltage level lower than the input signal IN to generate the pull-up control signal PU and may change the voltage level of the second node ND2 to a voltage level higher than the input signal IN to generate the pull-down control signal PD. When the first control signal CON1 is disabled, the driving control circuit 110 might not generate, from the input signal IN, the voltage levels of the first node ND1 and the second node ND2 and might not generate the pull-up control signal PU and the pull-down control signal PD.
The driving circuit 120 may be connected to the first node ND1 to receive the pull-up control signal PU from the driving control circuit 110 and may be connected to the second node ND2 to receive the pull-down control signal PD from the driving control circuit 110. The driving circuit 120 may change a voltage level of the output node ON based on the voltage levels of the first node ND1 and the second node ND2 and/or the pull-up control signal PU and the pull-down control signal PD. The output signal OUT may be generated through the output node ON. The driving circuit 120 may pull-up drive the output node ON based on the voltage level of the first node ND1 and/or the pull-up control signal PU. The driving circuit 120 may pull-down drive the output node ON based on the voltage level of the second node ND2 and/or the pull-down control signal PD. The driving circuit 120 may receive a first power voltage V1 and a second power voltage V2. The first power voltage V1 may have a higher voltage level than the second power voltage V2. For example, the first power voltage V1 may be an operating power voltage of the buffer circuit 100, and the second power voltage V2 may be a ground voltage. The driving circuit 120 may drive, based on the voltage level of the first node ND1, the output node ON to the voltage level of the first power voltage V1. The driving circuit 120 may drive, based on the voltage level of the second node ND2, the output node ON to the voltage level of the second power voltage V2.
The buffer circuit 100 may further include a voltage fixing circuit 130. The voltage fixing circuit 130 may receive the first control signal CON1. Based on the first control signal CON1, the voltage fixing circuit 130 may fix the voltage levels of the first node ND1 and the second node ND2 to predetermined voltage levels. The voltage fixing circuit 130 may be provided to set the voltage level of the output signal OUT when the buffer circuit 100 is deactivated. When the first control signal CON1 is disabled, the voltage fixing circuit 130 may fix the voltage level(s) of the first node ND1 and/or the pull-up control signal PU to a voltage level of the first off-voltage. When the first control signal CON1 is disabled, the voltage fixing circuit 130 may fix the voltage level(s) of the second node ND2 and/or the pull-down control signal PD to a voltage level of the second off-voltage. The voltage level of the first off-voltage may be the same as or different from the voltage level of the second off-voltage. In one embodiment, the first off-voltage may have a higher voltage level than the second off-voltage. The first off-voltage may have the voltage level corresponding to a high logic level and the second off-voltage may have the voltage level corresponding to a low logic level. The driving circuit 120 may set the output signal OUT to a high-impedance state based on the pull-up control signal PU having the voltage level of the first off-voltage and the pull-down control signal PD having the voltage level of the second off-voltage. Furthermore, as the voltage level of the first off-voltage increases and the voltage level of the second off-voltage decreases, an off-leakage current of the driving circuit 120 and the buffer circuit 100 may be reduced. In one embodiment, the first off-voltage and the second off-voltage may have the voltage level corresponding to a high logic level. The driving circuit 120 may set the output signal OUT to a low logic level based on the pull-up control signal PU and the pull-down control signal PD. In one embodiment, the first off-voltage and the second off-voltage may have the voltage level corresponding to a low logic level. The driving circuit 120 may set the output signal OUT to a high logic level based on the pull-up control signal PU and the pull-down control signal PD.
The buffer circuit 100 may further include a voltage adjusting circuit 140. The voltage adjusting circuit 140 may receive a second control signal CON2 and may be selectively activated based on the second control signal CON2. The voltage adjusting circuit 140 may be connected between the first node ND1 and the second node ND2. When the second control signal CON2 is disabled, the voltage adjusting circuit 140 may be deactivated. When the second control signal CON2 is enabled, the voltage adjusting circuit 140 may be activated, may additionally change the voltage level(s) of the first node ND1 and/or the pull-up control signal PU and may additionally change the voltage level(s) of the second node ND2 and/or the pull-down control signal PD. The voltage adjusting circuit 140 may additionally lower the voltage level of the first node ND1 and may additionally raise the voltage level of the second node ND2. The voltage adjusting circuit 140 may lower the voltage level of the first node ND1 to a voltage level lower by a third voltage level than the high boundary voltage level. The voltage level lower by the third voltage level than the high boundary voltage level may be lower than the voltage level lower by the first voltage level than the high boundary voltage level. The voltage level lower by the third voltage level than the high boundary voltage level may be high enough for the driving circuit 120 to determine as a high logic level. The voltage adjusting circuit 140 may raise the voltage level of the second node ND2 to a voltage level higher by a fourth voltage level than the low boundary voltage level. The voltage level higher by the fourth voltage level than the low boundary voltage level may be higher than the voltage level higher by the second voltage level than the low boundary voltage level. The voltage level higher by the fourth voltage level than the low boundary voltage level may be low enough for the driving circuit 120 to determine as a low logic level. The voltage adjusting circuit 140 may additionally change the swing range of the pull-up control signal PU from the first swing range to a third swing range. The third swing range may be smaller than the first swing range and may be between a voltage level, which is lower by the third voltage level than the high boundary voltage level, and the low boundary voltage level. The voltage adjusting circuit 140 may additionally change the swing range of the pull-down control signal PD from the second swing range to a fourth swing range. The fourth swing range may be smaller than the second swing range and may be between the high boundary voltage level and a voltage level, which is higher by the fourth voltage level than the low boundary voltage level.
The buffer circuit 100 may further include an input buffer 150 and an output buffer 160. The input buffer 150 may receive the input signal IN and may be connected to the driving control circuit 110. The input buffer 150 may buffer the input signal IN and may provide the buffered input signal IN to the driving control circuit 110. For example, the input buffer 150 may include an even number of inverters. The output buffer 160 may be connected to the output node ON and may receive the output signal OUT from the output node ON. The output buffer 160 may buffer the output signal OUT and may generate a final output signal FOUT. For example, the output buffer 160 may include an odd number of inverters.
The driving control circuit 110 may include a first transistor N1 and a second transistor P1. The first transistor N1 may be an N-channel MOS transistor, and the second transistor P1 may be a P-channel MOS transistor. The gate of the first transistor N1 may receive the first control signal CON1, and one of the source and drain of the first transistor N1 may receive the input signal IN while the other of the source and drain may be connected to the first node ND1. When the first control signal CON1 is enabled at a high logic level, the first transistor N1 may lower the high boundary voltage level of the input signal IN by the threshold voltage of the first transistor N1 to output the pull-up control signal PU. The first voltage level may be the threshold voltage of the first transistor N1. The voltage level of the pull-up control signal PU output from the first transistor N1 may vary between the voltage level, which is lowered by the threshold voltage of the first transistor N1 from the high boundary voltage level, and the low boundary voltage level. The gate of the second transistor P1 may receive the complementary signal CON1B of the first control signal CON1, and one of the source and drain of the second transistor P1 may receive the input signal IN while the other of the source and drain may be connected to the second node ND2. When the complementary signal CON1B of the first control signal CON1 is enabled at a low logic level, the second transistor P1 may raise the low boundary voltage level of the input signal IN by the threshold voltage of the second transistor P1 to output the pull-down control signal PD. The second voltage level may be the threshold voltage of the second transistor P1. The voltage level of the pull-down control signal PD output from the second transistor P1 may vary between the high boundary voltage level and the voltage level, which is raised by the threshold voltage of the second transistor P1 from the low boundary voltage level.
The driving circuit 120 may include a third transistor P2 and a fourth transistor N2. The third transistor P2 may be a P-channel MOS transistor, and the fourth transistor N2 may be an N-channel MOS transistor. The gate of the third transistor P2 may be connected to the first node ND1 to receive the pull-up control signal PU, the source of the third transistor P2 may receive the first power voltage V1, and the drain of the third transistor P2 may be connected to the output node ON. When the pull-up control signal PU is at a low logic level, the third transistor P2 may supply the first power voltage V1 to the output node ON to pull-up drive the output signal OUT. The gate of the fourth transistor N2 may be connected to the second node ND2 to receive the pull-down control signal PD, the source of the fourth transistor N2 may receive the second power voltage V2, and the drain of the fourth transistor N2 may be connected to the output node ON. When the pull-down control signal PD is at a high logic level, the fourth transistor N2 may allow current to flow from the output node ON to a node, to which the second power voltage V2 is provided, to pull-down drive the output signal OUT.
The voltage fixing circuit 130 may include a fifth transistor P3 and a sixth transistor N3. The fifth transistor P3 may be a P-channel MOS transistor and the sixth transistor N3 may be an N-channel MOS transistor. The gate of the fifth transistor P3 may receive the first control signal CON1. The source of the fifth transistor P3 may receive the first power voltage V1, and the drain of the fifth transistor P3 may be connected to the first node ND1. When the first control signal CON1 is disabled at a low logic level, the fifth transistor P3 may supply the first power voltage V1 to the first node ND1. The gate of the sixth transistor N3 may receive the complementary signal CON1B of the first control signal CON1. The source of the sixth transistor N3 may receive the second power voltage V2, and the drain of the sixth transistor N3 may be connected to the second node ND2. When the complementary signal CON1B of the first control signal CON1 is disabled at a high logic level, the sixth transistor N3 may supply the second power voltage V2 to the second node ND2. When the first control signal CON1 is disabled at a low logic level and the complementary signal CON1B of the first control signal CON1 is disabled at a high logic level, the fifth transistor P3 may fix the pull-up control signal PU to a high logic level and the sixth transistor N3 may fix the pull-down control signal PD to a low logic level. The driving circuit 120 may set the output signal OUT to a high-impedance state based on the pull-up control signal PU and the pull-down control signal PD. When the buffer circuit 100 is deactivated, the buffer circuit 100 may maintain the output signal OUT in a high-impedance state.
The voltage adjusting circuit 140 may include a first inverter IV1 and a second inverter IV2. An input node of the first inverter IV1 may be connected to the first node ND1 to receive the pull-up control signal PU. An output node of the first inverter IV1 may be connected to the second node ND2. The first inverter IV1 may receive the second control signal CON2 and may be activated when the second control signal CON2 is enabled. An input node of the second inverter IV2 may be connected to the output node of the first inverter IV1 and the second node ND2. The second inverter IV2 may receive the pull-down control signal PD through the second node ND2. An output node of the second inverter IV2 may be connected to the input node of the first inverter IV1 and the first node ND1. The second inverter IV2 may receive the second control signal CON2 and may be activated when the second control signal CON2 is enabled. Each current driving force of the first inverter IV1 and the second inverter IV2 may be designed to be small enough to avoid an abnormal operation. For example, the first inverter IV1 may additionally drive the second node ND2 to an extend that a voltage level, which is raised by the fourth voltage level from the low boundary voltage level, can be determined as a low logic level by the fourth transistor N2 of the driving circuit 120. The second inverter IV2 may additionally drive the first node ND1 to an extend that a voltage level, which is lowered by the third voltage level from the high boundary voltage level, can be determined as a high logic level by the third transistor P2 of the driving circuit 120.
The voltage fixing circuit 230 may include a first transistor P11 and a second transistor P12. Both the first transistor P11 and the second transistor P12 may be P-channel MOS transistors. The gate of the first transistor P11 may receive the first control signal CON1, the source of the first transistor P11 may receive the first power voltage V1 and the drain of the first transistor P11 may be connected to the first node ND1. When the first control signal CON1 is disabled at a low logic level, the first transistor P11 may supply the first power voltage V1 to the first node ND1 to drive the pull-up control signal PU to the first power voltage V1. The gate of the second transistor P12 may receive the first control signal CON1, the source of the second transistor P12 may receive the first power voltage V1 and the drain of the second transistor P12 may be connected to the second node ND2. When the first control signal CON1 is disabled at a low logic level, the second transistor P12 may supply the first power voltage V1 to the second node ND2 to drive the pull-down control signal PD to the first power voltage V1. When both the first node ND1 and the second node ND2 are fixed at the voltage level of the first power voltage V1, the driving circuit 220 may generate the output signal OUT of a low logic level. When the buffer circuit 200 is deactivated, the driving circuit 220 may keep the output signal OUT at a low logic level.
The voltage fixing circuit 330 may include a first transistor N11 and a second transistor N12. Both the first transistor N11 and the second transistor N12 may be N-channel MOS transistors. The gate of the first transistor N11 may receive the complementary signal CON1B of the first control signal CON1, the source of the first transistor N11 may receive the second power voltage V2 and the drain of the first transistor N11 may be connected to the first node ND1. When the complementary signal CON1B of the first control signal CON1 is disabled at a high logic level, the first transistor N11 may supply the second power voltage V2 to the first node ND1 to drive the pull-up control signal PU to the second power voltage V2. The gate of the second transistor N12 may receive the complementary signal CON1B of the first control signal CON1, the source of the second transistor N12 may receive the second power voltage V2 and the drain of the second transistor N12 may be connected to the second node ND2. When the complementary signal CON1B of the first control signal CON1 is disabled at a high logic level, the second transistor N12 may supply the second power voltage V2 to the second node ND2. When both the first node ND1 and the second node ND2 are fixed to the voltage level of the second power voltage V2, the driving circuit 320 may generate the output signal OUT of a high logic level. When the buffer circuit 300 is deactivated, the buffer circuit 300 may keep the output signal OUT at a high logic level.
The clock generating circuit 400 may include a first inverter 410, a second inverter 420, a third inverter 430, a fourth inverter 440, a fifth inverter 450, a sixth inverter 460, a seventh inverter 470 and an eighth inverter 480. The first to eighth inverters 410 to 480 may be tri-state inverters. The first inverter 410 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the second divisional clock signal QCK to output the first divisional clock signal ICK. The first inverter 410 may be activated when the clock signal CK is at a high logic level and the complementary clock signal CKB is at a low logic level. The first inverter 410 may invertedly drive the second divisional clock signal QCK to output the first divisional clock signal ICK. The second inverter 420 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the fourth divisional clock signal QCKB to output the third divisional clock signal ICKB. The second inverter 420 may be activated when the clock signal CK is at a high logic level and the complementary clock signal CKB is at a low logic level. The second inverter 420 may invertedly drive the fourth divisional clock signal QCKB to output the third divisional clock signal ICKB. The third inverter 430 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the second divisional clock signal QCK to output the fourth divisional clock signal QCKB. The third inverter 430 may be activated when the clock signal CK is at a high logic level and the complementary clock signal CKB is at a low logic level. The third inverter 430 may invertedly drive the second divisional clock signal QCK to output the fourth divisional clock signal QCKB. The fourth inverter 440 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the fourth divisional clock signal QCKB to output the second divisional clock signal QCK. The fourth inverter 440 may be activated when the clock signal CK is at a high logic level and the complementary clock signal CKB is at a low logic level. The fourth inverter 440 may invertedly drive the fourth divisional clock signal QCKB to output the second divisional clock signal QCK.
The fifth inverter 450 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the third divisional clock signal ICKB to output the second divisional clock signal QCK. The fifth inverter 450 may be activated when the clock signal CK is at a low logic level and the complementary clock signal CKB is at a high logic level. The fifth inverter 450 may invertedly drive the third divisional clock signal ICKB to output the second divisional clock signal QCK. The sixth inverter 460 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the first divisional clock signal ICK to output the fourth divisional clock signal QCKB. The sixth inverter 460 may be activated when the clock signal CK is at a low logic level and the complementary clock signal CKB is at a high logic level. The sixth inverter 460 may invertedly drive the first divisional clock signal ICK to output the fourth divisional clock signal QCKB. The seventh inverter 470 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the first divisional clock signal ICK to output the third divisional clock signal ICKB. The seventh inverter 470 may be activated when the clock signal CK is at a low logic level and the complementary clock signal CKB is at a high logic level. The seventh inverter 470 may invertedly drive the first divisional clock signal ICK to output the third divisional clock signal ICKB. The eighth inverter 480 may receive, as control signals, the clock signal CK and the complementary clock signal CKB and may receive the third divisional clock signal ICKB to output the first divisional clock signal ICK. The eighth inverter 480 may be activated when the clock signal CK is at a low logic level and the complementary clock signal CKB is at a high logic level. The eighth inverter 480 may invertedly drive the third divisional clock signal ICKB to output the first divisional clock signal ICK. At least one of the buffer circuits 100, 200 and 300 described in
When the clock signal CK transitions from a high logic level to a low logic level for the first time and the complementary clock signal CKB transitions from a low logic level to a high logic level for the first time, the fifth to eighth inverters 450 to 480 may be activated and the first to fourth inverters 410 to 440 may be deactivated. The fifth inverter 450 may invertedly drive the third divisional clock signal ICKB of a low logic level to output the second divisional clock signal QCK of a high logic level and the second divisional clock signal QCK may transition from a low logic level to a high logic level. The sixth inverter 460 may invertedly drive the first divisional clock signal ICK of a high logic level to output the fourth divisional clock signal QCKB of a low logic level and the fourth divisional clock signal QCKB may transition from a high logic level to a low logic level. The seventh inverter 470 may invertedly drive the first divisional clock signal ICK of a high logic level to output the third divisional clock signal ICKB of a low logic level and the third divisional clock signal ICKB may stay at a low logic level. The eighth inverter 480 may invertedly drive the third divisional clock signal ICKB of a low logic level to output the first divisional clock signal ICK of a high logic level and the first divisional clock signal ICK may stay at a high logic level.
When the clock signal CK transitions from a low logic level to a high logic level for the second time and the complementary clock signal CKB transitions from a high logic level to a low logic level for the second time, the first to fourth inverters 410 to 440 may be activated and the fifth to eighth inverters 450 to 480 may be deactivated. In the interval where the clock signal CK is at a high logic level and the complementary clock signal CKB is at a low logic level, the first inverter 410 may invertedly drive the second divisional clock signal QCK of a high logic level to output the first divisional clock signal ICK of a low logic level and the first divisional clock signal ICK may transition from a high logic level to a low logic level. The second inverter 420 may invertedly drive the fourth divisional clock signal QCKB of a low logic level to output the third divisional clock signal ICKB of a high logic level and the third divisional clock signal ICKB may transition from a low logic level to a high logic level. The third inverter 430 may invertedly drive the second divisional clock signal QCK of a high logic level to output the fourth divisional clock signal QCKB of a low logic level and the fourth divisional clock signal QCKB may stay at a low logic level. The fourth inverter 440 may invertedly drive the fourth divisional clock signal QCKB of a low logic level to output the second divisional clock signal QCK of a high logic level and the second divisional clock signal QCK may stay at a high logic level. As the clock signal CK and the complementary clock signal CKB transition repeatedly between logic levels, the clock generating circuit 400 may generate the first to fourth divisional clock signals ICK, QCK, ICKB and QCKB having a longer period than the clock signal CK and the complementary clock signal CKB and having 90° phase difference between each other. When any of the first to eighth inverters 410 to 480 includes at least one of the buffer circuits 100, 200 and 300 described with reference to
The second semiconductor apparatus 520 may be connected to the first semiconductor apparatus 510 through a plurality of buses. Each of the plurality of buses may be a signal transmission path, a link or a channel configured to transfer a signal. The plurality of buses may include a clock bus 501, a data bus 502 and so forth. The clock bus 501 may be a unidirectional bus from the first semiconductor apparatus 510 to the second semiconductor apparatus 520, and the data bus 502 may be a bidirectional bus between the first semiconductor apparatus 510 and the second semiconductor apparatus 520. The second semiconductor apparatus 520 may be connected to the first semiconductor apparatus 510 through the clock bus 501 and may receive a system clock signal SCK through the clock bus 501. The system clock signal SCK may be transmitted along with a complementary signal SCKB. The second semiconductor apparatus 520 may be connected to the first semiconductor apparatus 510 through the data bus 502 and may receive, through the data bus 502, data DQ from the first semiconductor apparatus 510 and provide, through the data bus 502, data DQ to the first semiconductor apparatus 510. The first semiconductor apparatus 510 may transmit data DQ to the second semiconductor apparatus 520 based on the system clock signal SCK and the complementary signal SCKB. The second semiconductor apparatus 520 may transmit data DQ to the first semiconductor apparatus 510 based on the system clock signal SCK and the complementary signal SCKB. Although not illustrated, the semiconductor system 500 may include a command/address bus, through which the second semiconductor apparatus 520 may be connected to the first semiconductor apparatus 510. The command/address bus may be a unidirectional bus from the first semiconductor apparatus 510 to the second semiconductor apparatus 520. The first semiconductor apparatus 510 may provide a command/address signal to the second semiconductor apparatus 520 through the command/address bus to direct the operation to be performed by the second semiconductor apparatus 520. The first semiconductor apparatus 510 may provide the second semiconductor apparatus 520 with a command/address signal in synchronization with the system clock signal SCK and the complementary signal SCKB.
The first semiconductor apparatus 510 may include a clock generating circuit 511 and a data input/output circuit 512. The clock generating circuit 511 may generate the system clock signal SCK and the complementary signal SCKB. The clock generating circuit 511 may transmit the system clock signal SCK and SCKB to the second semiconductor apparatus 520 through the clock bus 501. The clock generating circuit 511 may provide the system clock signal SCK and the complementary signal SCKB to the data input/output circuit 512. The clock generating circuit 511 may include a clock generator such as an oscillator, a phase-locked loop, a delay-locked loop, a clock divider and so forth to generate the system clock signal SCK and the complementary signal SCKB, which have a consistent frequency and toggle. The clock generating circuit 511 may include the clock generating circuit 400 illustrated in
The data input/output circuit 512 may be connected to the data bus 502. The data input/output circuit 512 may generate the data DQ based on internal data DATA1 of the first semiconductor apparatus 510 and may transmit the data DQ to the second semiconductor apparatus 520 through the data bus 502. The data input/output circuit 512 may receive the data DQ transmitted from the second semiconductor apparatus 520 through the data bus 502 and may generate the internal data DATA1 based on the data DQ. The data input/output circuit 512 may receive the system clock signal SCK and the complementary signal SCKB from the clock generating circuit 511. The data input/output circuit 512 may transmit or receive the data DQ in synchronization with the system clock signal SCK and the complementary signal SCKB. In an embodiment, the data input/output circuit 512 may be modified to receive the data DQ in synchronization with a clock signal (e.g., a data strobe signal) from the second semiconductor apparatus 520.
The semiconductor apparatus 520 may include an internal clock generating circuit 521 and a data input/output circuit 522. The internal clock generating circuit 521 may be connected to the clock bus 501 and may receive the system clock signal SCK and the complementary signal SCKB from the first semiconductor apparatus 510 through the clock bus 501. Based on the system clock signal SCK and the complementary signal SCKB, the internal clock generating circuit 521 may generate a plurality of internal clock signals INCK. The plurality of internal clock signals INCK may have the same frequency as the system clock signal SCK and the complementary signal SCKB. In an embodiment, the plurality of internal clock signals INCK may have a lower frequency than the system clock signal SCK and the complementary signal SCKB. In an embodiment, the plurality of internal clock signals INCK may have a higher frequency than the system clock signal SCK and the complementary signal SCKB. The internal clock generating circuit 521 may buffer the system clock signal SCK and the complementary signal SCKB or divide/multiply the frequency of the system clock signal SCK and the complementary signal SCKB to generate the plurality of internal clock signals INCK. To divide the frequency of the system clock signal SCK and the complementary signal SCKB for generating the plurality of internal clock signals INCK, the internal clock generating circuit 521 may include the clock generating circuit 400 illustrated in
The data input/output circuit 522 may be connected to the data bus 502 to receive, through the data bus 502, the data DQ transmitted from the first semiconductor apparatus 510 or transmit, through the data bus 502, the data DQ to the first semiconductor apparatus 510. The data input/output circuit 522 may generate, based on internal data DATA2 of the second semiconductor apparatus 520, the data DQ and may transmit the data DQ to the first semiconductor apparatus 510 through the data bus 502. The data input/output circuit 522 may receive the data DQ transmitted from the first semiconductor apparatus 510 and may generate the internal data DATA2 based on the data DQ. The data input/output circuit 522 may receive the plurality of internal clock signals INCK generated by the internal clock generating circuit 521. In synchronization with the plurality of internal clock signals INCK, the data input/output circuit 522 may provide the data DQ to the first semiconductor apparatus 510 and may receive the data DQ transmitted from the first semiconductor apparatus 510.
The differential buffer circuit 600 may include a first buffer circuit 611 and a second buffer circuit 621. The first buffer circuit 611 may receive the first input signal IN1 and may buffer the first input signal IN1 to generate the first output signal OUT1. The first buffer circuit 611 may receive a first control signal CON1 and a second control signal CON2. Based on the first control signal CON1, the first buffer circuit 611 may reduce a swing range of the first input signal IN1 to generate a first pull-up control signal swinging within a first swing range and a first pull-down control signal swinging within a second swing range. The first swing range may be formed in a region of a lower voltage level and the second swing range may be formed in a region of a higher voltage level, the second swing range being higher than the first swing range. The first buffer circuit 611 may pull-up drive the first output signal OUT1 based on the first pull-up control signal and may pull-down drive the first output signal OUT1 based on the first pull-down control signal. Based on the second control signal CON2, the first buffer circuit 611 may further adjust the first swing range to generate the first pull-up control signal swinging within a third swing range. Based on the second control signal CON2, the first buffer circuit 611 may further adjust the second swing range to generate the first pull-down control signal swinging within a fourth swing range. The third swing range may be smaller than the first swing range and the fourth swing range may be smaller than the second swing range. At least one of the buffer circuits 100, 200 and 300 illustrated in
The second buffer circuit 621 may receive the second input signal IN2 and may buffer the second input signal IN2 to generate the second output signal OUT2. The second buffer circuit 621 may receive the first control signal CON1 and the second control signal CON2. Based on the first control signal CON1, the second buffer circuit 621 may reduce the swing range of the second input signal IN2 to generate a second pull-up control signal swinging within the first swing range and a second pull-down control signal that swings within the second swing range. The second buffer circuit 621 may pull-up drive the second output signal OUT2 based on the second pull-up control signal and may pull-down drive the second output signal OUT2 based on the second pull-down control signal. Based on the second control signal CON2, the second buffer circuit 621 may additionally adjust the first swing range to generate the second pull-up control signal swinging within the third swing range. Based on the second control signal CON2, the second buffer circuit 621 may additionally adjust the second swing range to generate the second pull-down control signal swinging within the fourth swing range. At least one of the buffer circuits 100, 200 and 300 illustrated in
The differential buffer circuit 600 may further include a first input buffer 612 and a second input buffer 622. The first input buffer 612 may buffer the first input signal IN1 and may provide the buffered first input signal IN1 to the first buffer circuit 611. For example, the first input buffer 612 may include an even number of inverters. The second input buffer 622 may buffer the second input signal IN2 and may provide the buffered second input signal IN2 to the second buffer circuit 621. For example, the second input buffer 622 may include an even number of inverters.
The differential buffer circuit 600 may further include at least a first inverter 613, a second inverter 623 and a first latch 631. The first inverter 613 may receive the first output signal OUT1 and may invertedly drive the first output signal OUT1. The second inverter 623 may receive the second output signal OUT2 and may invertedly drive the second output signal OUT2. The first latch 631 may be connected between output nodes of the first inverter 613 and the second inverter 623. The first latch 631 may receive the output signals of the first inverter 613 and the second inverter 623 to keep the voltage levels of the output signals of the first inverter 613 and the second inverter 623. The first latch 631 may invertedly drive the output signal of the first inverter 613 and may maintain, based on the invertedly driven signal, the voltage level of the output signal of the second inverter 623. The first latch 631 may invertedly drive the output signal of the second inverter 623 to maintain, based on the invertedly driven signal, the voltage level of the output signal of the first inverter 613.
The differential buffer circuit 600 may further include a third inverter 614, a fourth inverter 624, a second latch 632, a fifth inverter 615 and a sixth inverter 625. The third inverter 614 may receive the output signal of the first inverter 613 and may invertedly drive the output signal of the first inverter 613. The fourth inverter 624 may receive the output signal of the second inverter 623 and may invertedly drive the output signal of the second inverter 623. The second latch 632 may be connected between output nodes of the third inverter 614 and the fourth inverter 624. The second latch 632 may receive the output signals of the third inverter 614 and the fourth inverter 624 to keep the voltage levels of the output signals of the third inverter 614 and the fourth inverter 624. The second latch 632 may invertedly drive the output signal of the third inverter 614 and may maintain, based on the invertedly driven signal, the voltage level of the output signal of the fourth inverter 624. The second latch 632 may invertedly drive the output signal of the fourth inverter 624 and may maintain, based on the invertedly driven signal, the voltage level of the output signal of the third inverter 614. The fifth inverter 615 may invertedly drive the output signal of the third inverter 614 to generate a first final output signal FOUT1. The sixth inverter 625 may invertedly drive the output signal of the fourth inverter 624 to generate a second final output signal FOUT2. The number of inverters and latches included in the differential buffer circuit 600 will not be limited as illustrated in
The buffer circuit 700 may include a first driving control circuit 710, a second driving control circuit 720 and a driving circuit 730. The first driving control circuit 710 may receive the first input signal IN1 and the first selection signal SEL1 to generate the pull-up control signal PU and the pull-down control signal PD. The first driving control circuit 710 may output the pull-up control signal PU through the first node ND1 and the pull-down control signal PD through the second node ND2. When the first selection signal SEL1 is enabled, the first driving control circuit 710 may change the voltage level of the first input signal IN1 to generate the pull-up control signal PU and the pull-down control signal PD. When the first selection signal SEL1 is enabled, the first driving control circuit 710 may lower the high boundary voltage level of the first input signal IN1 by a first voltage level to generate the pull-up control signal PU and may raise the low boundary voltage level of the first input signal IN1 by a second voltage level to generate the pull-down control signal PD. The first driving control circuit 710 may convert the swing range of the first input signal IN1 to generate the pull-up control signal PU swinging within a first swing range and the pull-down control signal PD swinging within a second swing range. Both the first swing range and the second swing range may be smaller than the swing range of the first input signal IN1. The first swing range may be formed in a region of a lower voltage level and the second swing range may be formed in a region of a higher voltage level than the first swing range. The first swing range may be between a voltage level, which is lower by the first voltage level than the high boundary voltage level, and the low boundary voltage level. The second swing range may be between the high boundary voltage level and a voltage level, which is higher by the second voltage level than the low boundary voltage level.
The second driving control circuit 720 may receive the second input signal IN2 and the second selection signal SEL2 to generate the pull-up control signal PU and the pull-down control signal PD. When the second selection signal SEL2 is enabled, the second driving control circuit 720 may change the voltage level of the second input signal IN2 to generate the pull-up control signal PU and the pull-down control signal PD. The second driving control circuit 720 may output the pull-up control signal PU through the first node ND1 and the pull-down control signal PD through the second node ND2. When the second selection signal SEL2 is enabled, the second driving control circuit 720 may lower the high boundary voltage level of the second input signal IN2 by the first voltage level to generate the pull-up control signal PU and may raise the low boundary voltage level of the second input signal IN2 by the second voltage level to generate the pull-down control signal PD. The second driving control circuit 720 may generate the pull-up control signal PU swinging within the first swing range and the pull-down control signal PD swinging within the second swing range.
The driving circuit 730 may receive the pull-up control signal PU and the pull-down control signal PD, which are generated from one of the first driving control circuit 710 and the second driving control circuit 720, to generate the output signal OUT. The driving circuit 730 may pull-up drive the output node ON based on the pull-up control signal PU and may pull-down drive the output node ON based on the pull-down control signal PD. The driving circuit 730 may output the output signal OUT through the output node ON. The driving circuit 730 may receive a first power voltage V1 and a second power voltage V2. The first power voltage V1 may have a higher voltage level than the second power voltage V2. For example, the first power voltage V1 may be the operating power voltage of the buffer circuit 700 and the second power voltage V2 may be the ground voltage. The driving circuit 730 may drive, based on the pull-up control signal PU, the output node ON to the voltage level of the first power voltage V1. The driving circuit 730 may drive, based on the pull-down control signal PD, the output node ON to the voltage level of the second power voltage V2.
The buffer circuit 700 may further include a voltage adjusting circuit 740. The voltage adjusting circuit 740 may receive a control signal CON and may be selectively activated based on the control signal CON. The voltage adjusting circuit 740 may be connected between the first node ND1 and the second node ND2. When the control signal CON is disabled, the voltage adjusting circuit 740 may be deactivated. When the control signal CON is enabled, the voltage adjusting circuit 740 may be activated and may additionally adjust the voltage levels of the pull-up control signal PU and the pull-down control signal PD. The voltage adjusting circuit 740 may additionally lower the voltage level of the pull-up control signal PU and may additionally raise the voltage level of the pull-down control signal PD. The voltage adjusting circuit 740 may change the voltage level of the pull-up control signal PU to a voltage level lower by a third voltage level than the high boundary voltage level. The voltage level lower by the third voltage level than the high boundary voltage level may be lower than the voltage level lower by the first voltage level than the high boundary voltage level. The voltage adjusting circuit 740 may change the voltage level of the pull-down control signal PD to a voltage level higher by a fourth voltage level than the low boundary voltage level. The voltage level higher by the fourth voltage level than the low boundary voltage level may be higher than the voltage level higher by the second voltage level than the low boundary voltage level. The voltage adjusting circuit 740 may additionally convert the swing range of the pull-up control signal PU from the first swing range to a third swing range. The third swing range may be smaller than the first swing range and may be between a voltage level, which is lower by the third voltage level than the high boundary voltage level, and the low boundary voltage level. The voltage adjusting circuit 740 may additionally convert the swing range of the pull-down control signal PD from the second swing range to a fourth swing range. The fourth swing range may be smaller than the second swing range and may be between the high boundary voltage level and a voltage level, which is higher by the fourth voltage level than the low boundary voltage level.
The buffer circuit 700 may further include an output buffer 750. The output buffer 750 may be connected to the output node ON and may receive the output signal OUT. The output buffer 750 may invertedly drive the output signal OUT to generate the final output signal FOUT. For example, the output buffer 750 may include an odd number of inverters.
The first driving control circuit 710 may include a first transistor N21 and a second transistor P21. The first transistor N21 may be an N-channel MOS transistor and the second transistor P21 may be a P-channel MOS transistor. The gate of the first transistor N21 may receive the first selection signal SEL1 and one of the source and the drain of the first transistor N21 may receive the first input signal IN1 and the other of the source and the drain of the first transistor N21 may be connected to the first node ND1. When the first selection signal SEL1 is enabled at a high logic level, the first transistor N21 may lower the high boundary voltage level of the first input signal IN1 by the threshold voltage of the first transistor N21 to generate the pull-up control signal PU having the lowered voltage level. The gate of the second transistor P21 may receive the complementary signal SEL1B of the first selection signal SEL1 and one of the source and drain of the second transistor P21 may receive the first input signal IN1 and the other of the source and drain of the second transistor P21 may be connected to the second node ND2. When the complementary signal SEL1B of the first selection signal SEL1 is enabled at a low logic level, the second transistor P21 may raise the low boundary voltage level of the first input signal IN1 by the threshold voltage of the second transistor P21 to generate the pull-down control signal PD having the raised voltage level.
The second driving control circuit 720 may include a third transistor N22 and a fourth transistor P22. The third transistor N22 may be an N-channel MOS transistor and the fourth transistor P22 may be a P-channel MOS transistor. The gate of the third transistor N22 may receive the second selection signal SEL2 and one of the source and drain of the third transistor N22 may receive the second input signal IN2 and the other of the source and drain of the third transistor N22 may be connected to the first node ND1. When the second selection signal SEL2 is enabled at a high logic level, the third transistor N22 may lower the high boundary voltage level of the second input signal IN2 by the threshold voltage of the third transistor N22 to generate the pull-up control signal PU having the lowered voltage level. The gate of the fourth transistor P22 may receive the complementary signal SEL2B of the second selection signal SEL2 and one of the source and drain of the fourth transistor P22 may receive the second input signal IN2 and the other of the source and drain of the fourth transistor P22 may be connected to the second node ND2. When the complementary signal SEL2B of the second selection signal SEL2 is enabled at a low logic level, the fourth transistor P22 may raise the low boundary voltage level of the second input signal IN2 by the threshold voltage of the fourth transistor P22 to generate the pull-down control signal PD having the raised voltage level.
The driving circuit 730 may include a fifth transistor P23 and a sixth transistor N23. The fifth transistor P23 may be a P-channel MOS transistor and the sixth transistor N23 may be an N-channel MOS transistor. The gate of the fifth transistor P23 may be connected to the first node ND1 to receive the pull-up control signal PU, the source of the fifth transistor P23 may receive the first power voltage V1 and the drain of the fifth transistor P23 may be connected to the output node ON. When the pull-up control signal PU is at a low logic level, the fifth transistor P23 may pull-up drive the output signal OUT by supplying the first power voltage V1 to the output node ON. The gate of the sixth transistor N23 may be connected to the second node ND2 to receive the pull-down control signal PD, the source of the sixth transistor N23 may receive the second power voltage V2 and the drain of the sixth transistor N23 may be connected to the output node ON. When the pull-down control signal PD is at a high logic level, the sixth transistor N23 may pull-down drive the output signal OUT by allowing current to flow from the output node ON to the node, to which the second power voltage V2 is supplied.
The voltage adjusting circuit 740 may include a first inverter IV21 and a second inverter IV22. The input node of the first inverter IV21 may be connected to the first node ND1 to receive the pull-up control signal PU. The output node of the first inverter IV21 may be connected to the second node ND2. The first inverter IV21 may receive the control signal CON and may be activated when the control signal CON is enabled. The input node of the second inverter IV22 may be connected to the output node of the first inverter IV21 and the second node ND2. The second inverter IV22 may receive the pull-down control signal PD through the second node ND2. The output node of the second inverter IV22 may be connected to the input node of the first inverter IV21 and the first node ND1. The second inverter IV22 may receive the control signal CON and may be activated when the control signal CON is enabled.
When the first selection signal SEL1 is enabled, the second driving control circuit 720 may be deactivated and the first driving control circuit 710 may generate, from the first input signal IN1, the pull-up control signal PU and the pull-down control signal PD. The first driving control circuit 710 may change the voltage level of the first input signal IN1 to generate the pull-up control signal PU swinging within the first swing range and the pull-down control signal PD swinging within the second swing range. The driving circuit 730 may pull-up drive the output node ON when the pull-up control signal PU is at a low logic level and may pull-down drive the output node ON when the pull-down control signal PD is at a high logic level, thereby generating the output signal OUT. The output buffer 750 may invertedly drive the output signal OUT to generate the final output signal FOUT of a logic level corresponding to the first input signal IN1. Because the first driving control circuit 710 generates the pull-up control signal PU having a voltage level lower than the high boundary voltage level of the first input signal IN1, the time point when the pull-up control signal PU transitions from a high logic level to a low logic level may become earlier. Because the first driving control circuit 710 generates the pull-down control signal PD having a voltage level higher than the low boundary voltage level of the first input signal IN1, the time point when the pull-down control signal PD transitions from a low logic level to a high logic level may become earlier. As the time points for the logic levels of the pull-up control signal PU and the pull-down control signal PD to transition become earlier, the output node ON may be driven more quickly and the buffer circuit 700 may reduce the time amount required to generate the output signal OUT from the first input signal IN1. When the control signal CON is enabled together, the voltage adjusting circuit 740 may be activated to additionally lower the voltage level of the pull-up control signal PU and to additionally raise the voltage level of the pull-down control signal PD. Accordingly, the time points for the logic levels of the pull-up control signal PU and the pull-down control signal PD to transition become further earlier and the operation speed of the buffer circuit 700 may become further faster.
When the second selection signal SEL2 is enabled, the first driving control circuit 710 may be deactivated and the second driving control circuit 720 may generate, from the second input signal IN2, the pull-up control signal PU and the pull-down control signal PD. The second driving control circuit 720 may change the voltage level of the second input signal IN2 to generate the pull-up control signal PU swinging within the first swing range and the pull-down control signal PD swinging within the second swing range. The driving circuit 730 may pull-up drive the output node ON when the pull-up control signal PU is at a low logic level to and may pull-down drive the output node ON when the pull-down control signal PD is at a high logic level, thereby generating the output signal OUT. The output buffer 750 may invertedly drive the output signal OUT to generate the final output signal FOUT of a logic level corresponding to the second input signal IN2. Because the second driving control circuit 720 generates the pull-up control signal PU having a voltage level lower than the high boundary voltage level of the second input signal IN2, the time point when the pull-up control signal PU transitions from a high logic level to a low logic level may become earlier. Because the second driving control circuit 720 generates the pull-down control signal PD having a voltage level higher than the low boundary voltage level of the second input signal IN2, the time point when the pull-down control signal PD transitions from a low logic level to a high logic level may become earlier. As the time points for the logic levels of the pull-up control signal PU and the pull-down control signal PD to transition become earlier, the output node ON may be driven more quickly and the buffer circuit 700 may reduce the time amount required to generate the output signal OUT from the second input signal IN2. When the control signal CON is enabled together, the voltage adjusting circuit 740 may be activated to additionally lower the voltage level of the pull-up control signal PU and to additionally raise the voltage level of the pull-down control signal PD. Accordingly, the time points for the logic levels of the pull-up control signal PU and the pull-down control signal PD to transition become further earlier and the operation speed of the buffer circuit 700 may become further faster.
While certain embodiments have been described above, it will be understood by those skilled in the art that the embodiments described are by way of example only. Accordingly, the buffer circuit, clock generating circuit, semiconductor apparatus, and semiconductor system using the same should not be limited based on the described embodiments. Rather, the buffer circuit, clock generating circuit, semiconductor apparatus, and semiconductor system using the same described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0053381 | Apr 2023 | KR | national |
