Number | Name | Date | Kind |
---|---|---|---|
5254883 | Horowitz et al. | Oct 1993 | A |
5376833 | Chloupek | Dec 1994 | A |
5489862 | Risinger et al. | Feb 1996 | A |
5498990 | Leung et al. | Mar 1996 | A |
5606717 | Farmwald et al. | Feb 1997 | A |
5684421 | Chapman et al. | Nov 1997 | A |
5831929 | Manning | Nov 1998 | A |
5838177 | Keeth | Nov 1998 | A |
5852378 | Keeth | Dec 1998 | A |
5860080 | James et al. | Jan 1999 | A |
5870347 | Keeth et al. | Feb 1999 | A |
5872736 | Keeth | Feb 1999 | A |
5910920 | Keeth | Jun 1999 | A |
5920518 | Harrison et al. | Jul 1999 | A |
5926034 | Seyyedy | Jul 1999 | A |
5935263 | Keeth et al. | Aug 1999 | A |
5940608 | Manning | Aug 1999 | A |
5940609 | Harrison | Aug 1999 | A |
5946244 | Manning | Aug 1999 | A |
5946260 | Manning | Aug 1999 | A |
5949254 | Keeth | Sep 1999 | A |
5959929 | Cowles et al. | Sep 1999 | A |
5963502 | Watanabe et al. | Oct 1999 | A |
5986955 | Siek et al. | Nov 1999 | A |
5996043 | Manning | Nov 1999 | A |
6000022 | Manning | Dec 1999 | A |
6009487 | Davis et al. | Dec 1999 | A |
6011732 | Harrison et al. | Jan 2000 | A |
6014759 | Manning | Jan 2000 | A |
6016282 | Keeth | Jan 2000 | A |
6026050 | Baker et al. | Feb 2000 | A |
6026051 | Keeth et al. | Feb 2000 | A |
6029250 | Keeth | Feb 2000 | A |
6029252 | Manning | Feb 2000 | A |
6031787 | Jeddeloh | Feb 2000 | A |
6032220 | Martin et al. | Feb 2000 | A |
6032274 | Manning | Feb 2000 | A |
6034878 | Osaka et al. | Mar 2000 | A |
6047248 | Georgious et al. | Apr 2000 | A |
6094704 | Martin et al. | Jul 2000 | A |
6094727 | Manning | Jul 2000 | A |
6101197 | Keeth et al. | Aug 2000 | A |
6101612 | Jeddeloh | Aug 2000 | A |
6108795 | Jeddeloh | Aug 2000 | A |
6321282 | Horowitz et al. | Nov 2001 | B1 |
6462591 | Garrett, Jr. et al. | Oct 2002 | B2 |
Entry |
---|
SLDRAM Consortium, 400 Mb/s/pin SLDRAM, 1997 Draft/Advance Data Sheet (pp. 1-59). |
Song et al., “NRZ Timing Recovery Technique for Band-Limited Channels,” IEEE Journal of Solid-State Circuits, vol. 32, No. 4, pp514-520, (Apr. 1997). |
Chang et al., “A 2Gb/s/pin CMOS Asymmetric Serial Link,” Computer Science Laboratory, Stanford University. |
Dally and Poulton, “Digital Systems Engineering,” (1998), pp. 361-366. |
Intel, “440BX AGPset: 82443BX Host Bridge/Controller Datasheet,” (Apr. 1998). |
Poulton, John, “Signaling in High-performance Memory Systems,” ISSCC 1999. |
Designline, (Micron Technology Inc.) vol. 8, Issue 3 3Q99 (pp. 1-24). |