Claims
- 1. A method for invalidating a line in a cache block in a cache memory during a cache write operation, said cache block comprising two or more lines of data sharing a common block address, wherein an unsuccessful attempted read of data in said cache results in the generation of a cache miss request, in response to which cache miss request data is fetched to fill a block in said cache, and wherein two or more of said cache miss requests may be pending at a given time, comprising the steps of:
- providing a valid bit for each line in said cache block, said valid bit indicating whether valid data exists in said line;
- generating a read miss request with respect to one or more lines in said cache block, including a tag and block address and an invalidation control signal, said invalidation control signal causing the setting to invalid of the validity bits for those lines in said cache block other than said one or more lines for which said read miss request is generated when said invalidation control signal is on, and said invalidation control signal preventing the resetting of the validity bits for those lines in said cache block other than said one or more lines for which said read miss request is generated when said invalidation control signal is off;
- for said read miss request comparing said tag and block address of said read miss request against the tag and block address of other, pending read miss requests; and
- if a match is found in said step of comparing setting said line invalidation control signal off for said read miss request, but
- if a match is not found in said step of comparing setting said line invalidation control signal on for said read miss request.
Parent Case Info
This application is a Continuation of application Ser. No. 08/136,513, filed Oct. 12, 1993, now abandoned.
US Referenced Citations (31)
Foreign Referenced Citations (4)
Number |
Date |
Country |
0242010A1 |
Oct 1987 |
EPX |
R130467.4 |
Jul 1993 |
DEX |
22285998 |
Aug 1990 |
GBX |
2260631 |
Apr 1993 |
GBX |
Non-Patent Literature Citations (5)
Entry |
IBM Technical Disclosure Bulletin Double Frequency Clock Generator) Aug. 1991 Nishihara. |
"Advanced Clock Controller Cuts Power Needs, Size of Static CMOS Systems" (Electronic Design Oct. 04, 1984) Curtis A Mroz & Walt Niewierski Oct. 1984. |
"Clocking Subsystems Pace High Performance Logic" (Computer Design Nov. 1, 1987) Jacob Shuhani & Don Draper Nov. 1987. |
Microprocessor and Peripheral Handbook vol. 1 Microprocessor Intel 1987. |
Minoru et al, "Invalidation Processing System for Cache" Memory.sup.3, Jan. 31, 1900 (JP 9021095) Japanese Abstract. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
136513 |
Oct 1993 |
|